Light emitting diode and method of manufacturing and reworking the same

Abstract

The present disclosure provides a light emitting diode and a preparation method and a rework method thereof, and belongs to the technical field of optoelectronic manufacturing. The light emitting diode comprises an n-type layer, an active layer and a p-type layer which are stacked in sequence, the p-type layer comprises a first p-type sub-layer, a heavily doped tunnel junction layer and a second p-type sub-layer which are stacked in sequence, and the heavily doped tunnel junction layer comprises an n-type doped semiconductor layer. The embodiment of the present disclosure can improve the problem that the working voltage of the light emitting diode after rework is prone to increase.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode and its preparation and rework methods. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption. They are widely used in lighting, displays, signal lights, backlights, toys, and other fields.

[0003] In related technologies, light-emitting diodes (LEDs) typically consist of an n-type layer, an active layer, and a p-type layer stacked sequentially on a substrate. The p-type layer is generally p-type conductive through magnesium doping (Mg), and a transparent conductive layer and metal electrodes are deposited on top to form ohmic contacts. During chip manufacturing, deviations in processes such as photolithography, etching, or deposition often necessitate rework. The rework process generally includes steps such as removing the dielectric or metal layer from defective areas, cleaning the exposed p-type layer surface, and re-depositing the metal electrodes.

[0004] However, the forward operating voltage (Vf) of the LED increases significantly after rework. The main reasons include: first, surface damage; plasma etching or chemical cleaning during rework can disrupt the lattice of the p-type layer, creating defects; second, surface contamination and oxidation; the exposed p-type layer surface is prone to forming a gallium oxide (Ga2O3) insulating layer or adsorbing contaminants, thus disrupting the ohmic contact between the metal and the semiconductor; and third, Mg acceptor passivation; hydrogen (H) introduced in subsequent processes easily combines with Mg to form a Mg-H neutral complex, leading to a decrease in hole concentration and an increase in both the bulk resistance and contact resistance of the p-type layer. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) and its fabrication and rework methods, which can improve the problem of the LED's operating voltage easily increasing after rework. The technical solution is as follows: On one hand, embodiments of this disclosure provide a light-emitting diode, the light-emitting diode comprising an n-type layer, an active layer and a p-type layer stacked sequentially, the p-type layer comprising a first p-type sub-layer, a heavily doped tunnel junction layer and a second p-type sub-layer stacked sequentially, the heavily doped tunnel junction layer comprising an n-type doped semiconductor layer.

[0006] In one implementation of this disclosure, the heavily doped tunnel junction layer includes N + -GaN layer.

[0007] In another implementation of this disclosure, the N +-The GaN layer is Si-doped, and the N + The Si doping concentration of the GaN layer is 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 .

[0008] In another implementation of this disclosure, the N + - The thickness of the GaN layer ranges from 5 nm to 50 nm.

[0009] In another implementation of this disclosure, both the first p-type sublayer and the second p-type sublayer are Mg-doped, and the Mg doping concentration of the first p-type sublayer is greater than or equal to the Mg doping concentration of the second p-type sublayer.

[0010] In another implementation of this disclosure, the Mg doping concentration of the first p-type sublayer is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The Mg doping concentration of the second p-type sublayer is 5 × 10⁻⁶. 18 cm -3 Up to 1×10 19 cm -3 .

[0011] In another implementation of this disclosure, the thickness of the first p-type sublayer is 50 nm to 200 nm, and the thickness of the second p-type sublayer is 10 nm to 100 nm.

[0012] In another implementation of this disclosure, both the first p-type sublayer and the second p-type sublayer include a p-type GaN layer.

[0013] On the other hand, embodiments of this disclosure also provide a method for fabricating a light-emitting diode, the method comprising: forming an n-type layer on a substrate; forming an active layer on the n-type layer; forming a p-type layer on the active layer, the p-type layer comprising a first p-type sublayer, a heavily doped tunnel junction layer and a second p-type sublayer stacked sequentially, the heavily doped tunnel junction layer comprising an n-type doped semiconductor layer.

[0014] In another aspect, embodiments of this disclosure also provide a method for reworking a light-emitting diode (LED). The reworking method is used to rework the LED as described above, wherein the LED further includes a functional film layer located on the p-type layer. The reworking method includes: removing the functional film layer to expose a second p-type sub-layer of the p-type layer; cleaning the surface of the second p-type sub-layer; and performing rapid thermal annealing on the LED in a temperature range of 400°C to 800°C for a duration of 10 seconds to 10 minutes.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The light-emitting diode provided in this embodiment is constructed by sequentially stacking a first p-type sublayer, a heavily doped tunnel junction layer (n-type doped semiconductor layer), and a second p-type sublayer within a p-type layer; that is, an n-type doped semiconductor layer is pre-embedded inside a p-type GaN layer. Firstly, the heavily doped tunnel junction layer, with its extremely high n-type impurity concentration, compresses the depletion region width to the nanometer scale, allowing charge carriers to pass through the extremely thin barrier via quantum tunneling. + -P + The interface forms a low-resistance tunneling path, and this mechanism itself is the core way to achieve low-resistance ohmic contact.

[0016] Secondly, in chip manufacturing rework scenarios, due to deviations in photolithography, etching, etc., the defective area dielectric / metal needs to be removed and the electrode redeposited. Conventional processes will cause a sharp increase in contact resistance and bulk resistance, and an increase in forward voltage Vf due to lattice damage on the surface of the second p-type sublayer, Ga2O3 oxidation insulation, or Mg-H passivation. However, the buried layer heavily doped tunnel junction of this disclosure is located below the second p-type sublayer. The rework cleaning and etching only affect the surface second p-type sublayer. The integrity of the heavily doped tunnel junction is not affected by the surface process state, so the vertical low-resistance channel is still retained.

[0017] Furthermore, while the subsequent annealing step repairs the surface damage of the second p-type sublayer and activates some Mg acceptors, the pre-embedded heavily doped tunnel junction provides a tunneling path for electrons injected by the metal electrode, unaffected by the reworked surface condition. Electrons can tunnel through the even highly resistive second p-type sublayer, directly reaching the heavily doped tunnel junction, and then recombine with holes provided by the first p-type sublayer on the active region side, thereby bypassing the damage and oxidation region caused by rework and suppressing the abnormal rise in forward voltage Vf. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 2 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure.

[0020] The markings in the diagram are explained as follows: 10. Substrate; 21. Nucleation layer; 22. Buffer layer; 30. n-type layer; 40. Active layer; 50. p-type layer; 51. First p-type sublayer; 52. Heavily doped tunnel junction layer; 53. Second p-type sublayer; 54. p-type AlGaN layer. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0023] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. Figure 1 As shown, the light-emitting diode includes an n-type layer 30, an active layer 40 and a p-type layer 50 stacked in sequence. The p-type layer 50 includes a first p-type sub-layer 51, a heavily doped tunnel junction layer 52 and a second p-type sub-layer 53 stacked in sequence. The heavily doped tunnel junction layer 52 includes an n-type doped semiconductor layer.

[0024] The light-emitting diode provided in this embodiment is constructed by sequentially stacking a first p-type sublayer 51, a heavily doped tunnel junction layer 52 (n-type doped semiconductor layer), and a second p-type sublayer 53 within a p-type layer 50, i.e., pre-burying an n-type doped semiconductor layer inside the p-type GaN. Firstly, the heavily doped tunnel junction layer 52, with its extremely high n-type impurity concentration, compresses the depletion region width to the nanometer scale, allowing charge carriers to pass through the extremely thin barrier via quantum tunneling. + -P +The interface forms a low-resistance tunneling path, and this mechanism itself is the core way to achieve low-resistance ohmic contact.

[0025] Secondly, in chip manufacturing rework scenarios, due to deviations in photolithography, etching, etc., the defective area dielectric / metal needs to be removed and the electrode redeposited. Conventional processes will cause a sharp increase in contact resistance and bulk resistance, and an increase in forward voltage Vf due to lattice damage on the surface of the second p-type sublayer 53, Ga2O3 oxidation insulation, or Mg-H passivation. However, the buried layer heavily doped tunnel junction 52 of this disclosure is located below the second p-type sublayer 53. The rework cleaning and etching only affect the surface second p-type sublayer 53. The integrity of the heavily doped tunnel junction 52 is not affected by the surface process state, so it still retains the vertical low-resistance channel.

[0026] Furthermore, subsequent annealing steps can be used to repair surface damage in the second p-type sublayer 53 and activate some Mg acceptors. This pre-embedded heavily doped tunnel junction 52 provides a tunneling path for electrons injected by the metal electrode, unaffected by the reworked surface condition. Electrons can tunnel through the even highly resistive second p-type sublayer 53, directly reaching the heavily doped tunnel junction 52, and then recombine with holes provided by the first p-type sublayer 51 on the active region side, thus bypassing the damage and oxidation region caused by rework and suppressing the abnormal rise in forward voltage Vf.

[0027] Optionally, the heavily doped tunnel junction layer 52 includes N + -GaN layer.

[0028] In this embodiment of the disclosure, heavily Si-doped N is embedded inside the p-type layer 50. + -GaN tunnel junction (i.e., N) + -P + (Structure). Before rework, the current is transported laterally through the second p-type sublayer 53 and then longitudinally through the heavily doped Si layer; even if the surface second p-type sublayer 53 fails due to etching, oxidation, or Mg-H passivation after rework, the buried N + The tunnel junction of the GaN layer / first p-type sublayer 51 remains intact, providing electrons with a low-resistance tunneling path unaffected by the reworked surface condition, bypassing the damaged region and suppressing voltage rise.

[0029] Due to N + The GaN layer significantly improves the device's tolerance to surface conditions (damage, oxidation, passivation) of the second p-type sublayer 53. This eliminates the need for extremely stringent cleaning and etching conditions during rework, reducing process control complexity and improving rework yield. Furthermore, the built-in N... + The GaN layer also avoids potential damage caused by excessive rework in pursuit of surface cleanliness; and subsequent annealing can repair the surface of the second p-type sublayer 53 and activate some Mg, reducing thermal stress and degradation caused by resistance surge, which is beneficial to reliability.

[0030] Optionally, N+ -The GaN layer is Si-doped, and N + The Si doping concentration of the GaN layer is 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 .

[0031] N + - The GaN layer serves as the n-type side of the heavily doped tunnel junction, with a Si doping concentration of 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 The doping range can significantly compress the depletion region width formed with the first p-type sublayer 51, allowing electrons to cross the barrier through quantum tunneling rather than thermal emission. This provides a low-resistance path for electrons injected into the metal electrode that is unaffected by damage, oxidation, or Mg-H passivation of the surface second p-type sublayer 53, fundamentally suppressing the rise of the forward voltage Vf.

[0032] For example, N + The Si doping concentration of the GaN layer is 5 × 10⁻⁶. 20 cm -3 .

[0033] Optionally, N + - The thickness of the GaN layer ranges from 5 nm to 50 nm.

[0034] In this embodiment of the disclosure, N + The lower limit of the GaN layer thickness is 5nm, which is close to the critical point for tunneling activation, but with a 1×10⁻⁶ layer... 19 cm -3 Up to 1×10 21 cm -3 Si doping can still form an effective low-resistivity path; if the thickness is less than 5nm, the barrier width is insufficient to compensate and the tunneling is weak. After rework, it cannot bypass the second p-type sublayer 53 damage region, and Vf suppression fails.

[0035] N + The GaN layer is located beneath the second p-type sublayer 53. Rework etching / cleaning only damages the surface layer. A thickness within 50nm provides sufficient volume for heavy doping to compress the depletion region while avoiding process control issues. A thickness in the 5nm to 50nm range balances damage protection and tunneling requirements, allowing electrons to tunnel from the metal through the second p-type sublayer 53 to the N-type layer after subsequent annealing. + - The GaN layer recombines with holes in the first p-type sublayer 51 to suppress the increase in rework voltage.

[0036] N + The upper limit for the thickness of the GaN layer is 50nm. +- When the GaN layer exceeds 50nm, the absorption of free carriers will cause light loss, and the highly doped thick layer will prolong the longitudinal crossing distance of holes from the first p-type sublayer 51 to the active region, increase the bulk resistance, and weaken the benefits of the tunnel junction bypassing the surface failure region.

[0037] Optionally, both the first p-type sublayer 51 and the second p-type sublayer 53 are Mg-doped, and the Mg doping concentration of the first p-type sublayer 51 is greater than or equal to the Mg doping concentration of the second p-type sublayer 53.

[0038] The first p-type sublayer 51 is located in the N-type layer heavily doped with Si. + Below the GaN tunnel junction (near the active layer 40), the Mg doping concentration is greater than or equal to that of the second p-type sublayer 53, meaning that the first p-type sublayer 51 near the tunnel junction has a higher hole concentration. Increasing the Mg doping of the p-type layer 50 can lower the valence band barrier, enhance hole transport, and increase the hole concentration of the first p-type sublayer 51. This disclosure makes the first p-type sublayer 51 and N... + -GaN forms high-quality N + -P + Even if the surface of the second p-type sublayer 53 is damaged or Mg-H passivated after rework, the tunnel junction can still obtain sufficient holes from the highly Mg-doped first p-type sublayer 51, and bypass the failure zone through tunneling and recombination, thus suppressing the increase of Vf.

[0039] Furthermore, the second p-type sublayer 53 is located above the tunnel junction and close to the metal electrode, and its low Mg concentration can reduce its absorption of the light emitted from the active layer 40.

[0040] For example, the Mg doping concentration of the first p-type sublayer 51 is 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 .

[0041] The first p-type sublayer 51 is located in the N-type layer heavily doped with Si. + Below the GaN tunnel junction (near the active layer 40 side), the Mg concentration is in a relatively high range, which can effectively protect the P of the tunnel junction. + The hole concentration on the side. In the above implementation, the Mg doping concentration of the first p-type sublayer 51 can form high-quality N. + -P + Even if the second sublayer fails after rework, N + The GaN layer can still obtain sufficient holes from the first p-type sublayer 51, which recombine with electrons through quantum tunneling, thus suppressing the rise of the forward voltage Vf.

[0042] For example, the Mg doping concentration of the second p-type sublayer 53 is 5 × 10⁻⁶. 18 cm -3 Up to 1×10 19cm -3 .

[0043] The second p-type sublayer 53 is located above the tunnel junction and directly bears the etch / cleaning and metal electrode contact. Its Mg concentration is lower than that of the first p-type sublayer 51. Furthermore, the Mg doping concentration of the second p-type sublayer 53 is controlled at 5 × 10⁻⁶. 18 cm -3 Up to 1×10 19 cm -3 The lower Mg concentration, on the one hand, reduces its absorption of free carriers in the light emitted from the active layer 40, thus improving the light extraction efficiency; on the other hand, the lower Mg concentration limits the resistance surge caused by surface oxidation, lattice damage, or Mg-H passivation during rework to the surface layer, while the lower highly doped first p-type sublayer 51 and N + - The GaN layer provides a low-resistivity tunneling path that is unaffected by surface conditions. The second p-type sublayer 53 does not need to pursue extremely high doping. It can be activated by subsequent annealing and conduction in conjunction with the buried layer. This relaxes the rework process window, reduces the difficulty of cleaning / etching control, and improves rework yield and long-term reliability.

[0044] Optionally, both the first p-type sublayer 51 and the second p-type sublayer 53 include a p-type GaN layer.

[0045] Both the first p-type sublayer 51 and the second p-type sublayer 53 are p-type GaN layers, combined with heavily Si-doped N. + - The GaN tunnel junctions are all nitride systems with small lattice mismatch, which is conducive to the formation of high-quality N. + -P + Tunnel knot.

[0046] For example, the thickness of the first p-type sublayer 51 is 50 nm to 200 nm. For instance, the thickness of the first p-type sublayer 51 is 100 nm.

[0047] The first p-type sublayer 51 is located in N. + Below the GaN tunnel junction (near the active layer 40), with a thickness of 50nm to 200nm, combined with the relatively high Mg concentration mentioned earlier, high-quality N can be formed. + -P + Tunnel P + To ensure N after rework + - The GaN layer can obtain sufficient holes from the first p-type sublayer 51 and then recombine via quantum tunneling to suppress Vf increase.

[0048] For example, the thickness of the second p-type sublayer 53 is 10 nm to 100 nm. For instance, the thickness of the second p-type sublayer 53 is 50 nm.

[0049] The second p-type sublayer 53 is located above the tunnel junction. The thickness of the second p-type sublayer 53 is controlled to be between 10 nm and 100 nm, which can avoid the absorption of light by traditional thick p-type GaN layers.

[0050] Optionally, such as Figure 1 As shown, the p-type layer 50 also includes a p-type AlGaN layer 54, with a first p-type sub-layer 51, a heavily doped tunnel junction layer 52, and a second p-type sub-layer 53 sequentially stacked on the p-type AlGaN layer 54.

[0051] In this embodiment of the disclosure, the p-type AlGaN layer 54 is located below the first p-type sublayer 51 and serves as an electron blocking layer to improve carrier transport.

[0052] For example, the thickness of the p-type AlGaN layer 54 can be from 10 nm to 100 nm.

[0053] Optionally, the n-type layer 30 may be an n-type GaN layer. The thickness of the n-type layer 30 is from 0.5 μm to 3 μm.

[0054] In this process, the dopant for the n-type layer 30 is silane, and the concentration of the silane dopant can be 5 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 .

[0055] Optionally, the active layer 40 includes multiple quantum well layers and multiple quantum barrier layers stacked alternately.

[0056] For example, the active layer 40 includes 8 to 15 layers of quantum wells and 8 to 15 layers of quantum barriers stacked alternately.

[0057] The number of alternating active layers 40 is controlled within the above range, which can enhance the quantum confinement effect through multiple quantum wells, efficiently confine carriers in the well, reduce leakage to the barrier layer or electrode, and increase the probability of radiative recombination. It can also avoid insufficient confinement caused by too few layers or excessive layers, resulting in lattice stress accumulation (such as the superposition of Mg doping compressive stress) and an increase in epitaxial defects.

[0058] For example, the quantum well layer can be an InGaN layer, and the quantum barrier layer can be a GaN layer.

[0059] Optionally, such as Figure 1 As shown, the light-emitting diode also includes a nucleation layer 21 and a buffer layer 22 stacked sequentially, with an n-type layer 30 located on the buffer layer 22.

[0060] Optionally, the nucleation layer 21 can be a GaN layer.

[0061] The nucleation layer 21 can alleviate lattice mismatch, reduce initial stress concentration, and optimize the quality of subsequent crystals through its small-sized island structure.

[0062] The thickness of the nucleation layer 21 can be from 0.3 μm to 0.5 μm.

[0063] Optionally, the buffer layer 22 includes a GaN layer. Using a GaN layer as a transition layer can effectively prevent impurities from the substrate 10 from diffusing into subsequent layers.

[0064] Optionally, such as Figure 1 As shown, the light-emitting diode may also include a substrate 10, which is a substrate that carries an epitaxial layer, and a nucleation layer 21 is stacked on the substrate 10.

[0065] For example, the substrate 10 is a sapphire substrate 10, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0066] As an example, in this embodiment of the disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a commonly used substrate 10, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a flat sapphire substrate 10.

[0067] Figure 2 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 2 As shown, the preparation method includes: Step S11: Form an n-type layer on the substrate.

[0068] Step S12: Form an active layer on the n-type layer.

[0069] Step S13: Form a p-type layer on the active layer.

[0070] The p-type layer includes a first p-type sub-layer, a heavily doped tunnel junction layer, and a second p-type sub-layer stacked sequentially. The heavily doped tunnel junction layer includes an n-type doped semiconductor layer.

[0071] The light-emitting diode (LED) fabricated by the method provided in this disclosure involves sequentially stacking a first p-type sublayer, a heavily doped tunnel junction layer (n-type doped semiconductor layer), and a second p-type sublayer within a p-type layer; that is, pre-burying an n-type doped semiconductor layer inside a p-type GaN layer. Firstly, the heavily doped tunnel junction layer, with its extremely high n-type impurity concentration, compresses the depletion region width to the nanometer scale, allowing charge carriers to tunnel through the extremely thin barrier via quantum tunneling. + -P + The interface forms a low-resistance tunneling path, and this mechanism itself is the core way to achieve low-resistance ohmic contact.

[0072] Secondly, in chip manufacturing rework scenarios, due to deviations in photolithography, etching, etc., the defective area dielectric / metal needs to be removed and the electrode redeposited. Conventional processes will cause a sharp increase in contact resistance and bulk resistance, and an increase in forward voltage Vf due to lattice damage on the surface of the second p-type sublayer, Ga2O3 oxidation insulation, or Mg-H passivation. However, the buried layer heavily doped tunnel junction of this disclosure is located below the second p-type sublayer. The rework cleaning and etching only affect the surface second p-type sublayer. The integrity of the heavily doped tunnel junction is not affected by the surface process state, so the vertical low-resistance channel is still retained.

[0073] Furthermore, while the subsequent annealing step repairs the surface damage of the second p-type sublayer and activates some Mg acceptors, the pre-embedded heavily doped tunnel junction provides a tunneling path for electrons injected by the metal electrode, unaffected by the reworked surface condition. Electrons can tunnel through the even highly resistive second p-type sublayer, directly reaching the heavily doped tunnel junction, and then recombine with holes provided by the first p-type sublayer on the active region side, thereby bypassing the damage and oxidation region caused by rework and suppressing the abnormal rise in forward voltage Vf.

[0074] The following steps may also be included before step S11: The first step is to provide a substrate as the basic support for epitaxial growth.

[0075] The substrate can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0076] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.

[0077] In this embodiment of the present disclosure, the sapphire substrate can be subjected to high-temperature cleaning treatment in a hydrogen atmosphere at 1000°C to 1200°C for 5 to 20 minutes, and then subjected to nitriding treatment.

[0078] In this embodiment of the disclosure, the sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment of the disclosure, the sapphire substrate is baked for 15 minutes.

[0079] Specifically, the baking temperature can be from 1000°C to 1200°C, and the pressure in the MOCVD reaction chamber during baking can be from 100 mbar to 200 mbar.

[0080] The second step is to grow a nucleus layer on the substrate.

[0081] GaN layers with a thickness of 0.3 μm to 2 µm were grown under the MOCVD reaction chamber temperature controlled at 1030 °C to 1100 °C and the reaction chamber pressure controlled at 150 torr to 500 torr in a mixed atmosphere of nitrogen, hydrogen and ammonia.

[0082] The second step is to grow a buffer layer on the nucleation layer.

[0083] Specifically, a GaN buffer layer is grown in the MOCVD reaction chamber. The buffer layer is used to mitigate the lattice mismatch between the substrate and the subsequent epitaxial layers.

[0084] The growth temperature is 400℃ to 800℃, the growth pressure is 1 mtorr to 20 mtorr, and the GaN layer deposition thickness is 10 nm to 50 nm.

[0085] Step S11 may include: growing an n-type layer on the buffer layer.

[0086] Optionally, the n-type layer can be an n-type GaN layer. The thickness of the n-type layer is 0.5 μm to 3 μm. The dopant of the n-type layer is silane. The n-type GaN layer is the semiconductor layer closest to the substrate in the LED structure, providing an electron injection channel for subsequent active layer growth.

[0087] Specifically, in an MOCVD system with a temperature adjusted to 1000℃ to 1150℃ and a growth pressure of 100 torr to 300 torr, an n-type doped GaN layer with a thickness of 0.5 μm to 3 µm is grown, and the Si doping concentration of the n-type GaN layer is 1 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 .

[0088] Step S12 may include: growing multiple alternating layers of quantum wells and multiple layers of quantum barriers to form an active layer.

[0089] For example, the active layer includes 8 to 15 layers of quantum well layers and 8 to 15 layers of quantum barrier layers stacked alternately.

[0090] The growth conditions for the quantum well layer include: a pure nitrogen atmosphere, a growth temperature controlled at 700℃ to 850℃, and a growth pressure controlled at 200 Tott to 500 Torr to ensure uniform incorporation of the In component.

[0091] For example, the quantum well layer includes an InGaN layer, and the thickness of each quantum well layer is 3 nm to 5 nm.

[0092] For example, the quantum barrier layer includes a GaN layer. The thickness of each quantum barrier layer is 8 nm to 15 nm.

[0093] Step S13 may include the following steps: The first step is to grow a p-type AlGaN layer on the active layer, which serves as an electron blocking layer to reduce light absorption and support the upper contact layer.

[0094] The second step involves growing a first p-type sublayer (p-type GaN layer) on the p-type AlGaN layer using magnesia-diocene (Cp₂Mg) doping. The Mg concentration of the first p-type sublayer is 1 × 10¹. 9 cm - ³ to 1×10² 0 cm - ³ Thickness from 50nm to 200nm.

[0095] The third step involves growing N-type sublayers on the first p-type sublayer using silane heavy doping. + -GaN layer, N + -Si doping concentration of GaN layer is 1×10¹ 9 cm - ³ to 1×10²¹cm - ³, N + The thickness of the GaN layer ranges from 5 nm to 50 nm. + -The GaN layer and the first p-type sublayer constitute N + -P + Tunnel knot.

[0096] Fourth step, in N + A second p-type sublayer (p-type GaN layer) continues to grow on the GaN layer, with a Mg concentration of 5 × 10¹. 8 cm - ³ to 1×10¹ 9 cm - ³, with a thickness of 10nm to 100nm, serves as the surface contact layer.

[0097] This disclosure provides a method for reworking a light-emitting diode (LED). The method is used to rework an LED as described above. The LED further includes a functional film layer located on a p-type layer.

[0098] For example, the functional film layer may be an insulating dielectric layer or a metal layer for current transmission.

[0099] The rework method for this LED includes the following steps: The first step is to remove the functional film layer to expose the second p-type sublayer of the p-type layer.

[0100] Photoresist is used to protect non-rework areas, and the insulating dielectric layer or metal layer located above the p-type layer and covering the surface of the second p-type sublayer is selectively stripped by wet etching or dry etching.

[0101] Etching stops at the surface of the second p-type sublayer to avoid damaging the underlying buried N. + -GaN tunnel junction and first p-type sublayer, thereby exposing the surface layer that can be reprocessed.

[0102] The second step is to clean the surface of the second p-type sublayer.

[0103] The exposed second p-type sublayer was cleaned with a cleaning solution to remove rework etching residues, surface-adsorbed contaminants, and the naturally formed gallium oxide (Ga2O3) insulating layer.

[0104] After cleaning and drying, the surface lattice cleanliness of p-type GaN is restored, providing a contamination-free interface for subsequent annealing activation and electrode re-fabrication, while reducing the risk of contact resistance surges caused by surface states.

[0105] The third step involves rapidly thermally annealing the LEDs at a temperature range of 400°C to 800°C for 10 seconds to 10 minutes.

[0106] The cleaned epitaxial wafer is placed in a rapid thermal annealing apparatus and heated to 400°C to 800°C at a rate of 20°C / second to 40°C / second under nitrogen, oxygen, or vacuum atmosphere, held at that temperature for 10 seconds to 10 minutes, and then cooled.

[0107] After annealing, a new transparent conductive layer and / or P-type electrode are re-prepared on the surface of the treated second p-type sublayer to form a new ohmic contact.

[0108] In the above implementation, annealing at 400℃ to 800℃ can break the Mg-H complex bonds introduced by rework cleaning / etching, allowing H to be discharged and activating the Mg acceptor in the second p-type sublayer, thereby increasing the hole concentration.

[0109] The following is a comparison of two embodiments provided in this disclosure with related technologies.

[0110] In the first embodiment, the fabrication process of the light-emitting diode includes: growing sequentially on a patterned sapphire substrate in an MOCVD reaction chamber: a GaN nucleation layer, an undoped GaN buffer layer, and a Si-doped N-type GaN layer (thickness 1.5 μm, Si doping concentration 2 × 10¹). 9 cm - ³), InGaN / GaN multi-quantum-well active layer (11 cycles), p-type AlGaN electron blocking layer; then the first p-type sublayer, heavily doped tunnel junction layer and second p-type sublayer are grown. After mesa etching, a SiO2 passivation layer is deposited on the p-type layer (i.e. the surface of the second p-type sublayer) as a functional film.

[0111] The first p-type sublayer is a Mg-doped p-type GaN layer with a thickness of 100 nm and a Mg doping concentration of 1 × 10¹.9 cm - ³, growth temperature 940℃.

[0112] The heavily doped tunnel junction is Si-doped N + -GaN layer, 20nm thick, Si doping concentration 5×10¹ 9 cm - ³, growth temperature 900℃.

[0113] The second p-type sublayer is Mg-doped p-type GaN with a thickness of 30 nm and a Mg doping concentration of 5 × 10¹. 8 cm - ³, growth temperature 900℃.

[0114] In this process, the Mg concentration in the first p-type sublayer is greater than that in the second p-type sublayer, and a heavily doped tunnel junction layer is sandwiched between the two layers, forming an embedded N-type sublayer. + -P + Tunnel knot.

[0115] In the first embodiment, defective LEDs are reworked due to photoresist residue. The rework process is as follows: First, the functional film layer is removed by plasma ashing to remove the resist, and SiO2 is etched by BOE wet etching to expose the surface of the second p-type sublayer.

[0116] Then, the exposed surfaces are cleaned using standard methods with organic solvents and acid / alkali solutions.

[0117] Next, a sacrificial layer is deposited by using an electron beam evaporation device to deposit a 5 nm thick Ni metal layer on the cleaned surface.

[0118] Then, the epitaxial wafer is placed in a rapid annealing furnace and annealed at 650°C for 60 seconds under a N2 atmosphere. The epitaxial wafer is then immersed in aqua regia to completely remove the Ni layer and the surface oxide layer formed during annealing.

[0119] Next, the epitaxial wafer was immediately transferred to a sputtering stage to deposit an ITO transparent conductive layer, which was then alloyed and annealed to complete the preparation of the P electrode metal.

[0120] Table 1 below is a comparison table of test data for light-emitting diodes in the embodiments provided in this disclosure and related technologies.

[0121] Table 1

[0122] As shown in Table 1, the forward voltage of the reworked chip at 120mA is only 0.03V higher than that of the normal chip; the increase is about 0.1V when there is no buried tunnel junction in the related technology. This proves that the built-in heavily doped Si tunnel junction provides a low-resistance tunneling path around the surface damage region after rework, which can effectively suppress the rise in forward voltage.

[0123] The first embodiment is basically the same as Example 1, except for the rework annealing step: In the second embodiment, after cleaning, the Ni sacrificial layer is not deposited. The epitaxial wafer is directly placed in a rapid annealing furnace and annealed at 550°C for 300 seconds in a N2 / O2 mixed atmosphere. Then, ITO and P electrodes are directly deposited.

[0124] As shown in Table 1, the voltage increase after rework in the second embodiment is approximately 0.06V, which is slightly higher than that in the first embodiment, but still far superior to the rework structure of related technologies (above 0.1V). This indicates that even without the sacrificial layer oxidation step, the bottom layer N + The GaN / first p-type sublayer tunnel junction remains intact, and annealing can utilize the pre-set low-resistivity channel to widen the process window and reduce rework degradation.

[0125] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes an n-type layer (30), an active layer (40), and a p-type layer (50) stacked sequentially. The p-type layer (50) includes a first p-type sub-layer (51), a heavily doped tunnel junction layer (52), and a second p-type sub-layer (53) stacked sequentially. The heavily doped tunnel junction layer (52) includes an n-type doped semiconductor layer.

2. The light-emitting diode according to claim 1, characterized in that, The heavily doped tunnel junction (52) includes N + -GaN layer.

3. The light-emitting diode according to claim 2, characterized in that, The N + -The GaN layer is Si-doped, and the N + The Si doping concentration of the GaN layer is 1×10⁻⁶. 19 cm -3 Up to 1×10 21 cm -3 .

4. The light-emitting diode according to claim 3, characterized in that, The N + - The thickness of the GaN layer ranges from 5 nm to 50 nm.

5. The light-emitting diode according to any one of claims 1 to 4, characterized in that, Both the first p-type sublayer (51) and the second p-type sublayer (53) are Mg-doped, and the Mg doping concentration of the first p-type sublayer (51) is greater than or equal to the Mg doping concentration of the second p-type sublayer (53).

6. The light-emitting diode according to claim 5, characterized in that, The Mg doping concentration of the first p-type sublayer (51) is 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 ; The Mg doping concentration of the second p-type sublayer (53) is 5 × 10⁻⁶. 18 cm -3 Up to 1×10 19 cm -3 .

7. The light-emitting diode according to claim 5, characterized in that, The thickness of the first p-type sublayer (51) is 50 nm to 200 nm, and the thickness of the second p-type sublayer (53) is 10 nm to 100 nm.

8. The light-emitting diode according to any one of claims 1 to 4, characterized in that, Both the first p-type sublayer (51) and the second p-type sublayer (53) include p-type GaN layers.

9. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: An n-type layer (30) is formed on the substrate (10); An active layer (40) is formed on the n-type layer (30); A p-type layer (50) is formed on the active layer (40). The p-type layer (50) includes a first p-type sub-layer (51), a heavily doped tunnel junction layer (52), and a second p-type sub-layer (53) stacked sequentially. The heavily doped tunnel junction layer (52) includes an n-type doped semiconductor layer.

10. A method for reworking a light-emitting diode, characterized in that, The rework method is used to rework a light-emitting diode as described in any one of claims 1 to 8, wherein the light-emitting diode further includes a functional film layer located on the p-type layer (50), and the rework method includes: Remove the functional film layer to expose the second p-type sublayer (53) of the p-type layer (50). Clean the surface of the second p-type sublayer (53); The light-emitting diode is subjected to rapid thermal annealing in a temperature range of 400°C to 800°C for 10 seconds to 10 minutes.

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