Chip testing method and system based on parameter correlation

Abstract

The embodiment of the application belongs to the chip testing technical field, and relates to a chip testing method and system based on parameter correlation. The method comprises the following steps: performing all-round sampling on core parameters of a chip to be tested to obtain core test results; dividing non-core parameters into second parameters and first parameters which can be tested in advance according to the core test results and a parameter correlation graph; performing preset-round sampling on the first parameters to obtain first actual test results, inputting the first actual test results into a time sequence steady state evaluation model to obtain steady state evaluation results, and generating first test results of the first parameters according to the first actual test results and the steady state evaluation results if the test early termination condition is met; if the condition is not met, iteratively testing the first parameters until the condition is met or all-round sampling is completed to obtain second test results; performing all-round sampling on each second parameter to obtain third test results; and generating a chip test result according to the test results. The application improves the efficiency of chip testing.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing method, apparatus, computer equipment, and storage medium based on parameter correlation. Background Technology

[0002] Chip mass production testing is a crucial step in semiconductor manufacturing. With the increasing complexity of integrated circuits, the number of test items and the testing time required for chip mass production testing have increased significantly. How to reduce testing time while ensuring test coverage and accuracy is a common technical challenge in the chip testing field.

[0003] Currently, chip mass production testing typically employs a fixed test sequence scheme, meaning each chip undergoes the same full set of tests, lacking the ability to differentiate between different chips. Some adaptive testing schemes make dynamic decisions based on real-time data during the testing process, but the decision-making basis is relatively singular, usually based on a simple comparison between the measured values ​​of the current test parameters and preset values. Furthermore, the decision-making method is rather passive, typically based on post-test adjustments after the results have been completed. Therefore, the efficiency of chip testing remains low. Summary of the Invention

[0004] The purpose of this application is to provide a chip testing method, apparatus, computer equipment, and storage medium based on parameter correlation to solve the problem of low chip testing efficiency.

[0005] To address the aforementioned technical problems, this application provides a chip testing method based on parameter correlation, employing the following technical solution: Obtain the parameter correlation map of the chip under test, and determine the core parameters and non-core parameters of the chip under test through the parameter correlation map; The core parameters are sampled in all rounds to obtain the core test results; Based on the core test results and the correlation in the parameter correlation graph, the non-core parameters are divided into a first parameter and a second parameter. The first parameter has the authority to terminate the test early. For each first parameter, the first parameter is sampled for a preset number of rounds to obtain a first measured result, and the first measured result is input into the time series steady-state evaluation model to obtain a steady-state evaluation result; When the steady-state evaluation result meets the preset test early termination condition, a first test result of the first parameter is generated based on the first measured result and the steady-state evaluation result; When the steady-state evaluation result does not meet the test early termination condition, the first parameter is iteratively tested until the obtained steady-state evaluation result meets the test early termination condition or all rounds of sampling are completed, and a second test result is obtained. Sample each second parameter for all rounds to obtain a third test result for each second parameter; Based on all the test results obtained, the chip test results of the chip under test are generated.

[0006] Furthermore, prior to the step of obtaining the parameter correlation map of the chip under test, the method further includes: Obtain historical test data for the chip; Calculate the correlation coefficients between the parameters of the chip based on the historical test data, and determine the relevant parameter pairs based on the obtained correlation coefficients; The correlation direction of each relevant parameter pair is determined by regression model; Based on the relevant parameter pairs and their corresponding association directions, a parameter association map of the chip is constructed.

[0007] Furthermore, prior to the step of obtaining the parameter correlation map of the chip under test, the method further includes: Obtain historical test data for the chip; For each parameter of the chip, a first historical test result obtained from the historical test data after a preset number of sampling rounds, and a second historical test result obtained from sampling after the preset number of sampling rounds are obtained. The steady-state interval of the parameter is calculated based on the first historical measurement result, and training labels are generated based on the steady-state interval and the second historical measurement result. The training labels include steady-state and non-steady-state conditions. Based on the first and second historical measured results of each parameter and the training labels, the initial time-series steady-state evaluation model is trained, and the time-series steady-state evaluation model is obtained.

[0008] Furthermore, the step of dividing the non-core parameters into first parameters and second parameters based on the core test results and the correlation relationships in the parameter correlation graph includes: Based on the correlation relationships in the parameter correlation graph, the correlation parameters of the core parameters are determined, and the correlation parameters are non-core parameters; Based on the core test results, calculate the predicted values ​​of each related parameter; For each associated parameter, when the predicted value of the associated parameter meets the preset specification conditions, the associated parameter is classified as a first parameter, and the first parameter has the authorization to terminate the test early. When the predicted value of the associated parameter does not meet the specification conditions, the associated parameter is classified as a second parameter, and the second parameter does not have the authorization to terminate the test early.

[0009] Furthermore, the step of generating a first test result for the first parameter based on the first measured result and the steady-state evaluation result when the steady-state evaluation result meets the preset test early termination conditions includes: Obtain the steady-state evaluation value and its confidence level from the steady-state evaluation results; When the steady-state evaluation value is steady-state and the confidence level is greater than or equal to the preset confidence level threshold, it is determined that the preset test early termination condition is met. Generate batch cutoff signals for the remaining rounds; The remaining rounds of sampling are skipped by batch truncation of the signal, and the first test result of the first parameter is generated based on the first measured result and the steady-state evaluation result.

[0010] Furthermore, the step of iteratively testing the first parameter until the obtained steady-state evaluation result meets the early termination condition or all rounds of sampling are completed, when the steady-state evaluation result does not meet the early termination condition, to obtain the second test result includes: Obtain the steady-state evaluation value and its confidence level from the steady-state evaluation results; When the steady-state evaluation value is non-steady-state or the confidence level is less than the preset confidence threshold, it is determined that the steady-state evaluation result does not meet the test early termination condition; The first parameter is iteratively tested until the obtained steady-state evaluation result meets the early termination condition of the test. A second test result is then obtained based on the measured result and the steady-state evaluation result when the early termination condition is met; or... The first parameter is sampled for all rounds to obtain the second test result.

[0011] Furthermore, the above methods also include: For the first parameter corresponding to the first test result, the first parameter is randomly selected for sampling in the remaining rounds to obtain the actual test results. When the sampling test results of the preset number of first parameters do not meet the early termination condition of the test, the time-series steady-state evaluation model is incrementally trained based on the first test results of the first parameter and the sampling test results.

[0012] To address the aforementioned technical problems, this application also provides a chip testing device based on parameter correlation, employing the following technical solution: The graph acquisition module is used to acquire the parameter correlation graph of the chip under test, and to determine the core parameters and non-core parameters of the chip under test through the parameter correlation graph. The core sampling module is used to sample the core parameters in all rounds to obtain the core test results. The parameter partitioning module is used to partition the non-core parameters into a first parameter and a second parameter based on the core test results and the correlation in the parameter correlation graph. The first parameter has the authority to terminate the test early. The first sampling module is used to sample each first parameter for a preset number of rounds to obtain a first measured result, and input the first measured result into the time series steady-state evaluation model to obtain a steady-state evaluation result; The first generation module is used to generate a first test result of the first parameter based on the first measured result and the steady-state evaluation result when the steady-state evaluation result meets the preset test early termination conditions. The iterative testing module is used to perform iterative testing on the first parameter until the obtained steady-state evaluation result meets the early termination condition or all rounds of sampling are completed when the steady-state evaluation result does not meet the early termination condition, and obtain the second test result. The second sampling module is used to sample each second parameter for all rounds to obtain the third test result for each second parameter; The result generation module is used to generate chip test results for the chip under test based on all the obtained test results.

[0013] To address the aforementioned technical problems, this application also provides a computer device, which includes a memory and a processor. The memory stores computer-readable instructions, and the processor executes the computer-readable instructions to implement the steps of the parameter-association-based chip testing method described above.

[0014] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing computer-readable instructions, which, when executed by a processor, implement the steps of the parameter-association-based chip testing method described above.

[0015] Compared with the prior art, the embodiments of this application have the following main advantages: Core parameters are determined through parameter correlation graphs, and core test results are obtained by sampling them through all rounds. Core parameters are strongly correlated with multiple parameters, and their measurement results can predict other parameters. Based on the correlation between the core test results and the parameter correlation graph, non-core parameters are divided into first parameters and second parameters. The first parameter uses a time-series steady-state evaluation model to determine whether sampling should be terminated early, while the second parameter undergoes sampling through all rounds, achieving differentiated processing. Only core parameters are fully tested; non-core first parameters undergo sampling through preset rounds, and if the conditions are met, early termination is achieved, reducing the total number of test rounds and test time for a single chip. If the steady-state evaluation does not meet the early termination conditions, iterative testing is used to continuously evaluate the parameter state until a reliable result is obtained, ensuring test accuracy. Sampling through all rounds for the second parameter ensures test accuracy. This application makes real-time determinations during the test process, allowing for early prediction of the state of subsequent rounds and proactive termination, improving test efficiency while ensuring test coverage. Attached Figure Description

[0016] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of an embodiment of the chip testing method based on parameter correlation according to this application; Figure 2 This is a schematic diagram of the structure of an embodiment of the chip testing apparatus based on parameter association according to this application; Figure 3 This is a schematic diagram of the structure of one embodiment of the computer device according to this application. Detailed Implementation

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0021] refer to Figure 1 The diagram illustrates a flowchart of an embodiment of a parameter-association-based chip testing method according to this application. The parameter-association-based chip testing method includes the following steps: Step S101: Obtain the parameter correlation map of the chip under test, and determine the core parameters and non-core parameters of the chip under test through the parameter correlation map.

[0022] The parameter correlation map is pre-constructed and records the correlations between various test parameters of the chip. Some parameters of the chip are correlated, meaning that two parameters are related in terms of physical or electrical characteristics, and the measurement result of one parameter can be used to infer the measurement result of another parameter within a preset accuracy range.

[0023] In a parameter association graph, a parameter node can be connected to several directed edges, pointing to subordinate parameters that can be predicted by that parameter. A core parameter is the parameter with the most associated edges in the parameter association graph (there must be at least one core parameter), and it has predictable relationships with the largest number of other parameters. Non-core parameters are all parameters other than the core parameters.

[0024] Specifically, before mass production testing of the chip under test, a parameter correlation graph corresponding to that chip model is first obtained. Core and non-core parameters are determined by querying the number of associated edges at each node in the graph. Each node in the graph represents a test parameter, and directed edges between nodes indicate a correlation between two parameters; the direction of the edge indicates the prediction direction. The parameter with the most associated edges is identified as the core parameter, and all other parameters are identified as non-core parameters.

[0025] In one embodiment, parameters with a number of associated edges greater than a preset threshold can also be defined as core parameters.

[0026] The core parameter is strongly correlated with several other parameters, and its measurement results can provide a basis for predicting other parameters.

[0027] Step S102: Sample the core parameters for all rounds to obtain the core test results.

[0028] Here, "all rounds of sampling" can refer to performing all N rounds of repeated testing (N being a preset positive integer) on the current test parameters. The core test result can be the measured data obtained after performing all rounds of sampling on the core parameters.

[0029] Specifically, the Automatic Test Equipment (ATE) performs repeated tests on the core parameters in all rounds. In each round of testing, the ATE applies preset stimulus conditions to the chip, reads the response signal at preset measurement points, and records the measured value. After completing all N rounds of testing, the measured values ​​obtained in each round are used as the core test result.

[0030] Step S103: Based on the core test results and the correlation in the parameter correlation graph, the non-core parameters are divided into first parameters and second parameters. The first parameters have the authorization to terminate the test early.

[0031] Specifically, the association relationships in the parameter association graph are queried based on the core test results. The graph records non-core parameters that are associated with the core parameters. The predicted value of the non-core parameter is calculated based on the mapping function recorded in the core test results and the association relationships.

[0032] If the predicted value meets the preset specifications, the non-core parameter is classified as a first parameter and granted early termination authorization, allowing for early termination in subsequent tests when conditions are met. If the predicted value does not meet the preset specifications, the non-core parameter is classified as a second parameter, does not have early termination authorization, and requires completion of all sampling rounds in subsequent tests. Non-core parameters in the graph that are not recorded as having a correlation with core parameters are classified as second parameters.

[0033] Step S104: For each first parameter, the first parameter is sampled for a preset number of rounds to obtain the first measured result, and the first measured result is input into the time series steady-state evaluation model to obtain the steady-state evaluation result.

[0034] Specifically, for each first parameter, ATE first performs a preset number of repeated tests (K rounds), and the measured data obtained from the K rounds is the first measured result. The first measured result is input into the time series steady-state evaluation model, which can be a pre-trained neural network model that can output a steady-state evaluation result based on the time series change trend of the measured data from the previous K rounds.

[0035] The steady-state evaluation results can include steady-state evaluation values, which indicate whether the parameter is in a steady state, that is, whether the measured values ​​in subsequent rounds fall within the preset steady-state range and the measured values ​​no longer change significantly.

[0036] Step S105: When the steady-state evaluation result meets the preset test early termination condition, generate the first test result of the first parameter based on the first measured result and the steady-state evaluation result.

[0037] Specifically, it is determined whether the steady-state evaluation result meets the preset test early termination condition. In one embodiment, if the steady-state evaluation value is steady-state, the test early termination condition is met. At this time, the ATE stops sampling in subsequent rounds, generates the first test result of the first parameter based on the measured data of the Kth round and the steady-state evaluation result, and uses the measured value at the steady-state determination time (i.e., the measured value of the Kth round) as the final value of the current test parameter.

[0038] Step S106: When the steady-state evaluation result does not meet the test early termination condition, iterative testing is performed on the first parameter until the obtained steady-state evaluation result meets the test early termination condition or all rounds of sampling are completed, and the second test result is obtained.

[0039] Specifically, in one embodiment, if the steady-state evaluation value is non-steady-state, the steady-state evaluation result does not meet the test early termination condition. The ATE continues to execute the next round of sampling for the current first parameter, inputting the newly obtained K+1 rounds of measured data into the time-series steady-state evaluation model, and re-performs the steady-state evaluation. If the early termination condition is met after the re-evaluation, a second test result is generated based on the measured data of that round and the steady-state evaluation result. If the condition is still not met after the re-evaluation, the next round of sampling is executed and evaluated again, and so on iteratively. If the above process is repeated until all N rounds of sampling are completed and the early termination condition is still not met, a second test result is generated based on the measured data of all rounds.

[0040] Step S107: Sample each second parameter for all rounds to obtain the third test result for each second parameter.

[0041] Specifically, since the second parameter does not have early termination authorization, the ATE performs repeated testing for all N rounds for each second parameter and records the measurement data for each round. After sampling for all rounds, a third test result for the second parameter is generated based on the measured data from all rounds.

[0042] Step S108: Based on all the obtained test results, generate the chip test results of the chip under test.

[0043] Among them, the chip test result refers to the final test report or judgment conclusion output after the chip under test has completed all tests.

[0044] Specifically, after completing all rounds of sampling of the core parameters, testing of all first parameters (including early termination branches and iterative branches), and all rounds of sampling of all second parameters, the core test results, first test results, second test results, and third test results obtained from the above process are summarized. Each test result is compared and organized with the preset specification standards to generate the chip test result of the chip under test, which can indicate whether the chip under test meets the quality requirements.

[0045] In this embodiment, core parameters are determined through parameter correlation graphs, and core test results are obtained by sampling them through all rounds. Core parameters are strongly correlated with multiple parameters, and their measurement results can predict other parameters. Based on the correlation between the core test results and the parameter correlation graphs, non-core parameters are divided into first parameters and second parameters. The first parameter uses a time-series steady-state evaluation model to determine whether sampling should be terminated early, while the second parameter undergoes sampling through all rounds, achieving differentiated processing. Only core parameters are fully tested; non-core first parameters are sampled through a preset number of rounds, and if the conditions are met, early termination is achieved, reducing the total number of test rounds and test time for a single chip. If the steady-state evaluation does not meet the early termination conditions, iterative testing is used to continuously evaluate the parameter state until a reliable result is obtained, ensuring test accuracy. Sampling through all rounds for the second parameter ensures test accuracy. This application makes real-time determinations during the testing process, allowing for early prediction of the state of subsequent rounds and proactive termination, improving test efficiency while ensuring test coverage.

[0046] Furthermore, before the step of obtaining the parameter correlation map of the chip under test, the method may further include: obtaining historical test data of the chip; calculating the correlation coefficient between the parameters of the chip based on the historical test data, and determining the relevant parameter pairs based on the obtained correlation coefficients; determining the correlation direction of each relevant parameter pair through a regression model; and constructing the parameter correlation map of the chip based on each relevant parameter pair and its corresponding correlation direction.

[0047] Specifically, the parameter correlation map is pre-constructed. First, historical test data for this chip model is obtained, which contains a large number of complete test records for each chip on various parameters. For each chip in the historical test data, the average value of multiple rounds of sampling for each parameter is taken as the representative value of that parameter.

[0048] Then, pairwise correlation analysis was performed on each parameter. For each pair of parameters, the Pearson correlation coefficient and the Spearman rank correlation coefficient were calculated. The Pearson correlation coefficient measures the degree of linear correlation between the two parameters, while the Spearman rank correlation coefficient captures a non-linear but monotonic correlation. If the absolute value of either the Pearson correlation coefficient or the Spearman rank correlation coefficient exceeds a preset threshold, the pair of parameters is determined to be a correlated parameter pair.

[0049] For each relevant parameter pair, a mapping function, such as a regression model, is used to fit and predict along two directions. The regression model fits the mapping relationship between two parameters, taking a representative value of one parameter as input and a predicted value of the other as output. The prediction error of parameter A predicting parameter B, and the prediction error of parameter B predicting parameter A, are calculated separately. The direction with the smaller prediction error is determined as the association direction for that parameter pair, representing the predictable direction between the two parameters. If the error of parameter A predicting parameter B is smaller, the association direction is from A to B, and the measurement result of parameter A can predict the measurement result of parameter B with higher accuracy. Simultaneously, the prediction accuracy in that direction is recorded, represented by the mean absolute error.

[0050] Using the chip's parameters as nodes, the relevant parameter pairs and their corresponding directions as directed edges, and the prediction accuracy as the edge attribute, a parameter association graph of the chip is constructed.

[0051] In this embodiment, correlation is determined by the correlation coefficient between parameters to achieve the mining of association relationships; the bidirectional prediction error of the relevant parameter pairs is calculated by the regression model to determine the association direction, thus providing a data foundation for subsequent prediction of other parameters based on core parameters; the construction of parameter association graphs is beneficial to improving subsequent testing efficiency.

[0052] Furthermore, prior to the step of obtaining the parameter correlation map of the chip under test, the method may further include: obtaining historical test data of the chip; for each parameter of the chip, obtaining a first historical test result obtained from the historical test data after a preset number of sampling rounds, and a second historical test result obtained after the preset number of sampling rounds; calculating the steady-state interval of the parameter based on the first historical test result, and generating training labels based on the steady-state interval and the second historical test result, wherein the training labels include steady-state and non-steady-state states; and training an initial time-series steady-state evaluation model based on the first historical test result, the second historical test result, and the training labels of each parameter to obtain the time-series steady-state evaluation model.

[0053] Specifically, historical test data for this chip model is obtained, which includes a large number of complete test records and final test conclusions for each parameter. For each test parameter of the chip, sampled data from a preset round K is extracted from the historical test data as the first historical test result, and sampled data from each round after round K is used as the second historical test result. The value of K can be adjusted according to compression ratio and accuracy.

[0054] Calculate the steady-state interval of this parameter. The calculation method can be as follows: calculate the average of the first historical measured results (the first K rounds of sampled values), and use this average as the center, determining the upper and lower boundaries according to a preset percentage threshold (such as ±3% or ±5%) to form the steady-state interval. For example, if the average of the first 3 rounds of sampled values ​​is 12.63, and the preset percentage threshold is ±3%, then the steady-state interval is 12.63 × (1 ± 3%), i.e., 12.25 to 13.01. The steady-state interval is used to determine whether subsequent rounds are in a steady state.

[0055] Then, the sampled values ​​of each round in the second historical test results are compared with the steady-state interval. If all sampled values ​​in the second historical test results fall within the steady-state interval, the test parameter remains stable in subsequent rounds, and the training label of the training sample is marked as steady-state. If there are sampled values ​​in the second historical test results that exceed the steady-state interval, the test parameter does not remain stable in subsequent rounds, and the training label of the training sample is marked as non-steady-state.

[0056] The initial time-series steady-state evaluation model is trained in a supervised manner using the first historical measured results of each parameter as input and the corresponding training labels as supervision signals. The initial time-series steady-state evaluation model can be a Long Short-Term Memory (LSTM) network, a variant of a recurrent neural network that effectively captures long-term dependencies in time series data, suitable for handling the temporal evolution patterns between multiple rounds of sampling values ​​in chip testing. This model can also be built based on gated recurrent units or Transformers.

[0057] After training, the time-series steady-state evaluation model can output steady-state evaluation results and their corresponding confidence levels in real time during the online testing phase, based on the sequence of measured values ​​of the first K rounds of the current test parameters.

[0058] In this embodiment, a steady-state interval is calculated based on historical test data and training labels are generated, thereby training a time-series steady-state evaluation model. The model can learn the mapping relationship between the sampling value sequence of the first K rounds and the steady-state state of subsequent rounds from a large number of historical samples, providing data support for early termination decisions during testing, which is beneficial to improving testing efficiency.

[0059] Furthermore, the step of classifying non-core parameters into first parameters and second parameters based on the correlation relationships in the core test results and parameter correlation graph can include: determining the related parameters of the core parameters based on the correlation relationships in the parameter correlation graph, where the related parameters are non-core parameters; calculating the predicted values ​​of each related parameter based on the core test results; for each related parameter, when the predicted value of the related parameter meets the preset specification conditions, the related parameter is classified as a first parameter, and the first parameter has early termination authorization for the test; when the predicted value of the related parameter does not meet the specification conditions, the related parameter is classified as a second parameter, and the second parameter does not have early termination authorization for the test.

[0060] Specifically, based on the parameter correlation map, the correlated parameters that are related to the core parameters are identified. For each correlated parameter, the predicted value of the correlated parameter is calculated based on the core test results and the mapping function (which can be a regression function) in the correlation relationship.

[0061] The system determines whether the predicted value meets preset specification conditions. These conditions include two sub-conditions: first, whether the predicted value falls within the preset specification limits for the associated parameter; and second, whether the distance between the predicted value and the nearest specification limit boundary is greater than a preset safety threshold. The safety threshold is set based on the prediction accuracy of the association. For example, if the mean absolute error (MAE) of predicting the associated parameter using the core parameter is recorded in the graph, the safety threshold could be 2 × MAE. During the determination, the distances between the predicted value and the lower and upper specification limits are calculated separately, and the smaller value is taken as the minimum boundary distance. If the predicted value falls within the specification limits and the minimum boundary distance is greater than the safety threshold, the specification conditions are met, the associated parameter is classified as the first parameter, and early termination of the test is granted.

[0062] If the predicted value does not fall within the specification limits, or the minimum boundary distance is less than or equal to the safety threshold, it does not meet the specification conditions. This associated parameter is classified as a second parameter, and the test is not granted early termination authorization.

[0063] In this embodiment, the correlation parameters are determined by the correlation graph and the predicted values ​​are calculated based on the core test results. Parameters whose predicted values ​​are far from the specification limit boundary are designated as first parameters and granted early termination authorization. In subsequent tests, the number of parameters that need to be sampled in all rounds can be reduced, which is beneficial to reducing test time.

[0064] Furthermore, step S105 may include: obtaining the steady-state evaluation value and its confidence level in the steady-state evaluation result; determining that the preset test early termination condition is met when the steady-state evaluation value is steady-state and the confidence level is greater than or equal to a preset confidence level threshold; generating a batch cutoff signal for the remaining rounds; skipping the sampling of the remaining rounds according to the batch cutoff signal for the remaining rounds, and generating a first test result with a first parameter according to the first measured result and the steady-state evaluation result.

[0065] Specifically, the steady-state evaluation results output by the time-series steady-state evaluation model include steady-state evaluation values ​​and their confidence levels. The confidence level is a quantitative representation of the reliability of the steady-state evaluation values ​​by the model; the larger the value, the higher the reliability.

[0066] The steady-state evaluation value and confidence level are compared with the preset early termination conditions. If the steady-state evaluation value is steady-state and the confidence level is greater than or equal to the preset confidence level threshold, the test is deemed to meet the early termination conditions. The ATE generates a batch cutoff signal for the remaining rounds, stops sampling for the remaining rounds based on this signal, and generates the first test result for the first parameter based on the obtained measured value of the Kth round and the steady-state evaluation result.

[0067] In this embodiment, early termination is triggered when the confidence level of the steady-state assessment is high enough, reducing the risk of early termination due to model misjudgment; the signal is truncated in batches according to the remaining rounds to skip all remaining rounds of the current parameter, which improves the testing efficiency.

[0068] Furthermore, step S106 may include: obtaining the steady-state evaluation value and its confidence level in the steady-state evaluation result; determining that the steady-state evaluation result does not meet the test early termination condition when the steady-state evaluation value is non-steady-state or the confidence level is less than a preset confidence level threshold; performing iterative testing on the first parameter until the obtained steady-state evaluation result meets the test early termination condition, and obtaining the second test result based on the measured result when the test early termination condition is met and the steady-state evaluation result; or, sampling the first parameter for all rounds to obtain the second test result.

[0069] Specifically, the steady-state evaluation result output by the time-series steady-state evaluation model includes the steady-state evaluation value and its confidence level. If the steady-state evaluation value is non-steady-state, it indicates that based on the time-series change trend of the measured values ​​in the first K rounds, subsequent rounds have not yet entered a stable state, and the measured value of this parameter may fluctuate significantly, making early termination inadvisable. If the steady-state evaluation value is steady-state but the confidence level is less than the preset confidence level threshold, it indicates that the model's judgment result is not reliable enough, and early termination carries a certain risk, making early termination inadvisable. Neither of the above two situations meets the conditions for early termination of the test.

[0070] If the early termination condition is not met, the ATE continues sampling for the next round (round K+1) of the current first parameter to obtain new measured data. Then, the time-series data from the previous K+1 rounds are re-input into the model to obtain the steady-state evaluation value and confidence level again, and the early termination condition is re-evaluated. If the early termination condition is met after re-evaluation, a second test result is generated based on the measured data and steady-state evaluation result of that round. If the condition is still not met after re-evaluation, the next round of sampling is performed and re-evaluated, and this process is iterated. If the above process is repeated until all N rounds of sampling are completed and the early termination condition is still not met, a second test result is generated based on the measured data from all N rounds.

[0071] In this embodiment, when the steady-state evaluation value is unsteady or the confidence level is insufficient, the changing trend of the parameter state is continuously evaluated through iterative testing. Iterative testing ensures that early termination may still be triggered, thus ensuring the possibility of reducing testing time. If the early termination condition is not met, all rounds of sampling are completed to ensure that the first parameter obtains accurate test results.

[0072] Furthermore, the above-mentioned chip testing method based on parameter correlation may also include: for the first parameter corresponding to the first test result, randomly select the first parameter for the remaining rounds of sampling to obtain the sampling test results; when the sampling test results of a preset number of first parameters do not meet the test early termination condition, incrementally train the time-series steady-state evaluation model based on the first test result of the first parameter and the sampling test results.

[0073] Specifically, after completing mass production testing of a batch of chips, a portion of the test parameters that have been granted early termination authorization and have actually been terminated (i.e., the first parameter corresponding to the first test result) are randomly selected as inspection samples according to a preset sampling ratio.

[0074] Sampling is performed on the remaining rounds of the sampled data that were skipped, yielding the actual test results. These results are then compared to the corresponding steady-state interval to determine if the test meets the early termination criteria. If the actual test results for the first parameter (a preset number, such as the cumulative number of abnormal samples across multiple consecutive batches) do not meet the early termination criteria, it indicates a systematic deviation in the prediction accuracy of the time-series steady-state assessment model, and the model may be drifting.

[0075] The preset quantity can be set according to the actual situation of the production line. For example, it can be set to at least one abnormal sample in each of three consecutive batches, which avoids frequent unnecessary model updates due to a single occasional abnormal sample, and can respond in a timely manner when the model drifts.

[0076] When the above triggering conditions are met, the first measured result of the first parameter and the sampled measured result are used as new training samples to incrementally train the time series steady-state evaluation model. The updated model is then deployed to the test system.

[0077] Furthermore, when the sampled test results of a preset number of first parameters do not meet the early termination conditions, the types of associated parameters involved in the sampling anomalies can be statistically analyzed. If the sampling anomalies are concentrated on the first parameter corresponding to a certain association (for example, due to the drift in the association between parameter T1 and parameter T2, resulting in a large number of abnormal sampling results for parameter T2), the parameter association graph can be corrected, reducing the weight of the association or re-evaluating its effectiveness. Graph correction can be performed after accumulating the statistical results of multiple batches of sampling to ensure the stability of the graph.

[0078] In this embodiment, the prediction accuracy of the model is continuously monitored by sampling. When the number of accumulated sampling anomalies exceeds a preset threshold, incremental training is triggered. This avoids frequent model updates caused by single, occasional anomalies and can respond in a timely manner when the model experiences systematic drift, thus maintaining the model's accuracy and improving the accuracy of chip testing.

[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing related hardware through computer-readable instructions. These computer-readable instructions can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, optical disk, or read-only memory (ROM), or random access memory (RAM).

[0080] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0081] Further reference Figure 2 As a response to the above Figure 1The implementation of the method shown in this application provides an embodiment of a chip testing device based on parameter correlation. This device embodiment is similar to... Figure 1 The method embodiments shown correspond to those described.

[0082] like Figure 2 As shown, the chip testing device 200 based on parameter correlation described in this embodiment includes: a spectrum acquisition module 201, a core sampling module 202, a parameter division module 203, a first sampling module 204, a first generation module 205, an iterative testing module 206, a second sampling module 207, and a result generation module 208, wherein: The graph acquisition module 201 is used to acquire the parameter correlation graph of the chip under test, and to determine the core parameters and non-core parameters of the chip under test through the parameter correlation graph.

[0083] The core sampling module 202 is used to sample the core parameters in all rounds to obtain the core test results.

[0084] The parameter partitioning module 203 is used to partition non-core parameters into first parameters and second parameters based on the core test results and the correlation in the parameter correlation graph. The first parameters have the authorization to terminate the test early.

[0085] The first sampling module 204 is used to sample each first parameter for a preset number of rounds to obtain a first measured result, and input the first measured result into the time series steady-state evaluation model to obtain a steady-state evaluation result.

[0086] The first generation module 205 is used to generate a first test result of the first parameter based on the first measured result and the steady-state evaluation result when the steady-state evaluation result meets the preset test early termination conditions.

[0087] The iterative testing module 206 is used to perform iterative testing on the first parameter until the obtained steady-state evaluation result meets the test early termination condition or all rounds of sampling are completed when the steady-state evaluation result does not meet the test early termination condition, and obtain the second test result.

[0088] The second sampling module 207 is used to sample each second parameter for all rounds to obtain the third test result for each second parameter.

[0089] The result generation module 208 is used to generate chip test results for the chip under test based on all the obtained test results.

[0090] In this embodiment, core parameters are determined through parameter correlation graphs, and core test results are obtained by sampling them through all rounds. Core parameters are strongly correlated with multiple parameters, and their measurement results can predict other parameters. Based on the correlation between the core test results and the parameter correlation graphs, non-core parameters are divided into first parameters and second parameters. The first parameter uses a time-series steady-state evaluation model to determine whether sampling should be terminated early, while the second parameter undergoes sampling through all rounds, achieving differentiated processing. Only core parameters are fully tested; non-core first parameters are sampled through a preset number of rounds, and if the conditions are met, early termination is achieved, reducing the total number of test rounds and test time for a single chip. If the steady-state evaluation does not meet the early termination conditions, iterative testing is used to continuously evaluate the parameter state until a reliable result is obtained, ensuring test accuracy. Sampling through all rounds for the second parameter ensures test accuracy. This application makes real-time determinations during the testing process, allowing for early prediction of the state of subsequent rounds and proactive termination, improving test efficiency while ensuring test coverage.

[0091] In some optional implementations of this embodiment, the chip testing device 200 based on parameter association may further include: a history acquisition module, a correlation calculation module, a direction determination module, and a map construction module, wherein: The history acquisition module is used to acquire historical test data of the chip.

[0092] The correlation calculation module is used to calculate the correlation coefficients between various parameters of the chip based on historical test data, and to determine the relevant parameter pairs based on the obtained correlation coefficients.

[0093] The direction determination module is used to determine the correlation direction of each relevant parameter pair through a regression model.

[0094] The graph construction module is used to construct the parameter association graph of the chip based on each relevant parameter pair and its corresponding association direction.

[0095] In this embodiment, correlation is determined by the correlation coefficient between parameters to achieve the mining of association relationships; the bidirectional prediction error of the relevant parameter pairs is calculated by the regression model to determine the association direction, thus providing a data foundation for subsequent prediction of other parameters based on core parameters; the construction of parameter association graphs is beneficial to improving subsequent testing efficiency.

[0096] In some optional implementations of this embodiment, the chip testing device 200 based on parameter association may further include: a data acquisition module, a test acquisition module, a label generation module, and a model training module, wherein: The data acquisition module is used to acquire historical test data of the chip.

[0097] The measured data acquisition module is used to obtain the first historical measured result obtained by sampling the parameter in a preset number of rounds from historical test data for each parameter of the chip, and the second historical measured result obtained by sampling after the preset number of rounds.

[0098] The label generation module is used to calculate the steady-state interval of the parameters based on the first historical measurement results, and to generate training labels based on the steady-state interval and the second historical measurement results. The training labels include steady-state and non-steady-state labels.

[0099] The model training module is used to train an initial time-series steady-state evaluation model based on the first and second historical measured results of each parameter and the training labels, thereby obtaining the time-series steady-state evaluation model.

[0100] In this embodiment, a steady-state interval is calculated based on historical test data and training labels are generated, thereby training a time-series steady-state evaluation model. The model can learn the mapping relationship between the sampling value sequence of the first K rounds and the steady-state state of subsequent rounds from a large number of historical samples, providing data support for early termination decisions during testing, which is beneficial to improving testing efficiency.

[0101] In some optional implementations of this embodiment, the parameter partitioning module 203 may include: an association determination submodule, a prediction calculation submodule, a first partitioning submodule, and a second partitioning submodule, wherein: The association determination submodule is used to determine the associated parameters of the core parameters based on the association relationships in the parameter association graph. The associated parameters are non-core parameters.

[0102] The prediction calculation submodule is used to calculate the predicted values ​​of each related parameter based on the core test results.

[0103] The first partitioning submodule is used to partition each associated parameter into a first parameter when the predicted value of the associated parameter meets the preset specification conditions. The first parameter has the authorization to terminate the test early.

[0104] The second partitioning submodule is used to partition the associated parameter into a second parameter when the predicted value of the associated parameter does not meet the specification conditions. The second parameter does not have the authorization to terminate the test early.

[0105] In this embodiment, the correlation parameters are determined by the correlation graph and the predicted values ​​are calculated based on the core test results. Parameters whose predicted values ​​are far from the specification limit boundary are designated as first parameters and granted early termination authorization. In subsequent tests, the number of parameters that need to be sampled in all rounds can be reduced, which is beneficial to reducing test time.

[0106] In some optional implementations of this embodiment, the first generation module 205 may include: an evaluation acquisition submodule, a termination determination submodule, a signal generation submodule, and a first generation submodule, wherein: The evaluation acquisition submodule is used to obtain the steady-state evaluation value and its confidence level from the steady-state evaluation results.

[0107] The termination determination submodule is used to determine the test early termination condition when the steady-state evaluation value is steady-state and the confidence level is greater than or equal to the preset confidence level threshold.

[0108] The signal generation submodule is used to generate batch truncation signals for the remaining rounds.

[0109] The first generation submodule is used to skip the sampling of the remaining rounds by batch truncating the signal according to the remaining rounds, and to generate the first test result of the first parameter according to the first measured result and the steady-state evaluation result.

[0110] In this embodiment, early termination is triggered when the confidence level of the steady-state assessment is high enough, reducing the risk of early termination due to model misjudgment; the signal is truncated in batches according to the remaining rounds to skip all remaining rounds of the current parameter, which improves the testing efficiency.

[0111] In some optional implementations of this embodiment, the iterative testing module 206 may include: an acquisition submodule, a determination submodule, an iterative testing submodule, and a full sampling submodule, wherein: The acquisition submodule is used to obtain the steady-state evaluation value and its confidence level from the steady-state evaluation results.

[0112] The determination submodule is used to determine whether the steady-state evaluation result does not meet the test termination conditions when the steady-state evaluation value is non-steady-state or the confidence level is less than the preset confidence level threshold.

[0113] The iterative testing submodule is used to perform iterative testing on the first parameter until the obtained steady-state evaluation result meets the test early termination condition, and obtain the second test result based on the measured result and steady-state evaluation result when the test early termination condition is met.

[0114] The full sampling submodule is used to sample the first parameter in all rounds to obtain the second test result.

[0115] In this embodiment, when the steady-state evaluation value is unsteady or the confidence level is insufficient, the changing trend of the parameter state is continuously evaluated through iterative testing. Iterative testing ensures that early termination may still be triggered, thus ensuring the possibility of reducing testing time. If the early termination condition is not met, all rounds of sampling are completed to ensure that the first parameter obtains accurate test results.

[0116] In some optional implementations of this embodiment, the chip testing device 200 based on parameter association may further include: a sampling inspection module and an incremental training module, wherein: The sampling module is used to randomly select the first parameter corresponding to the first test result and perform sampling for the remaining rounds to obtain the sampling test result.

[0117] The incremental training module is used to incrementally train the time-series steady-state evaluation model based on the first measured result of the first parameter and the sampled measured results when the sampling test results of the preset number of first parameters do not meet the early termination condition.

[0118] In this embodiment, the prediction accuracy of the model is continuously monitored by sampling. When the number of accumulated sampling anomalies exceeds a preset threshold, incremental training is triggered. This avoids frequent model updates caused by single, occasional anomalies and can respond in a timely manner when the model experiences systematic drift, thus maintaining the model's accuracy and improving the accuracy of chip testing.

[0119] To address the aforementioned technical problems, embodiments of this application also provide a computer device. Please refer to [link / reference needed]. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device in this embodiment.

[0120] The computer device 3 includes a memory 31, a processor 32, and a network interface 33 that are interconnected via a system bus. It should be noted that only the computer device 3 with components 31-33 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components can be implemented alternatively. Those skilled in the art will understand that the computer device described here is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0121] The computer device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The computer device can interact with the user via a keyboard, mouse, remote control, touchpad, or voice control.

[0122] The memory 31 includes at least one type of readable storage medium, including flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 31 may be an internal storage unit of the computer device 3, such as the hard disk or memory of the computer device 3. In other embodiments, the memory 31 may also be an external storage device of the computer device 3, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device 3. Of course, the memory 31 may also include both the internal storage unit and its external storage device of the computer device 3. In this embodiment, the memory 31 is typically used to store the operating system and various application software installed on the computer device 3, such as computer-readable instructions for chip testing methods based on parameter correlation. In addition, the memory 31 can also be used to temporarily store various types of data that have been output or will be output.

[0123] In some embodiments, the processor 32 may be a central processing unit (CPU), controller, microcontroller, microprocessor, or other data processing chip. The processor 32 is typically used to control the overall operation of the computer device 3. In this embodiment, the processor 32 is used to execute computer-readable instructions stored in the memory 31 or to process data, for example, to execute computer-readable instructions of the parameter-association-based chip testing method.

[0124] The network interface 33 may include a wireless network interface or a wired network interface, which is typically used to establish communication connections between the computer device 3 and other electronic devices.

[0125] The computer device provided in this embodiment can execute the above-described parameter-association-based chip testing method. Here, the parameter-association-based chip testing method can be any of the parameter-association-based chip testing methods described in the various embodiments above.

[0126] In this embodiment, core parameters are determined through parameter correlation graphs, and core test results are obtained by sampling them through all rounds. Core parameters are strongly correlated with multiple parameters, and their measurement results can predict other parameters. Based on the correlation between the core test results and the parameter correlation graphs, non-core parameters are divided into first parameters and second parameters. The first parameter uses a time-series steady-state evaluation model to determine whether sampling should be terminated early, while the second parameter undergoes sampling through all rounds, achieving differentiated processing. Only core parameters are fully tested; non-core first parameters are sampled through a preset number of rounds, and if the conditions are met, early termination is achieved, reducing the total number of test rounds and test time for a single chip. If the steady-state evaluation does not meet the early termination conditions, iterative testing is used to continuously evaluate the parameter state until a reliable result is obtained, ensuring test accuracy. Sampling through all rounds for the second parameter ensures test accuracy. This application makes real-time determinations during the testing process, allowing for early prediction of the state of subsequent rounds and proactive termination, improving test efficiency while ensuring test coverage.

[0127] This application also provides another embodiment, namely, providing a computer-readable storage medium storing computer-readable instructions that can be executed by at least one processor to cause the at least one processor to perform the steps of the parameter-association-based chip testing method described above.

[0128] In this embodiment, core parameters are determined through parameter correlation graphs, and core test results are obtained by sampling them through all rounds. Core parameters are strongly correlated with multiple parameters, and their measurement results can predict other parameters. Based on the correlation between the core test results and the parameter correlation graphs, non-core parameters are divided into first parameters and second parameters. The first parameter uses a time-series steady-state evaluation model to determine whether sampling should be terminated early, while the second parameter undergoes sampling through all rounds, achieving differentiated processing. Only core parameters are fully tested; non-core first parameters are sampled through a preset number of rounds, and if the conditions are met, early termination is achieved, reducing the total number of test rounds and test time for a single chip. If the steady-state evaluation does not meet the early termination conditions, iterative testing is used to continuously evaluate the parameter state until a reliable result is obtained, ensuring test accuracy. Sampling through all rounds for the second parameter ensures test accuracy. This application makes real-time determinations during the testing process, allowing for early prediction of the state of subsequent rounds and proactive termination, improving test efficiency while ensuring test coverage.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0130] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A chip testing method based on parameter correlation, characterized in that, Includes the following steps: Obtain the parameter correlation map of the chip under test, and determine the core parameters and non-core parameters of the chip under test through the parameter correlation map; The core parameters are sampled in all rounds to obtain the core test results; Based on the core test results and the correlation in the parameter correlation graph, the non-core parameters are divided into a first parameter and a second parameter. The first parameter has the authority to terminate the test early. For each first parameter, the first parameter is sampled for a preset number of rounds to obtain a first measured result, and the first measured result is input into the time series steady-state evaluation model to obtain a steady-state evaluation result; When the steady-state evaluation result meets the preset test early termination condition, a first test result of the first parameter is generated based on the first measured result and the steady-state evaluation result. When the steady-state evaluation result does not meet the test early termination condition, the first parameter is iteratively tested until the obtained steady-state evaluation result meets the test early termination condition or all rounds of sampling are completed, and a second test result is obtained. Sample each second parameter for all rounds to obtain a third test result for each second parameter; Based on all the test results obtained, the chip test results of the chip under test are generated.

2. The chip testing method based on parameter correlation according to claim 1, characterized in that, Before the step of obtaining the parameter correlation map of the chip under test, the method further includes: Obtain historical test data for the chip; Calculate the correlation coefficients between the parameters of the chip based on the historical test data, and determine the relevant parameter pairs based on the obtained correlation coefficients; The correlation direction of each relevant parameter pair is determined by regression model; Based on the relevant parameter pairs and their corresponding association directions, a parameter association map of the chip is constructed.

3. The chip testing method based on parameter correlation according to claim 1, characterized in that, Before the step of obtaining the parameter correlation map of the chip under test, the method further includes: Obtain historical test data for the chip; For each parameter of the chip, a first historical test result obtained from the historical test data after a preset number of sampling rounds, and a second historical test result obtained from sampling after the preset number of sampling rounds are obtained. The steady-state interval of the parameter is calculated based on the first historical measurement result, and training labels are generated based on the steady-state interval and the second historical measurement result. The training labels include steady-state and non-steady-state conditions. Based on the first and second historical measured results of each parameter and the training labels, the initial time-series steady-state evaluation model is trained, and the time-series steady-state evaluation model is obtained.

4. The chip testing method based on parameter correlation according to claim 1, characterized in that, The step of dividing the non-core parameters into first parameters and second parameters based on the core test results and the correlation in the parameter correlation graph includes: Based on the correlation relationships in the parameter correlation graph, the correlation parameters of the core parameters are determined, and the correlation parameters are non-core parameters; Based on the core test results, calculate the predicted values ​​of each related parameter; For each associated parameter, when the predicted value of the associated parameter meets the preset specification conditions, the associated parameter is classified as a first parameter, and the first parameter has the authorization to terminate the test early. When the predicted value of the associated parameter does not meet the specification conditions, the associated parameter is classified as a second parameter, and the second parameter does not have the authorization to terminate the test early.

5. The chip testing method based on parameter correlation according to claim 1, characterized in that, The step of generating a first test result for the first parameter based on the first measured result and the steady-state evaluation result when the steady-state evaluation result meets the preset test early termination conditions includes: Obtain the steady-state evaluation value and its confidence level from the steady-state evaluation results; When the steady-state evaluation value is steady-state and the confidence level is greater than or equal to the preset confidence level threshold, it is determined that the preset test early termination condition is met. Generate batch cutoff signals for the remaining rounds; The remaining rounds of sampling are skipped by batch truncation of the signal, and the first test result of the first parameter is generated based on the first measured result and the steady-state evaluation result.

6. The chip testing method based on parameter correlation according to claim 1, characterized in that, The step of iteratively testing the first parameter until the steady-state evaluation result meets the early termination condition or all rounds of sampling are completed, when the steady-state evaluation result does not meet the early termination condition, to obtain the second test result includes: Obtain the steady-state evaluation value and its confidence level from the steady-state evaluation results; When the steady-state evaluation value is non-steady-state or the confidence level is less than the preset confidence threshold, it is determined that the steady-state evaluation result does not meet the test early termination condition; The first parameter is iteratively tested until the obtained steady-state evaluation result meets the early termination condition of the test. A second test result is then obtained based on the measured result and the steady-state evaluation result when the early termination condition is met; or... The first parameter is sampled for all rounds to obtain the second test result.

7. The chip testing method based on parameter correlation according to claim 1, characterized in that, The method further includes: For the first parameter corresponding to the first test result, the first parameter is randomly selected for sampling in the remaining rounds to obtain the actual test results. When the sampling test results of the preset number of first parameters do not meet the early termination condition of the test, the time-series steady-state evaluation model is incrementally trained based on the first test results of the first parameter and the sampling test results.

8. A chip testing device based on parameter correlation, characterized in that, include: The graph acquisition module is used to acquire the parameter correlation graph of the chip under test, and to determine the core parameters and non-core parameters of the chip under test through the parameter correlation graph. The core sampling module is used to sample the core parameters in all rounds to obtain the core test results. The parameter partitioning module is used to partition the non-core parameters into a first parameter and a second parameter based on the core test results and the correlation in the parameter correlation graph. The first parameter has the authority to terminate the test early. The first sampling module is used to sample each first parameter for a preset number of rounds to obtain a first measured result, and input the first measured result into the time series steady-state evaluation model to obtain a steady-state evaluation result; The first generation module is used to generate a first test result of the first parameter based on the first measured result and the steady-state evaluation result when the steady-state evaluation result meets the preset test early termination conditions. The iterative testing module is used to perform iterative testing on the first parameter until the obtained steady-state evaluation result meets the early termination condition or all rounds of sampling are completed when the steady-state evaluation result does not meet the early termination condition, and obtain the second test result. The second sampling module is used to sample each second parameter for all rounds to obtain the third test result for each second parameter; The result generation module is used to generate chip test results for the chip under test based on all the obtained test results.

9. A computer device comprising a memory and a processor, the memory storing computer-readable instructions, wherein the processor, when executing the computer-readable instructions, implements the steps of the chip testing method based on parameter association as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the steps of the chip testing method based on parameter association as described in any one of claims 1 to 7.

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