A sleeve type via hole capacitor and a manufacturing method thereof

Abstract

The application discloses a sleeve type through-hole capacitor and a manufacturing method thereof, and relates to the field of electronic packaging. The sleeve type through-hole capacitor comprises a through hole arranged in a substrate core plate, and an outer conductive layer is arranged on the hole wall of the through hole. A hole cavity surrounded by the outer conductive layer is filled with an insulating medium body, and a through hole is arranged on the hole wall of the insulating medium body along the axial direction. An inner conductive layer is arranged on the hole wall of the through hole. The outer conductive layer and the inner conductive layer are insulated from each other through the insulating medium body, and an equivalent capacitor is formed between the outer conductive layer and the inner conductive layer. The capacitor is characterized in that the outer conductive layer, the insulating medium body and the inner conductive layer are arranged in the through hole of the substrate core plate, so that the through hole itself forms a sleeve type capacitor structure, thereby maintaining the original interlayer electrical interconnection function of the through hole and constructing a filtering capacitor inside the through hole. The capacitor does not need to additionally increase independent capacitor elements on the surface layer or inside of the substrate, and is beneficial to saving the design space of the substrate.

Description

Technical Field

[0001] This invention relates to electronic packaging technology, specifically to a sleeve-type through-hole capacitor and its manufacturing method. Background Technology

[0002] As chip operating frequencies continue to increase, high-frequency noise suppression in the chip power distribution network (PDN) becomes a critical aspect of packaging design. To reduce high-frequency power supply noise at the chip level, decoupling capacitors are typically placed on the package substrate near the chip.

[0003] Existing decoupling capacitor solutions mainly include the following:

[0004] Deep trench capacitors (DTC): Deep trench structures are formed on silicon interposers using chip etching processes. Their drawbacks include high process costs and difficulty in achieving high voltage withstand designs.

[0005] Embedded capacitors: The capacitor structure is embedded inside the substrate. Its disadvantages are that the manufacturing process is complex, the cost is high, and it occupies the internal space of the substrate.

[0006] Multi-layer ceramic capacitors (MLCCs): As discrete components mounted on the substrate surface, their disadvantages include a large parasitic inductance (usually exceeding 200 pH), a high equivalent series resistance (exceeding several milliohms), and a large size that occupies the substrate surface space. At the same time, due to process limitations, their mounting position is difficult to place close to the chip, resulting in large mounting parasitic parameters and limited filtering effect on high-frequency noise.

[0007] Traditional chip packaging substrates consist of a fiberglass copper-clad laminate and a plated through-hole (PTH). The fiberglass core primarily provides support, and its structure should be preserved as much as possible. However, to connect the upper and lower electrical networks, holes need to be drilled to create the PTH. The PTH is hollow inside, thus wasting internal space.

[0008] Based on the shortcomings of the existing technology, a technical solution is needed that can effectively filter out high-frequency power supply noise without significantly increasing process costs and substrate space occupation. Summary of the Invention

[0009] The purpose of this invention is to provide a sleeve-type through-hole capacitor and its manufacturing method, so as to solve the problem that the existing decoupling capacitor schemes cannot effectively filter out high-frequency power supply noise without significantly increasing process costs and substrate space occupation.

[0010] To achieve the above objectives, the present invention provides the following technical solution:

[0011] In a first aspect, the present invention provides a sleeve-type through-hole capacitor, including a through-hole disposed in a substrate core plate, wherein an outer conductive layer is provided on the wall of the through-hole;

[0012] The cavity enclosed by the outer conductive layer is filled with an insulating dielectric body, and the insulating dielectric body has a through hole along its axial direction.

[0013] An inner conductive layer is provided on the wall of the through hole;

[0014] The outer conductive layer and the inner conductive layer are insulated from each other by the insulating medium, and an equivalent capacitance is formed between the outer conductive layer and the inner conductive layer.

[0015] Furthermore, the relative permittivity of the insulating dielectric is greater than 10.

[0016] Furthermore, the inner pores formed by the inner conductive layer are filled with sealing resin.

[0017] Furthermore, the outer conductive layer is electrically connected to the first conductive layer, and the inner conductive layer is electrically connected to the second conductive layer. The first conductive layer and the second conductive layer are insulated from each other and are located on opposite sides of the thickness direction of the substrate core.

[0018] Furthermore, at least one side of the substrate core is laminated with an add-on dielectric layer and a conductive line layer formed on the add-on dielectric layer, and the outer conductive layer or the inner conductive layer is electrically connected to the conductive line layer through a conductive blind via disposed in the add-on dielectric layer.

[0019] Secondly, the present invention provides a method for manufacturing a sleeve-type through-hole capacitor, comprising the following steps:

[0020] S1. Process an external hole on the substrate core board;

[0021] S2. An outer conductive layer is formed on the wall of the outer hole;

[0022] S3. Fill the cavity surrounded by the outer conductive layer with an insulating medium to form an insulating medium body;

[0023] S4. An inner hole is machined in the insulating dielectric body;

[0024] S5. An inner conductive layer is formed on the wall of the inner hole.

[0025] Furthermore, the relative permittivity of the insulating medium is greater than 10.

[0026] Furthermore, after forming the inner conductive layer, the internal cavity of the inner hole is filled with resin.

[0027] Compared with the prior art, the present invention provides a sleeve-type through-hole capacitor and its manufacturing method. By setting an outer conductive layer, an insulating dielectric body and an inner conductive layer in the through-hole of the substrate core board, the through-hole itself forms a sleeve-type capacitor structure, thereby maintaining the original interlayer electrical interconnection function of the through-hole while constructing a filter capacitor inside the through-hole.

[0028] Since this capacitor structure utilizes the original internal hollow space of the through hole, there is no need to add an additional independent capacitor element on the surface or inside of the substrate, which helps to save substrate design space.

[0029] Meanwhile, the outer conductive layer and the inner conductive layer are themselves components of the power supply network path. The additional parasitic inductance and equivalent series resistance introduced by this structure are smaller than those of discrete MLCC components mounted on the substrate surface, which is beneficial to improving the high-frequency filtering effect, especially suitable for filtering scenarios of high-frequency power supply noise above 50MHz.

[0030] The technical solution of this application does not require the introduction of expensive semiconductor etching equipment. It can be achieved based on conventional drilling, electroplating and filling processes in the existing packaging substrate manufacturing process. The manufacturing cost is controllable and has good compatibility with existing production lines. By adjusting the outer diameter, inner diameter, relative permittivity of the insulating dielectric and the thickness of the substrate core, the required capacitance value can be flexibly designed. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0032] Figure 1 A top view cross-sectional schematic diagram of a sleeve-type through hole provided in an embodiment of the present invention;

[0033] Figure 2 A flowchart illustrating the method provided in this embodiment of the invention;

[0034] Figure 3 This is a side cross-sectional schematic diagram of a sleeve-type through hole provided in an embodiment of the present invention;

[0035] Figure 4 This is a schematic block diagram illustrating the principle of equivalent capacitance of a sleeve-type through-hole provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the core board structure of a traditional chip packaging substrate, which serves as the background technology of this invention.

[0037] Explanation of reference numerals in the attached figures:

[0038] 1. Outer conductive layer; 2. Insulating dielectric; 3. Inner conductive layer. Detailed Implementation

[0039] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0040] As attached Figure 1 To be continued Figure 5 As shown:

[0041] Example 1:

[0042] This embodiment provides a sleeve-type through-hole capacitor, including a through-hole disposed in a substrate core. The through-hole has a sleeve-type structure with three layers.

[0043] The substrate core can be made of conventional core materials used in the packaging substrate field, such as glass fiber reinforced epoxy resin copper clad laminate or other insulating core materials suitable for packaging substrates. The thickness of the substrate core can be determined according to the packaging design requirements; in this embodiment, the core thickness is 1 mm.

[0044] An outer conductive layer 1 is disposed on the wall of the initial external hole machined in the substrate core board. The material of the outer conductive layer 1 is usually copper, but other conductive metal materials, such as gold, silver, aluminum or their alloys, can also be used. The outer conductive layer 1 can be formed by electroplating, and its thickness is generally 5μm~50μm, which can be determined according to the conductivity and current carrying capacity requirements and the electroplating process capability.

[0045] An insulating dielectric 2 fills the cavity enclosed by the outer conductive layer 1. The insulating dielectric 2 has a through-hole along its axial direction, which is used to accommodate the inner conductive layer 3. The function of the insulating dielectric 2 is to electrically insulate the outer conductive layer 1 and the inner conductive layer 3 from each other, and to act as a dielectric layer that forms a capacitance effect between them.

[0046] The insulating dielectric 2 is made of an insulating material, which can be an insulating material with a relative permittivity greater than 10, such as a ceramic powder-filled resin system or a high-dielectric-constant polymer material. In this embodiment, the insulating dielectric 2 uses a barium titanate (BaTiO3) ceramic powder-filled epoxy resin system. The filling volume fraction of barium titanate can be adjusted according to the target capacitance value. In this embodiment, the filling volume fraction is 50%~80%. Using a dielectric material with a relative permittivity greater than 10 can achieve a higher capacitance per unit length within a limited space.

[0047] An inner conductive layer 3 is disposed on the wall of the through hole of the insulating dielectric 2. The material of the inner conductive layer 3 is usually copper, but other conductive metal materials can also be used. The inner conductive layer 3 can be formed by electroplating, and its thickness is generally 5μm~50μm.

[0048] Electrical insulation between the outer conductive layer 1 and the inner conductive layer 3 is achieved through an insulating dielectric 2. When the outer conductive layer 1 and the inner conductive layer 3 are connected to power networks at different potentials (e.g., the positive terminal of the power supply and the return ground), an equivalent capacitance is formed between them, which can be used to filter out high-frequency noise in the power distribution network.

[0049] In this embodiment, the cavity inside the inner hole formed by the inner conductive layer 3 is filled with sealing resin. The sealing resin can be epoxy resin or other filling resins suitable for the encapsulation process. The sealing resin prevents solder, flux residues or other foreign matter from entering the inner hole cavity during subsequent substrate lamination, soldering or surface mount processes, and prevents unintended electrical connections between the inner and outer conductive layers.

[0050] The outer conductive layer 1 and the inner conductive layer 3 are connected to conductive layers at different potentials. In this embodiment, the outer conductive layer 1 is electrically connected to the ground layer (GND) located below the substrate core, and the inner conductive layer 3 is electrically connected to the power layer (VCC) located above the substrate core; or vice versa. Both polarity connection methods can achieve capacitor filtering function and can be selected according to the overall wiring design of the packaging substrate.

[0051] In the packaging substrate design, at least one side of the substrate core board is laminated with an add-on dielectric layer and a conductive circuit layer formed on the add-on dielectric layer. The add-on dielectric layer can be made of ABF (Ajinomoto Build-up Film) or other dielectric materials suitable for the add-on process of the packaging substrate. In this embodiment, multiple ABF dielectric layers and copper foil conductive circuit layers are laminated on the upper and lower sides of the substrate core board, and the layers are electrically interconnected through conductive blind vias formed by laser drilling and electroplating. The outer conductive layer 1 can be electrically connected to the upper power layer through conductive blind vias through the add-on dielectric layer, and the inner conductive layer 3 can be electrically connected to the lower ground layer (or the polarities are reversed) through another conductive blind via.

[0052] In this embodiment, the sleeve-type through-hole capacitor is integrated into the chip's power supply network, which, while fulfilling the original through-hole electrical interconnection function, also achieves the filtering function for high-frequency power supply noise.

[0053] Example 2:

[0054] This embodiment is basically the same as the previous embodiment, except that in this embodiment, the insulating dielectric body 2 is filled with strontium titanate (SrTiO3) ceramic powder to form a polyimide resin system.

[0055] Example 3:

[0056] This embodiment provides a method for manufacturing a sleeve-type through-hole capacitor, including:

[0057] Step 1: Provide a substrate core board and machine external holes on the substrate core board.

[0058] The substrate core can be a conventional copper-clad laminate used in the packaging substrate manufacturing industry. The external holes can be machined or laser-drilled. The diameter of the external holes is determined based on the target capacitance value and substrate thickness; in this embodiment, the diameter is 200 μm. The location of the external holes is determined based on the wiring design of the packaging substrate, corresponding to the location where copper-plated vias are required in the original design.

[0059] Step 2: Form an outer conductive layer 1 on the wall of the outer hole.

[0060] Electroplating is used to deposit metallic copper on the wall of the external hole, forming an outer conductive layer 1. Conventional pre-treatment for hole wall metallization, including descaling and chemical copper plating, can be performed before electroplating. The thickness of the outer conductive layer 1 can be determined according to conductivity requirements.

[0061] Step 3: Fill the cavity enclosed by the outer conductive layer 1 with an insulating medium to form an insulating medium body 2.

[0062] An insulating medium is filled into the outer cavity of the conductive layer 1. The insulating medium can be an insulating material with a relative permittivity greater than 10. In this embodiment, a vacuum pressure potting process is used for filling. Liquid ceramic powder-filled epoxy resin is poured into the cavity under vacuum conditions, and then cured at a set temperature. The vacuum pressure potting process helps to expel gas from the cavity, reduces air bubble defects in the filler, and ensures the compactness of the insulating medium filling.

[0063] In this embodiment, the curing temperature of the barium titanate-filled epoxy resin is 120℃~150℃, and the curing time is 30 minutes~120 minutes. The cured insulating medium 2 should fill the entire cavity surrounded by the outer conductive layer 1, and there should be no visible gaps or air gaps between it and the outer hole wall and the outer conductive layer 1.

[0064] Step 4: Machining an inner hole in insulating medium 2.

[0065] An inner hole is machined along the axial direction within the cured insulating dielectric 2. The inner hole can be machined using laser drilling or mechanical drilling. To ensure uniform dielectric thickness between the inner hole and the outer conductive layer 1, the inner and outer holes should be drilled using the same positioning reference; that is, the same set of positioning targets or positioning hole systems should be used for both drilling operations, ensuring that the deviation between the inner and outer hole axes is controlled within an acceptable process range. In this embodiment, the concentricity deviation between the inner and outer holes does not exceed ±5μm.

[0066] The inner diameter is smaller than the outer diameter. The size of the inner diameter is determined based on the target capacitance value and machining accuracy; in this embodiment, the inner diameter is 196 μm.

[0067] Step 5: Form an inner conductive layer 3 on the wall of the inner hole.

[0068] Electroplating is used to deposit metallic copper on the wall of the inner hole, forming an inner conductive layer 3. Conventional pre-treatment for hole wall metallization can be performed before electroplating. This results in a sleeve-type through-hole capacitor structure with an outer conductive layer 1, an insulating dielectric 2, and an inner conductive layer 3.

[0069] After forming the inner conductive layer 3, the internal cavity of the inner hole can be further filled with resin material. The filling resin can be epoxy resin, which is filled into the inner hole and cured through conventional potting process or screen printing process.

[0070] The capacitance value can be approximated based on the principle of a parallel-plate capacitor.

[0071] Let the outer diameter be D1, the inner diameter be D2, the effective parallel length of the insulating dielectric 2 be L (i.e., the overlap length of the inner and outer conductive layers in the thickness direction of the substrate core), the relative permittivity of the insulating dielectric 2 be ε, and the vacuum permittivity ε0 ≈ 8.85 × 10⁻⁶. -12 F / m.

[0072] The dielectric thickness between the inner and outer conductive layers is approximately H ≈ (D1 - D2) / 2;

[0073] The effective relative area between the inner and outer conductive layers is S≈π·D²·L;

[0074] The equivalent capacitance value is C≈(ε·ε0·S) / H.

[0075] Taking a specific set of parameters as an example: D1=200μm, D2=196μm, L=1mm, ε=3000, then H=2μm, S≈π×196μm×1mm≈6.16×10 -7 m 2 C≈(3000×8.85×10) -12 ×6.16×10 -7 ) / (2×10-6 )≈8.17×10 -9 F, meaning the capacitance of a single sleeve-type through-hole capacitor is approximately 8.17nF.

[0076] In the packaging substrate design, if 1000 sleeve-type through-hole capacitors as described in this application are connected in parallel between a power supply and ground, the theoretical total capacitance value is approximately 8.17μF.

[0077] It should be noted that the above calculation formulas and parameter values ​​are only used to illustrate the principles of the technical solution of this application and do not constitute a limitation on the scope of protection of this application. In actual design, the values ​​of D1, D2, L, and ε can be adjusted according to factors such as substrate thickness, target capacitance value, and processing capability.

[0078] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A sleeve-type through-hole capacitor, comprising a through-hole disposed in a substrate core plate, characterized in that, An outer conductive layer is provided on the wall of the through hole; The cavity enclosed by the outer conductive layer is filled with an insulating dielectric body, and the insulating dielectric body has a through hole along its axial direction. An inner conductive layer is provided on the wall of the through hole; The outer conductive layer and the inner conductive layer are insulated from each other by the insulating medium, and an equivalent capacitance is formed between the outer conductive layer and the inner conductive layer.

2. A sleeve-type through-hole capacitor according to claim 1, characterized in that, The relative permittivity of the insulating medium is greater than 10.

3. A sleeve-type through-hole capacitor according to claim 1, characterized in that, The inner pores formed by the inner conductive layer are filled with sealing resin.

4. A sleeve-type through-hole capacitor according to claim 1, characterized in that, The outer conductive layer is electrically connected to the first conductive layer, and the inner conductive layer is electrically connected to the second conductive layer. The first conductive layer and the second conductive layer are insulated from each other and are located on opposite sides of the thickness direction of the substrate core.

5. A sleeve-type through-hole capacitor according to claim 4, characterized in that, The first conductive layer is one of a power layer and a ground layer, and the second conductive layer is the other.

6. A sleeve-type through-hole capacitor according to claim 1, characterized in that, At least one side of the substrate core is laminated with an augmentation dielectric layer and a conductive line layer formed on the augmentation dielectric layer, and the outer conductive layer or the inner conductive layer is electrically connected to the conductive line layer through a conductive blind via disposed in the augmentation dielectric layer.

7. A method for manufacturing a sleeve-type through-hole capacitor, characterized in that, Includes the following steps: S1. Process an external hole on the substrate core board; S2. An outer conductive layer is formed on the wall of the outer hole; S3. Fill the cavity surrounded by the outer conductive layer with an insulating medium to form an insulating medium body; S4. An inner hole is machined in the insulating dielectric body; S5. An inner conductive layer is formed on the wall of the inner hole; S6. Electrically connect the outer conductive layer and the inner conductive layer to the power layer and the ground layer, respectively.

8. The manufacturing method according to claim 7, characterized in that, The relative permittivity of the insulating medium is greater than 10.

9. The manufacturing method according to claim 7, characterized in that, After the inner conductive layer is formed, the internal cavity of the inner hole is filled with resin.

10. The manufacturing method according to claim 7, characterized in that, Also includes: An augmentation dielectric layer is laminated onto at least one surface of the substrate core plate; Conductive blind vias are formed in the build-up dielectric layer, so that the outer conductive layer or the inner conductive layer is electrically connected to the conductive line layer formed on the build-up dielectric layer through the conductive blind vias.

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