Packaging structure, electronic device and method for manufacturing packaging structure

Abstract

The application provides a packaging structure, an electronic device and a preparation method of the packaging structure, and relates to the technical field of semiconductors. The packaging structure comprises a first functional device, a support structure, a first interconnection structure and a first wiring structure. The support structure is provided with a hollow part, and the first functional device is arranged in the hollow part. The first interconnection structure comprises a first dielectric support layer and a first interconnection layer. The first dielectric support layer is located in the hollow part and between the support structure and the first functional device. The first dielectric support layer at least partially surrounds the first functional device. The first interconnection layer is arranged on the first dielectric support layer, and smooth interconnection between the first functional device and the first wiring structure is realized through the first interconnection layer. No via hole or metal wire is needed, the loss between interconnections is effectively reduced, the working frequency band is expanded, the line width of the first interconnection layer can be flexibly changed, that is, the first interconnection layer matched with the impedance value of the first functional device can be set according to the impedance value of the first functional device, and the return loss and interconnection loss are reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure, an electronic device, and a method for preparing the packaging structure. Background Technology

[0002] In the research and design of high-performance, high-density phased array front-end integration, high-density integration (which can overcome spatial limitations), low-loss transmission (which can ensure signal efficiency), and low distributed parameter interconnection (which can optimize signal integrity) are the three core objectives for achieving system optimization.

[0003] Typically, to achieve high-density integration, chips can be packaged in three dimensions. In the 3D packaging design of chips in the centimeter-wave (3–30 GHz) and millimeter-wave (30–300 GHz) frequency bands, wire bonding and via interconnects are currently commonly used to implement chip signal input and output.

[0004] However, via interconnects introduce coupling effects, leading to increased transmission loss, worsened transmission matching and return loss, and consequently, decreased high-frequency performance. Gold wire bonding interconnects introduce significant parasitic inductance, increasing the distributed inductance parameters of the circuit, worsening return loss, increasing interconnect loss, and also have a lower operating bandwidth. Both of these interconnect methods, especially in the millimeter-wave band, significantly worsen transmission matching, increase loss and signal delay, and may even introduce signal oscillation, limiting the operating bandwidth and performance of 3D chip packaging. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a packaging structure, an electronic device, and a method for fabricating the packaging structure, aiming to reduce interconnection transmission loss, broaden the operating bandwidth, and improve the performance of the packaging structure.

[0006] A first aspect of this application provides a packaging structure including a first functional device, a support structure, a first interconnect structure, and a first wiring structure. The support structure has a cutout portion in which the first functional device is disposed. The first interconnect structure includes a first dielectric support layer and a first interconnect layer. The first dielectric support layer is located in the cutout portion and between the support structure and the first functional device. The first dielectric support layer at least partially surrounds the first functional device. The first interconnect layer is disposed on the first dielectric support layer and electrically connected to the first functional device. The first wiring structure is disposed on the support structure and electrically connected to the first interconnect layer.

[0007] Since the first interconnect layer is a film layer and is supported by a first dielectric support layer located on the support structure and the first functional device, the first interconnect layer can be directly connected to the pads at the connection points of the first functional device to achieve interconnection, and can also be directly connected to the first wiring structure located on one side of the support structure to achieve interconnection. In other words, the first interconnect layer enables smooth interconnection between the first functional device and the first wiring structure without vias or metal wires. This effectively reduces interconnect parasitic inductance, lowers the distributed inductance parameter of the circuit, reduces coupling effects, reduces interconnect losses, and extends the operating frequency band. It effectively solves problems in existing packaging structures such as large parasitic parameters (e.g., large parasitic inductance), degraded signal integrity, increased energy loss, and narrow bandwidth. Furthermore, the linewidth of the first interconnect layer can be flexibly changed, and network patterns can be flexibly matched between structures requiring interconnection in very short distances (e.g., the first functional device and the first wiring structure) (where the pattern accuracy can be better than 0.5μm). For example, the first interconnect layer can be set to match the impedance value of the first functional device to reduce return loss and interconnection loss. Furthermore, since the first interconnect layer can be directly connected to the pad on the connection point of the first functional device to achieve interconnection, the interconnection accuracy is high, and the size of the pad on the connection point of the first functional device does not need to be large. In this way, the selection of the first functional device will be more flexible, that is, there is no need to select the first functional device with a pad of a specific size; and the volume of the first functional device can be smaller, which is conducive to the miniaturization of the packaging structure.

[0008] For example, the first functional device includes, but is not limited to, a device with radio frequency (RF) function. When the first functional device is a device with RF function, it can be an RF functional device whose operating frequency band can cover centimeter wave (3-30 GHz) and millimeter wave (30-300 GHz).

[0009] In one possible implementation, the support structure includes a first surface, and a first wiring structure is disposed on the first surface; the first interconnect layer and the first functional device are electrically connected at the same side as the first functional device.

[0010] The electrical connection points of the first wiring structure and the first interconnect layer with the first functional device are located on the same side of the first functional device. In this way, the electrical connection points of the first interconnect layer with the first wiring structure and the first interconnect layer with the first functional device are all located on the same side of the first functional device. Compared with the electrical connection points of the first interconnect layer with the first wiring structure and the first interconnect layer with the first functional device being located on opposite sides of the first functional device, the first interconnect layer does not need to pass through the cutout, thus shortening the length of the first interconnect layer and reducing the signal loss caused by the longer length of the first interconnect layer.

[0011] In one possible implementation, the first wiring structure includes at least one first wiring layer, and the first interconnect layer is electrically connected to the at least one first wiring layer.

[0012] For example, the first wiring structure may include only one first wiring layer, and the first interconnect layer is directly connected to the first wiring layer.

[0013] For example, the first wiring structure may include multiple first wiring layers. When the first wiring structure includes multiple first wiring layers, the first interconnect layer can be directly electrically connected to any one of the first wiring layers; of course, the first interconnect layer can also be directly electrically connected to all the first wiring layers, or electrically connected to a portion of the first wiring layers (such as the first interconnect layer and two of the multiple first wiring layers). Compared with via interconnection and wire bonding interconnection, the interconnection method of this application is more flexible.

[0014] In one possible implementation, the first wiring structure includes multiple first wiring layers stacked along a direction away from the first surface and a first insulating layer located between adjacent first wiring layers. A first interconnect layer is electrically connected to the first wiring layer; or, the first interconnect layer is electrically connected to the second wiring layer; or, the first interconnect layer is electrically connected to both the first wiring layer and the second wiring layer. The first wiring layer is a first wiring layer disposed on the first surface; along a direction perpendicular to the first surface, the second wiring layer is the first wiring layer closest to the first wiring layer.

[0015] The multi-layered first wiring layer facilitates better avoidance of interference between lines, preventing interference caused by insufficient wiring space and thus affecting the performance of the package structure. Furthermore, the first interconnect layer is electrically connected to the shorter first wiring layer and / or second wiring layer, which facilitates the formation of the first interconnect layer and shortens its length, reducing signal loss due to its longer length. Moreover, compared to existing interconnect methods such as gold wire bonding (with an arch height between 50 and 100 μm), the first interconnect layer in this application achieves an interconnect height between 0 and 20 μm, resulting in a more compact package structure.

[0016] In one possible implementation, when the first interconnect layer is electrically connected to the second first wiring layer, the connection points of the second first wiring layer and the first functional device are staggered along a direction perpendicular to the first surface, and the surface of the first dielectric support layer where the first interconnect layer is located gradually rises. In this way, the first interconnect layer can be smoothly connected to the second first wiring layer on a plane that is not on the same plane as the pad at the connection point of the first functional device.

[0017] In one possible implementation, the packaging structure further includes a second interconnect structure, which includes a second dielectric support layer and a second interconnect layer; at least two adjacent first wiring layers are staggered along a direction perpendicular to the first surface, and a first insulating layer between the staggered adjacent first wiring layers is embedded with the second dielectric support layer; the second interconnect layer is disposed on the second dielectric support layer and electrically connects the staggered adjacent first wiring layers.

[0018] In other words, when the signal of the first functional device is input and / or output through the first wiring structure, not only can the first functional device and the first wiring structure be interconnected without vias or metal wires, but the first wiring layers of the first wiring structure can also be interconnected without vias or metal wires. This can further effectively reduce interconnect parasitic inductance, lower coupling effects, and thus further reduce interconnect losses.

[0019] In one possible implementation, multiple second dielectric support layers and the first dielectric support layer are at least partially integrally formed. This simplifies the manufacturing process.

[0020] For example, the first dielectric support layer and the plurality of second dielectric support layers can be integrally formed; or, the first dielectric support layer can be formed separately and the plurality of second dielectric support layers can be integrally formed; or, the first dielectric support layer can be formed separately, a portion of the second dielectric support layers can be integrally formed, and the remaining portion of the second dielectric support layers can be integrally formed; or, the first dielectric support layer and a portion of the second dielectric support layers can be integrally formed, and the remaining portion of the second dielectric support layers can be integrally formed, and so on.

[0021] In one possible implementation, the surface of the second dielectric support layer with the second interconnect layer gradually rises, so that the second interconnect layer can smoothly connect the two first wiring layers located on different planes.

[0022] In one possible implementation, the packaging structure further includes a second functional device located on the side of the first wiring structure opposite to the support structure; the second functional device is electrically connected to the first wiring structure.

[0023] This enables high-density integration through three-dimensional stacking, allowing the package structure to achieve more complex functions. Furthermore, when the first wiring layers of the first wiring structure are electrically connected through a second interconnect layer on the second dielectric support layer, thereby interconnecting the first and second functional devices, compared to the interconnect structure of traditional multifunctional devices, it can effectively reduce the losses between multiple functional device interconnections, expand the operating frequency band, and reduce the overall package size, achieving flexible, high-density, and high-performance integrated packaging of multilayer functional devices.

[0024] For example, the second functional device includes, but is not limited to, a device with radio frequency (RF) function. When the second functional device is a device with RF function, it can be an RF functional device whose operating frequency band can cover centimeter wave (3-30 GHz) and millimeter wave (30-300 GHz).

[0025] In one possible implementation, the support structure further includes a second surface opposite to the first surface; the encapsulation structure further includes a second wiring structure disposed on the second surface, and the first interconnect layer passes through the cutout and is electrically connected to the second wiring structure.

[0026] This allows for double-sided signal output from the package structure, which helps to better avoid interference between lines and prevents signal interference caused by insufficient wiring space, thus affecting the performance of the package structure.

[0027] In one possible implementation, the second wiring structure includes multiple layers of second wiring stacked along a direction away from the second surface and a second insulating layer located between two adjacent layers of second wiring; the connection points of the first layer of second wiring and the first functional device are staggered along a direction perpendicular to the second surface; a first interconnect layer passes through a cutout and is electrically connected to the first layer of second wiring; wherein the first layer of second wiring is a second wiring layer disposed on the second surface; the packaging structure further includes a third interconnect structure, the third interconnect structure including a third dielectric support layer and a third interconnect layer; at least two adjacent layers of second wiring are staggered along a direction perpendicular to the second surface, a second insulating layer between the staggered adjacent layers of second wiring embeds the third dielectric support layer, and the third interconnect layer is disposed on the third dielectric support layer and electrically connected to the staggered adjacent layers of second wiring.

[0028] In other words, when the signal of the first functional device is input and / or output through the second wiring structure, not only can the first functional device and the second wiring structure be interconnected without vias or metal wires, but the second wiring layers of the second wiring structure can also be interconnected without vias or metal wires. This achieves double-sided signal output from the package structure while further effectively reducing interconnect parasitic inductance, lowering coupling effects, and consequently further reducing interconnect losses.

[0029] For example, at least a portion of the third dielectric support layer can be integrally formed, such as multiple third dielectric support layers being integrally formed; or, a portion of the third dielectric support layer can be integrally formed, while the remaining portion is formed separately. This simplifies the process steps.

[0030] In one possible implementation, the surface of the third dielectric support layer, where the third interconnect layer is located, gradually rises. This allows the third interconnect layer to smoothly connect two second wiring layers located on different planes.

[0031] In one possible implementation, the packaging structure further includes a third functional device located on the side of the second wiring structure opposite to the support structure; the third functional device is electrically connected to the second wiring structure.

[0032] This enables higher-density integration through three-dimensional stacking, allowing the package structure to achieve more complex functions. Furthermore, when the second wiring layers of the second wiring structure are interconnected via a third interconnect layer on the third dielectric support layer to achieve interconnection between the first and third functional devices, compared to traditional multi-functional device interconnection structures, it can effectively reduce losses between interconnections of multiple functional devices, expand the operating frequency band, and reduce the overall package size, achieving flexible, high-density, and high-performance integrated packaging of multi-layer functional devices.

[0033] For example, the third functional device includes, but is not limited to, devices with radio frequency (RF) functions. When the third functional device is a device with RF functions, it can be an RF functional device whose operating frequency band can cover centimeter wave (3-30 GHz) and millimeter wave (30-300 GHz).

[0034] In one possible implementation, the packaging structure further includes a fourth functional device, which is also disposed within the cutout portion; a first dielectric support layer is also provided between the first functional device and the fourth functional device; the fourth functional device is electrically connected to the first interconnect layer. Thus, the fourth functional device is electrically connected to the first functional device through the first interconnect layer.

[0035] This allows for smooth interconnection between the first and fourth functional devices without vias or metal wires. This effectively reduces parasitic inductance and coupling effects, thereby minimizing interconnect losses and extending the operating frequency band. Furthermore, replacing vias and metal wires with a first interconnect layer reduces the interconnect length between the first and fourth functional devices, preventing increased signal loss due to excessively long lines and also contributing to a smaller package size.

[0036] For example, the fourth functional device includes, but is not limited to, devices with radio frequency (RF) functions. When the fourth functional device is a device with RF functions, it can be an RF functional device whose operating frequency band can cover centimeter wave (3-30 GHz) and millimeter wave (30-300 GHz).

[0037] In one possible implementation, the first dielectric support layer includes a plane and / or an inclined plane, wherein the plane is parallel to the first surface and the inclined plane has a preset angle with the first surface; when the first dielectric support layer includes an inclined plane, the first interconnect layer is disposed on the inclined plane.

[0038] For example, when the pad at the connection point of the first functional device needs to be electrically connected to the first wiring layer of the same height, the surface of the first dielectric support layer with the first interconnect layer can be set as a plane. When the pad at the connection point of the first functional device needs to be electrically connected to the first wiring layer of a different height, the surface of the first dielectric support layer with the first interconnect layer can be set as a slope. When the pad at the connection point of the first functional device needs to be electrically connected to both the first wiring layer of the same height and the first wiring layer of a different height, the surface of the first dielectric support layer with the first interconnect layer can be set as a combination of a plane and a slope.

[0039] For example, the preset angle may include 10°, 20°, 30°, 40°, 50° or 60°, and the specific value of the preset angle can be determined according to the height of the wiring layer to be connected by the first interconnect layer.

[0040] In one possible implementation, a ground layer is provided on the back of the first functional device; the first interconnect structure further includes a ground connection layer, which is located on the surface of the first dielectric support layer away from the first interconnect layer, and the projection of the first interconnect layer on the first surface overlaps with the projection of the ground connection layer on the first surface; the surface of the first dielectric support layer with the ground connection layer is flush with the surface of the first functional device with the ground layer, and the ground connection layer is electrically connected to the ground layer, and the ground layer can provide a reference ground signal for the ground connection layer, thus simplifying the packaging process and reducing the packaging volume.

[0041] For example, the back side of the first functional device is the lower surface of the first functional device as described below.

[0042] In one possible implementation, the shape of the first interconnect layer includes, but is not limited to, rectangular branches or stepped branches.

[0043] In one possible implementation, the first functional device includes, but is not limited to, a bare chip, a chip package structure, or a device with circuit functionality, wherein the chip package structure contains at least one bare chip.

[0044] In one possible implementation, the second functional device includes, but is not limited to, a bare chip, a chip package structure, or a device with circuit functionality, wherein the chip package structure contains at least one bare chip.

[0045] In one possible implementation, the third functional device includes, but is not limited to, a bare chip, a chip package structure, or a device with circuit functionality, wherein the chip package structure contains at least one bare chip.

[0046] In one possible implementation, the fourth functional device includes, but is not limited to, a bare chip, a chip package structure, or a device with circuit functionality, wherein the chip package structure contains at least one bare chip.

[0047] A second aspect of this application also provides an electronic device comprising a printed circuit board and a package structure of the first aspect, the package structure being electrically connected to the printed circuit board. The electronic device of the second aspect is capable of achieving all the effects of the package structure of the first aspect.

[0048] A third aspect of this application also provides a method for preparing a packaging structure, the method comprising:

[0049] The first functional device is placed in the hollow part of the supporting structure;

[0050] In the hollowed-out portion, a first interconnection structure is formed between the support structure and the first functional device. The first interconnection structure includes a first dielectric support layer and a first interconnection layer. The first dielectric support layer at least partially surrounds the first functional device, and the first interconnection layer is disposed on the first dielectric support layer and electrically connected to the first functional device.

[0051] A first wiring structure is formed on the support structure, wherein the first wiring structure is electrically connected to the first interconnect layer.

[0052] The method for preparing the third type of encapsulation structure can achieve all the effects of the first type of encapsulation structure.

[0053] When a first interconnection structure is formed between the cutout portion and the supporting structure and the first functional device, the first interconnection structure may extend beyond the supporting structure; that is, part of the area may be located within the cutout portion, and part of the area may extend beyond the cutout portion. Of course, the first interconnection structure may also not extend beyond the supporting structure.

[0054] In one possible implementation, a first interconnection structure is formed in the hollowed-out portion, and between the support structure and the first functional device, including:

[0055] A first dielectric support layer is formed in the hollowed-out portion and between the support structure and the first functional device;

[0056] A first interconnect layer is formed on the first dielectric support layer.

[0057] When a first dielectric support layer is formed in the cutout portion and between the support structure and the first functional device, the first dielectric support layer may extend beyond the support structure; that is, part of the area may be located within the cutout portion, and part of the area may extend beyond the cutout portion. Of course, the first dielectric support layer may also not extend beyond the support structure.

[0058] In one possible implementation, a first dielectric support layer is formed in the cutout portion, and between the support structure and the first functional device, comprising:

[0059] A first dielectric support layer is formed in the hollowed-out portion and between the support structure and the first functional device by additive manufacturing.

[0060] A first interconnect layer is formed on the first dielectric support layer, including:

[0061] The first interconnect layer is formed on the first dielectric support layer by additive manufacturing.

[0062] In one possible implementation, the support structure includes a first surface; a first wiring structure is formed on one side of the support structure, including:

[0063] Multiple layers of first wiring layers and a first insulating layer located between two adjacent first wiring layers are sequentially formed on the first surface;

[0064] Wherein, the first interconnect layer is electrically connected to the first wiring layer of the first layer, and / or the first interconnect layer is electrically connected to the second wiring layer of the first layer, the first wiring layer of the first layer is the first wiring layer disposed on the first surface, along the direction perpendicular to the first surface, and the second wiring layer of the first layer is the first wiring layer that is closest to the first wiring layer of the first layer.

[0065] In one possible implementation, at least two adjacent first wiring layers are staggered along a direction perpendicular to the first surface;

[0066] When forming multiple layers of first wiring layers and a first insulating layer located between two adjacent first wiring layers sequentially on the first surface, the method further includes:

[0067] A second dielectric support layer is formed within the first insulating layer between two adjacent first wiring layers that are staggered;

[0068] A second interconnect layer is formed on the second dielectric support layer;

[0069] The second interconnect layer is electrically connected to the adjacent first wiring layers that are staggered.

[0070] In one possible implementation, a second dielectric support layer is formed within a first insulating layer between two adjacent, staggered first wiring layers, including:

[0071] A second dielectric support layer is formed within a first insulating layer between two adjacent first wiring layers that are staggered and arranged by additive manufacturing.

[0072] A second interconnect layer is formed on the second dielectric support layer, including:

[0073] A second interconnect layer is formed on a second dielectric support layer using additive manufacturing.

[0074] In one possible implementation, after forming the first wiring structure on one side of the support structure, the following is also included:

[0075] A second functional device is provided on the side of the first wiring structure that is away from the support structure.

[0076] The second functional device is electrically connected to the first wiring structure.

[0077] In one possible implementation, the support structure includes a second surface, which is the surface of the support structure facing away from the first wiring structure.

[0078] After the first wiring structure is formed on one side of the support structure, it also includes:

[0079] A second wiring structure is formed on the second surface, wherein the first interconnect layer passes through the cutout and is electrically connected to the second wiring structure.

[0080] In one possible implementation, a second wiring structure is formed on the second surface, including:

[0081] A multilayer second wiring layer and a second insulating layer located between two adjacent second wiring layers are sequentially formed on the second surface;

[0082] Wherein, along the direction perpendicular to the second surface, the connection points of the first second wiring layer and the first functional device are staggered, and at least some adjacent second wiring layers are staggered; the first interconnect layer passes through the cutout and is electrically connected to the first second wiring layer, and the first second wiring layer is a second wiring layer disposed on the second surface;

[0083] When forming multiple layers of second wiring layers and a second insulating layer located between two adjacent second wiring layers sequentially on the second surface, the method further includes:

[0084] A third dielectric support layer is formed within the second insulating layer between two adjacent second wiring layers that are staggered;

[0085] A third interconnect layer is formed on the third dielectric support layer, wherein the third interconnect layer is electrically connected to two adjacent second wiring layers that are staggered.

[0086] In one possible implementation, a third dielectric support layer is formed within a second insulating layer between two staggered adjacent second wiring layers, including:

[0087] A third dielectric support layer is formed within a second insulating layer between two adjacent second wiring layers that are staggered and arranged by additive manufacturing.

[0088] A third interconnect layer is formed on the third dielectric support layer, including:

[0089] A third interconnect layer is applied to the third dielectric support layer using additive manufacturing.

[0090] In one possible implementation, after the second wiring structure is formed on the side of the support structure opposite to the first wiring structure, the following is also included:

[0091] A third functional device is installed on the side of the second wiring structure that is away from the support structure.

[0092] The third functional device is electrically connected to the second wiring structure.

[0093] In one possible implementation, the support structure includes a first surface, and a first wiring structure is disposed on the first surface; the first interconnect layer and the first functional device are electrically connected at the same side as the first functional device; a ground layer is provided on the back of the first functional device;

[0094] The hollowed-out portion, and the first interconnection structure formed between the supporting structure and the first functional device, further includes:

[0095] A ground connection layer is formed on the surface of the first dielectric support layer on the side opposite to the first interconnect layer;

[0096] The projection of the first interconnect layer on the first surface overlaps with the projection of the ground connection layer on the first surface; the surface of the first dielectric support layer with the ground connection layer is flush with the surface of the first functional device with the ground layer, and the ground connection layer is electrically connected to the ground layer.

[0097] In one possible implementation, the support structure further includes a second surface, which is the surface of the support structure facing away from the first wiring structure;

[0098] After the first wiring structure is formed on one side of the support structure, it also includes:

[0099] A multilayer second wiring layer and a second insulating layer located between two adjacent second wiring layers are sequentially formed on the second surface;

[0100] In this configuration, along the direction perpendicular to the second surface, the connection points of the first layer and the second wiring layer are staggered, the first interconnect layer passes through the cutout and is electrically connected to the first layer and the second wiring layer, and the first layer and the second wiring layer are second wiring layers disposed on the second surface; the ground layer is disposed on the same layer as the first layer and the second wiring layer.

[0101] In one possible implementation, when the first functional device is disposed in the hollow portion of the support structure, it further includes:

[0102] The fourth functional device is placed in the hollow part of the supporting structure;

[0103] A first dielectric support layer is also provided between the first functional device and the fourth functional device; the fourth functional device is electrically connected to the first interconnect layer, and the fourth functional device is electrically connected to the first functional device through the first interconnect layer. Attached Figure Description

[0104] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0105] Figure 1 This application provides a schematic diagram of the structure of a communication system according to an embodiment of the present application.

[0106] Figure 2 This is a schematic diagram of a packaging structure in the prior art;

[0107] Figure 3 This diagram shows the positional relationship between the connecting pads, conductive structures, and isolation structures.

[0108] Figure 4 This is a schematic diagram of another packaging structure in the prior art;

[0109] Figure 5 This is a schematic diagram of a packaging structure provided in an embodiment of this application;

[0110] Figure 6a A top view of a first dielectric support layer, a support structure, and a first functional device provided in an embodiment of this application;

[0111] Figure 6b A top view of another first dielectric support layer, support structure, and first functional device provided in an embodiment of this application;

[0112] Figure 6c A top view of another first dielectric support layer, support structure, and first functional device provided in an embodiment of this application;

[0113] Figure 7 This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0114] Figure 8 This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0115] Figure 9 This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0116] Figure 10 This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0117] Figure 11aThis is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0118] Figure 11b This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0119] Figure 11c This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0120] Figure 12 This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0121] Figure 13a This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0122] Figure 13b This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0123] Figure 14 This is a schematic diagram of another packaging structure provided in an embodiment of this application;

[0124] Figure 15 This is a simulation diagram showing the relationship between the microstrip lines on the chip and the microstrip lines on the packaging substrate when interconnected using gold wire bonding.

[0125] Figure 16a for Figure 15 The loss curve corresponding to the structure shown;

[0126] Figure 16b for Figure 15 The parasitic inductance distribution curve corresponding to the structure shown;

[0127] Figure 17 This is a simulation diagram showing the relationship between the isolation structure and the connection pads of the packaging substrate when interconnecting vias.

[0128] Figure 18a for Figure 17 The loss curve corresponding to the structure shown;

[0129] Figure 18b for Figure 17 The parasitic capacitance distribution curve corresponding to the structure shown;

[0130] Figure 19 A simulation diagram showing the relationships between structures within a package structure when interconnected using the interconnection method provided in the embodiments of this application;

[0131] Figure 20a for Figure 19 The loss curve corresponding to the structure shown;

[0132] Figure 20bfor Figure 19 The parasitic inductance distribution curve corresponding to the structure shown;

[0133] Figure 21 This is a simulation diagram showing the relationship between the structures within another packaging structure when interconnected using the interconnection method provided in the embodiments of this application.

[0134] Figure 22a for Figure 21 The loss curve corresponding to the structure shown;

[0135] Figure 22b for Figure 21 The parasitic inductance distribution curve corresponding to the structure shown;

[0136] Figure 23a A simulation comparison diagram of the insertion loss of related technologies and this application;

[0137] Figure 23b The simulation comparison diagram shows the parasitic inductance of related technologies and that of this application.

[0138] Figure 24 A flowchart illustrating an encapsulation structure provided in an embodiment of this application;

[0139] Figures 25a to 25g for Figure 24 A schematic diagram of the encapsulation process corresponding to the flow shown;

[0140] Figure 26 A flowchart illustrating the formation of a first wiring structure and a second interconnection structure is provided in this application embodiment;

[0141] Figures 27a to 27m for Figure 26 A schematic diagram of the encapsulation process corresponding to the flow shown;

[0142] Figure 28 A flowchart illustrating yet another packaging structure provided in this application embodiment;

[0143] Figures 29a to 29i for Figure 28 The diagram shows the structure of the encapsulation process corresponding to the flow shown.

[0144] Figure label:

[0145] 1-Communication system; 2-Base station; 3-Electronic equipment;

[0146] 10-Package structure; 11-Chip; 12-Insulating layer; 13-Wiring layer; 14-Connection pad; 15-Metal wire; 16-Isolation structure; 18-Conductive structure; RDL-19;

[0147] 20 - Supporting structure; 21 - First surface; 22 - Second surface; 23 - Hollowed-out section;

[0148] 30 - First functional device; 31 - Upper surface; 32 - Lower surface; 33 - First pad; 34 - Grounding layer;

[0149] 40 - First interconnect structure; 41 - First dielectric support layer; 42 - First interconnect layer; 43 - Ground connection layer; 411 - Dielectric support part;

[0150] 50 - First wiring structure; 51 - First wiring layer; 52 - First insulating layer; 53 - First connection terminal;

[0151] 60 - Second interconnect structure; 61 - Second dielectric support layer; 62 - Second interconnect layer;

[0152] 70 - Second functional device; 71 - Second pad;

[0153] 80 - Second wiring structure; 81 - Second wiring layer; 82 - Second insulation layer; 83 - Second connection terminal;

[0154] 90 - Third interconnect structure; 91 - Third dielectric support layer; 92 - Third interconnect layer;

[0155] 100 - Third functional device; 101 - Third pad;

[0156] 110 - Fourth functional device; 111 - Fourth pad;

[0157] 340 - Grounding layer carrier plate; 350 - Temporary carrier plate. Detailed Implementation

[0158] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0159] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, while "more" refers to two or more. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0160] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0161] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.

[0162] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0163] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0164] This application provides a communication system, see [link to relevant documentation] Figure 1 , Figure 1 This is a schematic diagram of a communication system provided in an embodiment of this application. The communication system 1 includes a base station 2 and an electronic device 3. The base station 2 and the electronic device 3 are communicatively connected.

[0165] Base station 2 may include an encapsulation structure.

[0166] This application does not limit the specific form of the electronic device 3. For example, the electronic device 3 can be a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smartwatch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk maker, a robot vacuum cleaner), a drone, radar, aerospace equipment, and vehicle-mounted equipment, etc.

[0167] Electronic device 3 includes a printed circuit board (PCB) and a package structure, which is located on the PCB and electrically connected to the PCB.

[0168] The performance of the packaging structure has a significant impact on the entire communication system, especially for high-frequency (e.g., centimeter wave (3–30 GHz) and millimeter wave (30–300 GHz) bands) packaging structures, where the performance has an even greater impact on the entire communication system.

[0169] The performance of a packaging structure is closely related to its interconnection method. This application provides a packaging structure that adopts a novel interconnection method, which aims to reduce interconnection transmission loss, broaden the operating bandwidth, and improve the performance of the packaging structure.

[0170] To facilitate understanding of the packaging structure provided in the embodiments of this application, existing packaging structures will be introduced before introducing the packaging structure provided in the embodiments of this application.

[0171] For example, see Figure 2 , Figure 2 This is a schematic diagram of a prior art packaging structure. The packaging structure 10 includes a chip 11, an insulating layer 12, and wiring layers 13 located on both sides of the insulating layer 12. Through-holes are formed in the dielectric layer 12, and conductive structures 18 are provided within the through-holes for electrically connecting the wiring layers 13 on both sides of the insulating layer 12. In the wiring layer 13, the portion connected to the conductive structure 18 is a connecting pad 14.

[0172] The chip 11 embedded in an insulating layer 12 can be electrically connected to a wiring layer 13 on one side of the insulating layer 12 by means of metal wire 15 through wire bonding, and can be electrically connected to other chips 11 (e.g., chips 11 located on one side of the insulating layer 12 and electrically connected to the wiring layer 13 on one side of the insulating layer 12) through the wiring layer 13, and the input and output interfaces of the chip 11 can be brought out through conductive structures 18 electrically connected to the wiring layer 13 and other wiring layers 13.

[0173] Combination Figure 3 , Figure 3 This diagram shows the positional relationship between the connecting pad, the conductive structure, and the isolation structure. The connecting pad 14 is surrounded by an isolation structure 16, which isolates the connecting pad 14 to prevent short circuits and signal interference.

[0174] In this package structure 10, the input and output of chip signals are achieved through interconnection methods such as gold wire bonding and via interconnection.

[0175] However, in the gold wire bonding interconnection method, the interconnection length of the metal wire 15 is large. For example, the arch height H1 of the metal wire 15 is less than or equal to 100μm and greater than or equal to 50μm, and the arch length H2 of the metal wire 15 is greater than or equal to 100μm. In addition, the diameter of the metal wire 15 is small. This results in a large interconnection distribution parameter of the package structure 10 (generally manifested as a large inductance), which worsens the return loss and increases the interconnection loss. Furthermore, its operating frequency band is low (less than 50GHz).

[0176] In the via interconnection method, there will be a high-frequency coupling effect between the connecting pad 14 and the isolation structure 16, which will increase the high-frequency transmission loss, worsen the transmission matching and return loss, and lead to a decrease in high-frequency performance. Moreover, this interconnection method generally requires the pad of chip 11 to be larger in size (e.g., the size of the pad needs to be greater than 100μm×100μm). This makes the chip 11 selective and may also increase the area of ​​chip 11, resulting in a larger volume of package structure 10.

[0177] When gold wire bonding and vias are combined for interconnection, more complex RLC distribution parameters are generated, and even signal oscillations are introduced, which further deteriorates matching and transmission performance and limits package interconnect performance.

[0178] For example, see Figure 4 , Figure 4This is a schematic diagram of another packaging structure in the prior art. The packaging structure 10 includes: a chip 11, an insulating layer 12, and a redistribution layer (RDL) 19. An RDL 19 is provided between two insulating layers 12, and the chip 11 within the two insulating layers 12 is interconnected through conductive structures 18 in through-holes and the RDL 19.

[0179] In this package structure 10, signal interconnection can be achieved through rewiring and via interconnection.

[0180] As described above, in the via interconnection method, there is a high-frequency coupling effect between the connecting pad 14 and the isolation structure 16, leading to increased high-frequency transmission loss; worsening transmission matching and return loss, resulting in decreased high-frequency performance; and this interconnection method generally requires a larger pad size for the chip 11. Thus, even with selective chip 11, the area of ​​the chip 11 may increase, resulting in a larger package structure 10. Furthermore, the redistribution and via interconnection methods involve multiple layers of vias, which further exacerbates the aforementioned deterioration effects.

[0181] The above describes the interconnection methods in the packaging structure of the prior art. As can be seen from the above, the interconnection methods in the packaging structure of the prior art increase the transmission loss of the packaging structure, resulting in poor performance and large size of the packaging structure.

[0182] The packaging structure provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0183] See Figure 5 , Figure 5 This is a schematic diagram of a packaging structure provided in an embodiment of the present application. The packaging structure 10 includes a support structure 20, a first functional device 30, a first interconnection structure 40, and a first wiring structure 50.

[0184] The support structure 20 includes a first surface 21 and a second surface 22 disposed opposite to each other. The support structure 20 has a cutout 23 that can penetrate through the first surface 21 and the second surface 22. The support structure 20 is the core layer in the encapsulation structure 10 and provides support.

[0185] The first functional device 30 is disposed in the hollow portion 23, and there may be a gap between the first functional device 30 and the support structure 20. The first functional device 30 may include an upper surface 31 and a lower surface 32 opposite to each other. A first pad 33 may be provided on the upper surface 31 of the first functional device 30, and the first pad 33 is used to lead out the connection point of the first functional device 30. The number of first pads 33 may be the same as the number of connection points of the first functional device 30, that is, each connection point will correspond to one first pad 33, that is, a first pad 33 can be provided on each connection point. The signal of the first functional device 30 can be input and / or output through the first pad 33. The upper surface 31 of the first functional device 30 may be flush with the first surface 21 of the support structure 20. In some embodiments, the lower surface 32 of the first functional device 30 may also be flush with the second surface 22 of the support structure 20, that is, the thickness of the first functional device 30 is the same as the thickness of the support structure 20. Of course, the upper surface 31 of the first functional device 30 may not be flush with the first surface 21 of the support structure 20. For example, the upper surface 31 of the first functional device 30 may extend beyond the first surface 21 of the support structure 20; or, the first surface 21 of the support structure 20 may extend beyond the upper surface 31 of the first functional device 30. The lower surface 32 of the first functional device 30 may also not be flush with the second surface 22 of the support structure 20. For example, the lower surface 32 of the first functional device 30 may extend beyond the second surface 22 of the support structure 20; or, the second surface 22 of the support structure 20 may extend beyond the lower surface 32 of the first functional device 30.

[0186] The pads in this application may include structures such as solder pads that allow connection points of functional devices to be brought out. Furthermore, the upper surface of a device mentioned in this application may be the upper surface of the device along the vertical direction, and the lower surface of a device mentioned may be the lower surface of the device along the vertical direction.

[0187] The first interconnect structure 40 includes a first dielectric support layer 41 and a first interconnect layer 42. The first dielectric support layer 41 is located in the cutout portion 23 and in the gap between the support structure 20 and the first functional device 30. The first dielectric support layer 41 at least partially surrounds the first functional device 30. The first interconnect layer 42 may be disposed on the first dielectric support layer 41. When the first interconnect layer 42 is disposed on the first dielectric support layer 41, it may also be disposed on the upper surface 31 of the first functional device 30 and extend to the position of the first pad 33, directly overlapping with the first pad 33 to achieve electrical connection with the first pad 33, thereby achieving electrical connection with the first functional device 30.

[0188] The first wiring structure 50 can be disposed on the first surface 21 and electrically connected to the first interconnect layer 42. In this way, the first pad 33 can be electrically connected to the first wiring structure 50 through the first interconnect layer 42, and the signal of the first functional device 30 can be input and / or output through the first interconnect layer 42 and the first wiring structure 50 electrically connected to the first pad 33.

[0189] In the packaging structure 10 provided in this application embodiment, the first pad 33 and the first wiring structure 50 can be smoothly interconnected through the first interconnect layer 42 disposed on the first dielectric support layer 41, without vias or metal wires. This effectively reduces interconnect parasitic inductance, lowers coupling effects, and thus reduces interconnect losses, expands the operating frequency band, and effectively solves the problems of high interconnect losses, narrow bandwidth, and large parasitic parameters in existing packaging structures. Furthermore, the linewidth of the first interconnect layer 42 can be flexibly changed, and the network pattern can be flexibly matched between structures that require interconnection in very short distances (wherein the pattern accuracy can be better than 0.5μm). For example, the first interconnect layer 42 can be set to match the impedance value of the first functional device 30 to reduce return loss and interconnect loss. Furthermore, since the first interconnect layer 42 can be directly connected to the first pad 33 to achieve interconnection, the first pad 33 does not need to be large. This makes the selection of the first functional device 30 more flexible; and the volume of the first functional device 30 can be smaller, which is beneficial to the miniaturization of the packaging structure 10.

[0190] The material of the support structure 20 is not limited in this application embodiment. For example, the material of the support structure 20 may include silicon dioxide, etc.

[0191] This application does not limit the first functional device 30. For example, the first functional device 30 can be a bare die, where a die is a chip before it is packaged. Each die is an unpackaged chip with independent function, and it can consist of one or more circuits. Of course, the first functional device 30 can also be a packaging assembly that packages a single die; or a packaging assembly that packages multiple dies. The first functional device 30 may not be a chip, but rather a device with circuit functions (e.g., a module that implements chip functions without relying on traditional semiconductor integrated circuit structures, but through microelectromechanical systems, photonic integration, carbon-based materials, or other equivalent technologies). This application does not limit this. For example, the first functional device 30 can be a device with power amplifier (PA) functions, transceiver (TR) functions, and mixer functions. It can be a die with PA, TR, and mixer functions, a packaging assembly that packages a die with PA, TR, and mixer functions, or a device with circuit functions such as PA, TR, and mixer (this device is not a chip).

[0192] The number of first pads 33 is not limited in this application embodiment, as long as they can achieve the corresponding functions of the first functional device 30.

[0193] The number of first pads 33 can be one or more. When there are multiple first pads 33, all of the first pads 33 can be electrically connected to the first interconnect layer 42, and then electrically connected to the first wiring structure 50 through the first interconnect layer 42; or some of the first pads 33 can be electrically connected to the first interconnect layer 42 (the remaining first pads 33 are not electrically connected to the first interconnect layer 42, but are directly electrically connected to the first wiring structure 50 through existing gold wire bonding or vias, etc.).

[0194] For example, when there are multiple first pads 33, and the first functional device 30 is a device with radio frequency (RF) functionality (such as a radio frequency integrated circuit (RF IC)), the multiple first pads 33 may include at least one first pad 33 for RF signal input, at least one first pad 33 for RF signal output, at least one first pad 33 for power supply signal input, and at least one first pad 33 for control signal input. All of the multiple first pads 33 may be electrically connected to the first interconnect layer 42, and then electrically connected to the first wiring structure 50 through the first interconnect layer 42. Alternatively, at least one first pad 33 for RF signal input and at least one first pad 33 for RF signal output may be electrically connected to the first interconnect layer 42, and then electrically connected to the first wiring structure 50 through the first interconnect layer 42; the at least one first pad 33 for power supply signal input and at least one first pad 33 for control signal input may not be electrically connected to the first interconnect layer 42, but may be electrically connected to the first wiring structure 50 through existing metal wires or vias.

[0195] When multiple first pads 33 are electrically connected to the first interconnect layer 42, the multiple first pads 33 can be arranged sequentially along the circumference of the upper surface 31, which facilitates the electrical connection between the first interconnect layer 42 and each first pad 33.

[0196] Unless otherwise specified, the embodiments in this application are described with the example of two first pads 33 provided on the upper surface 31 of the first functional device 30, and both first pads 33 being electrically connected to the first interconnect layer 42.

[0197] In some embodiments, see continue to see Figure 5 The lower surface 32 of the first functional device 30 is provided with a ground layer (also called a GND plane) 34. For example, the second surface 22 of the support structure 20 is provided with a ground layer carrier plate 340. The ground layer carrier plate 340 includes one, two, or more ground layers 34 disposed on the second surface 22 of the support structure 20, wherein... Figure 5 The explanation is based on the example of a three-layer grounding layer 34.

[0198] The material of the first dielectric support layer 41 is not limited in this application embodiment. For example, the material of the first dielectric support layer 41 may include photoresist or epoxy resin, which can provide dielectric constant and support for the first interconnect layer 42.

[0199] The material of the first interconnect layer 42 is not limited in this application embodiment. For example, the material of the first interconnect layer 42 may include conductive materials such as nano-silver or nano-copper.

[0200] In some embodiments, the first interconnect layer 42 may also be referred to as a microstrip line, and the shape of the microstrip line includes, but is not limited to, rectangular stubs or stepped stubs.

[0201] In some embodiments, see continue to see Figure 5 A ground connection layer 43 is provided on the surface of the first dielectric support layer 41 facing away from the first interconnect layer 42. The projection of the first interconnect layer 42 onto the plane of the first surface 21 overlaps with the projection of the ground connection layer 43 onto the plane of the first surface 21. This ground connection layer 43 can be electrically connected to the ground layer 34 of the first functional device 30. The ground layer 34 can provide a reference ground signal for the ground connection layer 43, thus simplifying the packaging process and reducing the package size.

[0202] The specific location of the first dielectric support layer 41 in the cutout portion 23 is not limited in this embodiment, as long as it can support the first interconnect layer 42 so that the first interconnect layer 42 can be electrically connected to the first pad 33 and the first wiring structure 50 respectively.

[0203] In some possible implementations, combining Figure 6a , Figure 6a This is a top view schematic diagram of a first dielectric support layer, support structure, and first functional device provided in an embodiment of this application. The first dielectric support layer 41 can be annular and is disposed around the first functional device 30. In this way, when there are multiple first pads 33, it is convenient to set the first interconnect layer 42 on the first dielectric support layer 41, thereby facilitating the electrical connection between the first interconnect layer 42 and each first pad 33.

[0204] Among other possible implementation methods, combining Figure 6b , Figure 6b This is a top view of another first dielectric support layer, support structure and first functional device provided in the embodiments of this application. The first dielectric support layer 41 may partially surround the first functional device 30. For example, the first dielectric support layer 41 may be set according to the position of the first pad 33.

[0205] For example, the first functional device 30 includes a first pad 33, and the first dielectric support layer 41 surrounds only the area of ​​the first functional device 30 where the first pad 33 is provided. In this way, the first interconnect layer 42 located on the first dielectric support layer 41 can also realize the electrical connection between the first pad 33 and the first wiring structure 50.

[0206] For example, the first functional device 30 includes a plurality of first pads 33, and the first dielectric support layer 41 includes a plurality of dielectric support portions 411. For instance, the first functional device 30 includes three first pads 33, and the first dielectric support layer 41 includes three dielectric support portions 411. The plurality of dielectric support portions 411 are spaced apart (e.g., ...). Figure 6b (as shown), or, two partially adjacent dielectric support portions 411 are adjacent to each other, and two partially adjacent dielectric support portions 411 are spaced apart (e.g. Figure 6c (As shown). A dielectric support portion 411 is provided next to a first pad 33. Correspondingly, the first interconnect layer 42 includes multiple interconnect lines that are not connected to each other. The multiple interconnect lines are respectively provided on multiple dielectric support portions 411, so that multiple first pads 33 can be electrically connected to the first wiring structure 50 through multiple interconnect lines.

[0207] It should be noted that, Figure 5 This explanation uses the example of the first wiring structure 50 being disposed on the first surface 21 of the support structure 20. Of course, the first wiring structure 50 can also be disposed on the second surface 22. See [link / reference] Figure 7 , Figure 7 This is a schematic diagram of another packaging structure provided in an embodiment of this application. When the first wiring structure 50 is disposed on the second surface 22, the first interconnect layer 42 can pass through the cutout portion 23 and be electrically connected to the first wiring structure 50. When the first wiring structure 50 is disposed on the first surface 21, the first interconnect layer 42 does not need to pass through the cutout portion 23, shortening the length of the first interconnect layer 42 and reducing the signal loss caused by the longer length of the first interconnect layer 42. The following description uses the example of the first wiring structure 50 being disposed on the first surface 21.

[0208] The embodiments of this application do not limit the structure of the first wiring structure 50, and the first wiring structure 50 can be any structure with lines.

[0209] See also some possible implementations. Figure 8 , Figure 8 This is a schematic diagram of another packaging structure provided in an embodiment of this application. The first wiring structure 50 may only include a first wiring layer 51 disposed on the first surface 21. The first interconnect layer 42 may be electrically connected to the first wiring layer 51, and the first pad 33 is electrically connected to the first wiring layer 51 through the first interconnect layer 42.

[0210] In this case, a first connection terminal 53 can be provided on the first wiring layer 51, through which an external circuit board can be electrically connected. For example, the first connection terminal 53 can be solder, solder ball, solderable plating, or solderable connecting post, etc.

[0211] For further possible implementations, please refer to [link / reference]. Figure 5 The first wiring structure 50 may include a multi-layer first wiring layer 51 disposed on the first surface 21 and a first insulating layer 52 located between two adjacent first wiring layers 51, and the two adjacent first wiring layers 51 are electrically connected.

[0212] For ease of explanation, this application embodiment uses a first wiring structure 50 comprising four first wiring layers 51 and three first insulating layers 52 as an example. The four first wiring layers 51 are a first first wiring layer 51, a second first wiring layer 51, a third first wiring layer 51, and a fourth first wiring layer 51. The first first wiring layer 51 is the first wiring layer 51 disposed on the first surface 21 along a direction perpendicular to the first surface 21. The second first wiring layer 51 is the first wiring layer 51 closest to the first first wiring layer 51. The fourth first wiring layer 51 (i.e., the last first wiring layer 51) is the first wiring layer 51 farthest from the first surface 21 among the multiple first wiring layers 51. The third first wiring layer 51 is located between the second and fourth first wiring layers 51. The first layer first wiring layer 51 and the second layer first wiring layer 51 are electrically connected, the second layer first wiring layer 51 and the third layer first wiring layer 51 are electrically connected, and the third layer first wiring layer 51 and the fourth layer first wiring layer 51 are electrically connected.

[0213] The material of the first insulating layer 52 includes, but is not limited to, one or more of molding compound, Ajinomoto build-up film (ABF), and ceramic build-up film (CBF). Using ABF as the material of the first insulating layer 52 results in a thin film layer, low dielectric loss, and high thermal stability and reliability.

[0214] The material of the first wiring layer 51 includes, but is not limited to, one or more of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), and titanium (Ti). Using copper as the material of the first wiring layer 51 results in low cost, high reliability, and low contact resistance.

[0215] The line width of the first wiring layer 51 can be determined according to the signal transmitted by the package structure 10. For example, the line width of the first wiring layer 51 is greater than 0 μm and less than or equal to 100 μm, such as 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm, etc.

[0216] The first wiring layer 51 can be an RDL. When the first wiring layer 51 is an RDL, the first wiring layer 51 can include one metal layer or multiple metal layers.

[0217] When the first wiring structure 50 includes multiple first wiring layers 51, the first interconnect layer 42 can be electrically connected to any one of the first wiring layers 51; of course, the first interconnect layer 42 can also be electrically connected to all the first wiring layers 51, or to a portion of the first wiring layers 51 (such as the first interconnect layer 52 and two of the multiple first wiring layers 51). The signal of the first functional device 30 can be input and / or output through the first interconnect layer 42 and the first wiring layers 51 electrically connected to the first interconnect layer 42.

[0218] In one example, the first interconnect layer 42 is electrically connected to the first wiring layer 51, and the two first pads 33 are electrically connected to the first wiring layer 51 via the first interconnect layer 42. See also Figure 9 , Figure 9 This is a schematic diagram of another packaging structure provided in an embodiment of this application. Since the first surface 21 of the support structure 20 is flush with the upper surface 31 of the first functional device 30, the first wiring layer 51 on the first surface 21 and the first pad 33 on the upper surface 31 of the first functional device 30 have the same height. In this case, the surface of the first dielectric support layer 41 can be flush with the first surface 21 of the support structure 20 and the upper surface 31 of the first functional device 30, respectively. In this way, when the first interconnect layer 42 is provided on the surface of the first dielectric support layer 41, the first interconnect layer 42 can overlap with the first wiring layer 51 and the first pad 33, respectively, so that the first interconnect layer 42 can be electrically connected to the first wiring layer 51 and the first pad 33, respectively, and the first pad 33 can be electrically connected to the first wiring layer 51 through the first interconnect layer 42. The signal of the first functional device 30 can be input and / or output through the first interconnect layer 42, the first wiring layer 51, the second wiring layer 51, the third wiring layer 51 and the fourth wiring layer 51 electrically connected to the first pad 33.

[0219] In this example, when the first wiring structure 50 needs to be electrically connected to the first pad 33 through a first wiring layer 51 (this first wiring layer 51 is the first layer of first wiring layer 51), and the first layer of first wiring layer 51 is at the same height as the first pad 33, a smooth and compact connection without metal wires and without height difference can be achieved through the first interconnect layer 42. Compared with existing interconnection methods (e.g., Figure 2 Interconnection method of metal wire and via combination or Figure 4 The interconnection method provided in this application (using a combination of vias and RDL) can effectively reduce the parasitic inductance of the interconnection and expand the operating frequency band. At the same time, since the first interconnection layer 42 can be directly connected to the first pad 33 to achieve interconnection, the first pad 33 does not need to be large. This makes the selection of the first functional device 30 more flexible and can reduce the size of the interconnection structure, which is beneficial to the miniaturization of the package structure 10.

[0220] In another example, the first interconnect layer 42 is electrically connected to the second first wiring layer 51, and the two first pads 33 are electrically connected to the second first wiring layer 51 through the first interconnect layer 42. See also Figure 10 , Figure 10 This is a schematic diagram of another packaging structure provided in this application embodiment. Since the first surface 21 of the support structure 20 is flush with the upper surface 31 of the first functional device 30, the first layer of the first wiring layer 51 on the first surface 21 and the first pad 33 on the upper surface 31 of the first functional device 30 have the same height. The height of the second layer of the first wiring layer 51 is higher than the height of the first pad 33 on the upper surface 31 of the first functional device 30. In this case, along the direction perpendicular to the first surface 21, the second layer of the first wiring layer 51 and the first pad 33 can be staggered, that is, the projection of the second layer of the first wiring layer 51 onto the plane of the first surface 21 does not overlap with the projection of the first pad 33 onto the plane of the first surface 21. The first dielectric support layer 41 can extend beyond the first surface 21 of the support structure 20, and the portion of the first dielectric support layer 41 extending beyond the first surface 21 of the support structure 20 (e.g., Figure 5 The height of the area AA (framed by the curved frame) gradually increases in the direction perpendicular to the first surface 21. Correspondingly, the surface of the first dielectric support layer 41 where the first interconnect layer 42 is located (also called the first support surface) gradually increases. That is, the distance between the first support surface of the first dielectric support layer 41 where the first interconnect layer 42 is located and the plane where the first surface 21 is located gradually increases. If it increases to the same height as the second layer first wiring layer 51, the second layer first wiring layer 51 can directly overlap with the first interconnect layer 42 on this surface. In this way, the first interconnect layer 42 can directly overlap with the lower first pad 33 and the higher second layer first wiring layer 51, so that the first interconnect layer 42 can be electrically connected to the second layer first wiring layer 51 and the first pad 33 respectively, and the first pad 33 can be electrically connected to the second layer first wiring layer 51 through the first interconnect layer 42. The signal of the first functional device 30 can be input and / or output through the first interconnect layer 42, the second first wiring layer 51, the third first wiring layer 51 and the fourth first wiring layer 51 electrically connected to the first pad 33.

[0221] In this example, when the first wiring structure 50 needs to be electrically connected to the first pad 33 through a first wiring layer 51 (which is a second first wiring layer 51), and the second first wiring layer 51 is higher than the first pad 33, a smooth and compact connection with a height difference and no metal wires can be achieved through the first interconnect layer 42. Compared with existing interconnect methods (e.g., Figure 2The interconnection method provided in this application (using a combination of metal wires and vias) can effectively reduce transmission loss caused by coupling effects and extend the operating frequency band. Simultaneously, since the first interconnect layer 42 can be directly connected to the first pad 33 for interconnection, the first pad 33 does not need to be large. This allows for greater flexibility in selecting the first functional device 30 and reduces the size of the interconnection structure, which is beneficial for miniaturizing the package structure 10. Furthermore,

[0222] In another example, the first interconnect layer 42 is electrically connected to the first wiring layer 51 and the second wiring layer 51, respectively. One first pad 33 is electrically connected to the first wiring layer 51 via the first interconnect layer 42, and another first pad 33 is electrically connected to the second wiring layer 51 via the first interconnect layer 42. See also... Figure 5Since the first surface 21 of the support structure 20 is flush with the upper surface 31 of the first functional device 30, the first wiring layer 51 on the first surface 21 and the first pad 33 on the upper surface 31 of the first functional device 30 have the same height, while the height of the second wiring layer 51 is higher than the height of the first pad 33 on the upper surface 31 of the first functional device 30. In this case, along the direction perpendicular to the first surface 21, the second wiring layer 51 and the first pad 33 can be staggered, that is, the projection of the second wiring layer 51 onto the plane of the first surface 21 does not overlap with the projection of the first pad 33 onto the plane of the first surface 21. Furthermore, the first support surface of the first dielectric support layer 41, where the first interconnect layer 42 is located, is divided into at least a first region 412 and a second region 413. The first support surface in the first region 412 can be flush with the first surface 21 of the support structure 20 and the upper surface 31 of the first functional device 30, respectively. The first support surface in the second region 413 gradually rises, meaning the distance between the first support surface in the second region 413 and the plane containing the first surface 21 gradually increases, such as rising to the same height as the second first wiring layer 51. Thus, when the first interconnect layer 42 is located on the first support surface, the first interconnect layer 42 can directly overlap with the two first pads 33, achieving electrical connection between the first interconnect layer 42 and the first pads 33. When setting the first wiring layer 51, the first wiring layer 51 can be directly connected to the first interconnect layer 42 located in the first region 412, realizing the electrical connection between the first interconnect layer 42 and the first wiring layer 51; when setting the second wiring layer 51, the second wiring layer 51 can be directly connected to the first interconnect layer 42 located in the second region 413, realizing the electrical connection between the first interconnect layer 42 and the second wiring layer 51. In this way, one of the first pads 33 can be electrically connected to the first wiring layer 51 through the first interconnect layer 42, and the other first pad 33 can be electrically connected to the second wiring layer 51 through the first interconnect layer 42. The signal of the first functional device 30 can be input or output through the first interconnect layer 42, the first wiring layer 51, the second wiring layer 51, the third wiring layer 51 and the fourth wiring layer 51 electrically connected to one of the first pads 33, and can also be output or input through the first interconnect layer 42, the second wiring layer 51, the third wiring layer 51 and the fourth wiring layer 51 electrically connected to the other first pad 33.

[0223] In this example, when the first wiring structure 50 needs to be electrically connected to two first pads 33 via two first wiring layers 51 (the two first wiring layers 51 being the first layer 51 and the second layer 51, respectively), and the first layer 51 is at the same height as the first pad 33 while the second layer 51 is higher than the first pad 33, a smooth and compact connection without metal wires and without height difference can be achieved through the first interconnect layer 42. Furthermore, a smooth and compact connection with height difference but without metal wires can be achieved through the first interconnect layer 42. Compared to existing interconnection methods (e.g., ...), Figure 2 Interconnection method of metal wire and via combination or Figure 4 The interconnection method provided in this application (using a combination of vias and RDL) can effectively reduce the parasitic inductance of the interconnection and the transmission loss caused by coupling effect, thus expanding the operating frequency band. At the same time, since the first interconnection layer 42 can be directly connected to the first pad 33 to achieve interconnection, the first pad 33 does not need to be large. This makes the selection of the first functional device 30 more flexible and can reduce the size of the interconnection structure, which is beneficial to the miniaturization of the package structure 10.

[0224] In the above example, when the height of the first support surface of the first dielectric support layer 41 where the first interconnect layer 42 is provided gradually increases, the first support surface can be an inclined surface (the inclined surface has a preset angle with the plane where the first surface 21 is located), a curved surface (the line connecting the two ends of the curved surface has a preset angle with the plane where the first surface 21 is located), or a stepped surface, etc. The shape of the first support surface of the first dielectric support layer 41 where the first interconnect layer 42 is provided is not limited in this application embodiment.

[0225] It should be noted that the above is merely an illustrative example illustrating the specific configuration of each structure when the first interconnect layer 42 is electrically connected to the first wiring layer 51, the first interconnect layer 42 is electrically connected to the second wiring layer 51, and the first interconnect layer 42 is electrically connected to the first wiring layer 51 and the second wiring layer 51 respectively. However, this does not constitute a limitation on this application.

[0226] When the first wiring structure 50 includes multiple first wiring layers 51, the present application embodiments do not limit the interconnection method between the above-mentioned two adjacent first wiring layers 51.

[0227] See also the following for some possible implementations. Figure 5 Electrical connections between two adjacent first wiring layers 51 can be achieved through via interconnection.

[0228] Among other possible implementations, see [link to relevant documentation]. Figure 11a , Figure 11aThis is a schematic diagram of another packaging structure provided in an embodiment of this application. The packaging structure 10 further includes a second interconnect structure 60, which includes a second dielectric support layer 61 and a second interconnect layer 62. At least two adjacent first wiring layers 51 are staggered along a direction perpendicular to the first surface 21, wherein the staggered arrangement of adjacent first wiring layers 51 means that the projections of adjacent first wiring layers 51 onto the plane of the first surface 21 do not overlap. A second dielectric support layer 61 is embedded within a first insulating layer 52 between the staggered adjacent first wiring layers 51. The second interconnect layer 62 is disposed on the second dielectric support layer 61 and electrically connects the staggered adjacent first wiring layers 51.

[0229] For example, the height of the second dielectric support layer 61 gradually increases in the direction perpendicular to the first surface 21. Correspondingly, the surface of the second dielectric support layer 61 where the second interconnect layer 62 is located (also referred to as the second support surface) gradually increases, that is, the distance between the second support surface of the second dielectric support layer 61 where the second interconnect layer 62 is located and the plane where the first surface 21 is located gradually increases. Specifically, the height increases from the height of one of the first wiring layers 51 to the height of another first wiring layer 51 adjacent to that first wiring layer 51. For example, the second first wiring layer 51 and the third first wiring layer 51 are staggered, and the second dielectric support layer 61 is embedded in the first insulating layer 52 between the second first wiring layer 51 and the third first wiring layer 51. The second support surface of the second dielectric support layer 61 increases from the height of the second first wiring layer 51 to the height of the third first wiring layer 51. Thus, when the second interconnect layer 62 is disposed on the second support surface of the second dielectric support layer 61, the second interconnect layer 62 can directly overlap with the lower second layer first wiring layer 51 and the higher third layer first wiring layer 51, so that the second layer first wiring layer 51 can be electrically connected to the third layer first wiring layer 51 through the second interconnect layer 62.

[0230] Figure 11a The following description is based on the example of a first wiring structure 50 being electrically connected to two first pads 33 via a first wiring layer 51 and a second wiring layer 51, wherein the first wiring layer 51 is at the same height as the first pad 33, the second wiring layer 51 is higher than the first pad 33, and all adjacent first wiring layers 51 are staggered.

[0231] In this case, the signal of the first functional device 30 can be output or input through the first interconnect layer 42, the first wiring layer 51, the second interconnect layer 62 on the second dielectric support layer 61 within the first insulating layer 52 (i.e., the first insulating layer between the first wiring layer 51 and the second wiring layer 51), the second wiring layer 51, the second interconnect layer 62 on the second dielectric support layer 61 within the second insulating layer 52 (i.e., the first insulating layer between the second wiring layer 51 and the third wiring layer 51), the third wiring layer 51, the second interconnect layer 62 on the second dielectric support layer 61 within the third insulating layer 52 (i.e., the first insulating layer between the third wiring layer 51 and the fourth wiring layer 51), and the fourth wiring layer 51. Furthermore, the signal of the first functional device 30 can be input or output through the first interconnect layer 42, the second first wiring layer 51, the second dielectric support layer 61 within the second first insulating layer (i.e., the first insulating layer between the second and third first wiring layers 51) 52, the third first wiring layer 51, the second interconnect layer 62 within the second dielectric support layer 61 within the third first insulating layer (i.e., the first insulating layer between the third and fourth first wiring layers 51), and the fourth first wiring layer 51, which are electrically connected to another first pad 33.

[0232] By incorporating a second interconnect structure 60 within the first wiring structure 50, not only can the first functional device 30 be interconnected with the first wiring structure 50 without vias or metal wires, but the first wiring layers 51 of the first wiring structure 50 can also be interconnected without vias or metal wires. This effectively reduces interconnect parasitic inductance, lowers coupling effects, and consequently further reduces interconnect losses.

[0233] The material of the second dielectric support layer 61 is not limited in this embodiment. For example, the material of the second dielectric support layer 61 may include photoresist or epoxy resin, which can provide dielectric constant and support for the second interconnect layer 62. It should be noted that in actual installation, the materials of the first dielectric support layer 41 and the second dielectric support layer 61 may be the same or different; this embodiment does not limit this.

[0234] This application does not limit the material of the second interconnect layer 62. For example, the material of the second interconnect layer 62 may include conductive materials such as nano-silver or nano-copper. It should be noted that in actual implementation, the materials of the first interconnect layer 42 and the second interconnect layer 62 may be the same or different; this application does not limit this.

[0235] In the above example, when the height of the second support surface of the second dielectric support layer 61 where the second interconnect layer 62 is provided gradually increases, the second support surface can be an inclined surface (the inclined surface has a preset angle with the plane where the first surface 21 is located), a curved surface (the line connecting the two ends of the curved surface has a preset angle with the plane where the first surface 21 is located), or a stepped surface, etc. The shape of the second support surface of the second dielectric support layer 61 where the second interconnect layer 62 is provided is not limited in this embodiment.

[0236] When a second dielectric support layer 61 is provided within each of the multiple first insulating layers 52, that is, the number of second dielectric support layers 61 is also multiple. At least a portion of the multiple second dielectric support layers 61 can be integrally formed, that is, all of the multiple second dielectric support layers 61 are integrally formed; or, a portion of the multiple second dielectric support layers 61 can be integrally formed. For example, see [link to example]. Figure 11b , Figure 11b This is a schematic diagram of another packaging structure provided in an embodiment of this application. A second dielectric support layer 61 located within a first insulating layer 52 between the second and third first wiring layers 51, and another second dielectric support layer 61 located within a first insulating layer 52 between the third and fourth first wiring layers 51, are integrally formed. When at least a portion of the plurality of second dielectric support layers 61 are integrally formed, the process steps can be simplified.

[0237] Furthermore, the first dielectric support layer 41 may also be integrally formed with at least a portion of the plurality of second dielectric support layers 61, that is, the first dielectric support layer 41 may be integrally formed with all of the plurality of second dielectric support layers 61; or, the first dielectric support layer 41 may be integrally formed with a portion of the plurality of second dielectric support layers 61. For example, see [link to example]. Figure 11c , Figure 11c This is a schematic diagram of another packaging structure provided in an embodiment of this application. The first dielectric support layer 41 is integrally formed with the second dielectric support layer 61 located within the first insulating layer 52 between the first and second wiring layers 51, the second dielectric support layer 61 located within the first insulating layer 52 between the second and third wiring layers 51, and the second dielectric support layer 61 located within the first insulating layer 52 between the third and fourth wiring layers 51. This further simplifies the manufacturing process.

[0238] The following descriptions are based on the example of the first dielectric support layer 41 and the plurality of second dielectric support layers 61 being configured individually.

[0239] In some embodiments, see continue to see Figure 11aThe packaging structure 10 also includes at least one second functional device 70, which is located on the side of the first wiring structure 50 opposite to the support structure 20. The second functional device 70 is electrically connected to the first wiring structure 50. Specifically, the second functional device 70 may be provided with a second pad 71, which is used to lead out the connection point of the second functional device 70. The second pad 71 of the second functional device 70 may be electrically connected to the fourth (last) first wiring layer 51 of the first wiring structure 50.

[0240] This enables high-density integration through three-dimensional stacking, allowing the package structure 10 to achieve more complex functions. Furthermore, when the first wiring layers 51 of the first wiring structure 50 are electrically connected via the second interconnect layer 62 on the second dielectric support layer 61, the first functional device 30 and the second functional device 70 can be interconnected through the first interconnect layer 41, the first wiring layer 51, and the second interconnect layer 62. Compared to traditional interconnection methods for multifunctional devices (vias and / or metal wire interconnection), this effectively reduces losses between multiple functional device interconnections, expands the operating frequency band, and reduces the overall package size, achieving flexible, high-density, and high-performance integrated packaging of multi-layer functional devices.

[0241] The embodiments of this application do not limit the second functional device 70. For example, the second functional device 70 can be a bare die, where a die is a chip before it is packaged. Each die is an unpackaged chip with independent function, and it can consist of one or more circuits. Of course, the first functional device 30 can also be a packaging assembly that packages a single die; or, a packaging assembly that packages multiple dies. The second functional device 70 may also not be a chip, but rather some device with circuit functions (e.g., a module that achieves chip functions without relying on traditional semiconductor integrated circuit structures, but through microelectromechanical systems, photonic integration, carbon-based materials, or other equivalent technologies), which is not limited herein.

[0242] In some embodiments, to achieve double-sided signal output of the first functional device 30. See also Figure 12 , Figure 12This is a schematic diagram of another packaging structure provided in an embodiment of this application. The packaging structure 10 further includes a second wiring structure 80, which is disposed on the second surface 22. That is, the first wiring structure 50 and the second wiring structure 80 are located on opposite sides of the support structure 20. The first interconnect layer 42 passes through the cutout portion 23 and is electrically connected to the second wiring structure 80. One of the first pads 33 can be electrically connected to the second wiring structure 80 through the first interconnect layer 42. The signal of the first functional device 30 can be input or output through the first interconnect layer 42 and the second wiring structure 80 electrically connected to the first pad 33. The other first pad 33 can be electrically connected to the first wiring structure 50 through the first interconnect layer 42. The signal of the first functional device 30 can be output or input through the first interconnect layer 42 and the first wiring structure 500 electrically connected to the first pad 33. In this way, the signal of the packaging structure 10 can be brought out from both sides, which is beneficial for better mutual avoidance between lines and avoids mutual interference between signals due to insufficient wiring space, thus affecting the performance of the packaging structure 10.

[0243] The embodiments of this application do not limit the structure of the second wiring structure 80, and the second wiring structure 80 can be any structure with lines.

[0244] See also the following for some possible implementations. Figure 12 The second wiring structure 80 may consist of only one second wiring layer 81 disposed on the second surface 22. Along a direction perpendicular to the second surface 22, the second wiring layer 81 is offset from the first pad 33 of the first functional device 30, meaning the projection of the second wiring layer 81 onto the plane of the second surface 22 does not overlap with the projection of the first pad 33 onto the plane of the second surface 22. A portion of the first support surface of the first dielectric support layer 41, where the first interconnect layer 42 is located, is sloped. Thus, when the first interconnect layer 42 is disposed on the first support surface, it can directly overlap with the first pad 33; similarly, when the second wiring layer 81 is disposed on the second surface 22, it can also directly overlap with the first interconnect layer 42. The first interconnect layer 42 can be electrically connected to both the first pad 33 and the second wiring layer 81, and the first pad 33 is electrically connected to the second wiring layer 81 through the first interconnect layer 42.

[0245] In this case, a second connection terminal 83 can be provided on the second wiring layer 81, through which an external circuit board can be electrically connected. For example, the second connection terminal 83 can be solder, solder ball, solderable plating, or solderable connecting post, etc.

[0246] Among other possible implementations, see [link to relevant documentation]. Figure 13a , Figure 13aThis is a schematic diagram of another packaging structure provided in an embodiment of the present application. The second wiring structure 80 may include a multilayer second wiring layer 81 disposed on the second surface 22 and a second insulating layer 82 located between two adjacent second wiring layers 81, and the two adjacent second wiring layers 81 are electrically connected.

[0247] For ease of explanation, this application embodiment uses a second wiring structure 80 comprising four second wiring layers 81 and three second insulating layers 82 as an example. The four second wiring layers 81 are a first second wiring layer 81, a second second wiring layer 81, a third second wiring layer 81, and a fourth second wiring layer 81. The first second wiring layer 81 is a second wiring layer 81 disposed on the second surface 22. Along the direction perpendicular to the second surface 22, the second second wiring layer 81 is the second wiring layer 81 closest to the first second wiring layer 81. The fourth second wiring layer 81 (i.e., the last second wiring layer 81) is the second wiring layer 81 farthest from the second surface 22 among the multiple second wiring layers 81. The third second wiring layer 81 is located between the second second wiring layer 81 and the fourth second wiring layer 81. The first layer second wiring layer 81 and the second layer second wiring layer 81 are electrically connected, the second layer second wiring layer 81 and the third layer second wiring layer 81 are electrically connected, and the third layer second wiring layer 81 and the fourth layer second wiring layer 81 are electrically connected.

[0248] In this configuration, along the direction perpendicular to the second surface 22, the first second wiring layer 81 is offset from the first pad 33 of the first functional device 30, meaning the projection of the first second wiring layer 81 onto the plane of the second surface 22 does not overlap with the projection of the first pad 33 onto the plane of the second surface 22. A portion of the first support surface of the first dielectric support layer 41 is inclined, so that when the first interconnect layer 42 is disposed on the first support surface, the first interconnect layer 42 can directly overlap with the first pad 33, and when the second wiring layer 81 is disposed on the second surface 22, the second wiring layer 81 can also directly overlap with the first interconnect layer 42. The first interconnect layer 42 can be electrically connected to the first pad 33 and the second wiring layer 81 respectively, and the first pad 33 is electrically connected to the second wiring layer 81 through the first interconnect layer 42. The signal of the first functional device 30 can be input or output through the first interconnect layer 42, the first second wiring layer 81, the second second wiring layer 81, the third second wiring layer 81 and the fourth second wiring layer 81 electrically connected to one of the first pads 33, and can be output or input through the first interconnect layer 42, the second first wiring layer 51, the third first wiring layer 51 and the fourth first wiring layer 51 electrically connected to the other first pad 33.

[0249] When the second wiring structure 80 includes multiple second wiring layers 81, the ground layer 34 on the back of the first functional device 30 can be set on the same layer as the first second wiring layer 81.

[0250] The material of the second insulating layer 82 includes, but is not limited to, one or more of molding compounds, Ajinomoto build-up film (ABF), and ceramic build-up film (CBF). Using ABF as the material for the second insulating layer 82 results in a thin film layer, low dielectric loss, and high thermal stability and reliability.

[0251] The material of the second wiring layer 81 includes, but is not limited to, one or more of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), and titanium (Ti). Using copper as the material of the second wiring layer 81 results in low cost, high reliability, and low contact resistance.

[0252] The line width of the second wiring layer 81 can be determined according to the signal transmitted by the package structure 10. For example, the line width of the second wiring layer 81 is greater than 0 μm and less than or equal to 100 μm. For example, the line width of the first wiring layer 51 is 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm, etc.

[0253] The second wiring layer 81 can be an RDL. When the second wiring layer 81 is an RDL, the second wiring layer 81 can include one metal layer or multiple metal layers.

[0254] When the second wiring structure 80 includes multiple second wiring layers 81, the present application embodiments do not limit the interconnection method between the two adjacent second wiring layers 81.

[0255] In some possible implementations, electrical connections between two adjacent second wiring layers 81 can be achieved through via interconnection.

[0256] For further possible implementations, please refer to [link / reference]. Figure 13a The encapsulation structure 10 also includes a third interconnect structure 90, which includes a third dielectric support layer 91 and a third interconnect layer 92. At least two adjacent second wiring layers 81 are staggered along a direction perpendicular to the second surface 22, wherein the staggered arrangement of adjacent second wiring layers 81 means that the projections of adjacent second wiring layers 81 onto the plane of the second surface 22 do not overlap. A third dielectric support layer 91 is embedded within a second insulating layer 82 between the staggered adjacent second wiring layers 81. The third interconnect layer 92 is disposed on the third dielectric support layer 91 and electrically connects the staggered adjacent second wiring layers 81.

[0257] For example, the height of the third dielectric support layer 91 gradually increases in the direction perpendicular to the second surface 21. Correspondingly, the surface of the third dielectric support layer 91 where the third interconnect layer 82 is located (also referred to as the third support surface) gradually increases, that is, the distance between the third support surface of the third dielectric support layer 91 where the third interconnect layer 82 is located and the plane where the second surface 22 is located gradually increases. Specifically, it increases from the height of one of the second wiring layers 81 to the height of another second wiring layer 81 adjacent to that second wiring layer 81. For example, the second second wiring layer 81 and the third second wiring layer 81 are staggered, and the third dielectric support layer 91 is embedded in the second insulating layer 82 between the second second wiring layer 81 and the third second wiring layer 81. The third support surface of the third dielectric support layer 91 increases from the height of the second second wiring layer 81 to the height of the third second wiring layer 81. In this way, when the third interconnect layer 82 is disposed on the third support surface of the third dielectric support layer 91, the third interconnect layer 82 can directly overlap with the lower height of the second wiring layer 81, and can also directly overlap with the higher height of the third wiring layer 81, so that the second wiring layer 81 can be electrically connected to the third wiring layer 81 through the third interconnect layer 82.

[0258] It should be noted that, Figure 13a The explanation is based on the example of a first pad 33 being electrically connected to the second layer 51 of the first wiring structure 50, and the first wiring structure 50 having a second interconnection structure 60.

[0259] In this case, the signal of the first functional device 30 can be output or input through the first interconnect layer 42, the second first wiring layer 51, the second first insulating layer (i.e., the first insulating layer between the second and third first wiring layers 51) 52, the third first wiring layer 51, the second interconnect layer 62 on the second dielectric support layer 61 within the third first insulating layer (i.e., the first insulating layer between the third and fourth first wiring layers 51), and the fourth first wiring layer 51, which are electrically connected to one of the first pads 33. Furthermore, the signal of the first functional device 30 can be input or output through the first interconnect layer 42, the first second wiring layer 81, the second dielectric support layer 91 within the first first insulating layer (i.e., the second insulating layer between the first and second wiring layers 81 and the second wiring layer 81), the second second wiring layer 81, the third interconnect layer 92 on the third dielectric support layer 91 within the second second insulating layer (i.e., the second insulating layer between the second and third wiring layers 81), the third second wiring layer 81, the third interconnect layer 92 on the third dielectric support layer 91 within the third second insulating layer (i.e., the second insulating layer between the third and fourth wiring layers 81), and the fourth second wiring layer 81, which are electrically connected to another first pad 33.

[0260] A third interconnect structure 90 is provided within the second wiring structure 80, allowing not only the first functional device 30 and the second wiring structure 80 to be interconnected without vias or metal wires, but also the second wiring layers 81 of the second wiring structure 80 to be interconnected without vias or metal wires. This achieves double-sided signal output from the package structure 10 while further effectively reducing interconnect parasitic inductance, lowering coupling effects, and consequently reducing interconnect losses.

[0261] This application does not limit the material of the third dielectric support layer 91. For example, the material of the third dielectric support layer 91 may include photoresist or epoxy resin, which can provide the dielectric constant and support for the third interconnect layer 92. It should be noted that in actual installation, the materials of the first dielectric support layer 41, the second dielectric support layer 61, and the third dielectric support layer 91 can be the same, completely different, or partially the same; this application does not limit this.

[0262] The material of the third interconnect layer 92 is not limited in this embodiment. For example, the material of the third interconnect layer 92 may include conductive materials such as nano-silver or nano-copper. It should be noted that in actual configuration, the materials of the first interconnect layer 42, the second interconnect layer 62, and the third interconnect layer 92 may be the same, different, or partially the same, and this embodiment does not limit this.

[0263] In the above example, when the height of the third support surface of the third interconnect layer 92 on the third dielectric support layer 91 gradually increases, the third support surface can be an inclined surface (the inclined surface has a preset angle with the plane where the second surface 22 is located), a curved surface (the line connecting the two ends of the curved surface has a preset angle with the plane where the second surface 22 is located), or a stepped surface, etc. The shape of the third support surface is not limited in the embodiments of this application.

[0264] When a third dielectric support layer 91 is provided within each of the multiple second insulating layers 82, the number of third dielectric support layers 91 is also multiple. At least a portion of the multiple third dielectric support layers 91 can be integrally formed, that is, all of the multiple third dielectric support layers 91 are integrally formed; or, a portion of the multiple third dielectric support layers 91 can be integrally formed. For example, see [link to example]. Figure 13b , Figure 13b This is a schematic diagram of another packaging structure provided in an embodiment of this application. A third dielectric support layer 91 located within a second insulating layer 82 between the second wiring layer 81 and the third wiring layer 81, and a third dielectric support layer 91 located within a second insulating layer 82 between the third wiring layer 81 and the fourth wiring layer 81, are integrally formed. When at least a portion of the plurality of third dielectric support layers 91 are integrally formed, the process steps can be simplified.

[0265] The following descriptions are based on the example of the third dielectric support layer 91 being configured separately.

[0266] In some embodiments, see continue to see Figure 13a The packaging structure also includes at least one third functional device 100, which is located on the side of the second wiring structure 80 away from the support structure 20. The third functional device 100 is electrically connected to the second wiring structure 80. Specifically, the third functional device 100 may be provided with a third pad 101, which is used to lead out the connection point of the third functional device 80. The third pad 101 of the third functional device 100 may be electrically connected to the fourth (last) second wiring layer 81 of the second wiring structure 80.

[0267] This enables higher-density integration through three-dimensional stacking, allowing the package structure 10 to perform more complex functions. Furthermore, when the second wiring layers 81 of the second wiring structure 80 are connected via the third interconnect layer 92 on the third dielectric support layer 91, the first functional device 30 and the third functional device 100 can be interconnected through the first interconnect layer 41, the second wiring layer 81, and the third interconnect layer 92. Compared to traditional interconnection methods for multifunctional devices (vias and / or metal wire interconnection), this effectively reduces losses between multiple functional device interconnections, expands the operating frequency band, and reduces the overall package size, achieving flexible, high-density, and high-performance integrated packaging of multi-layer functional devices.

[0268] The embodiments of this application do not limit the third functional device 100. For example, the third functional device 100 can be a bare die, where a die is a chip before it is packaged. Each die is an unpackaged chip with independent function, and it can be composed of one or more circuits. Of course, the third functional device 100 can also be a packaging assembly that packages a single die; or a packaging assembly that packages multiple dies. The third functional device 100 may also not be a chip, but rather some device with circuit functions (e.g., a module that achieves chip functions without relying on traditional semiconductor integrated circuit structures, but through microelectromechanical systems, photonic integration, carbon-based materials, or other equivalent technologies), which is not limited herein.

[0269] In some embodiments, see Figure 14 , Figure 14 This is a schematic diagram of another packaging structure provided in an embodiment of this application. The packaging structure also includes a fourth functional device 110, which is also disposed in the cutout portion 23. A fourth pad 111 may be provided on the fourth functional device 110. The fourth pad 111 is used to lead out the connection point of the fourth functional device 110, and the signal of the fourth functional device 110 can be input and / or output through the fourth pad 111.

[0270] The surface of the fourth functional device 110 with the fourth pad 111 is flush with the upper surface 31 of the first functional device 30 with the first pad 33. A first dielectric support layer 41 is also provided between the first functional device 30 and the fourth functional device 110. The first interconnect layer 42 on the first dielectric support layer 41 between the first functional device 30 and the fourth functional device 110 can be electrically connected to the first functional device 30 and the fourth functional device 110 respectively, so that the fourth functional device 110 is electrically connected to the first functional device 30 through the first interconnect layer 42.

[0271] This allows for a smooth interconnection between the first functional device 30 and the fourth functional device 110, eliminating the need for vias and metal wires. This effectively reduces parasitic inductance in the interconnection, lowers coupling effects, and consequently reduces losses between interconnects, extending the operating frequency band. Furthermore, replacing vias and metal wires with the first interconnect layer 42 reduces the interconnection length between the first functional device 30 and the fourth functional device 110, avoiding increased signal loss due to excessively long lines, and also helps to reduce the size of the package structure.

[0272] See also Figure 14 The fourth functional device 110 can be electrically connected not only to the first functional device 30, but also to the third functional device 100 located on the side of the second wiring structure 80 opposite to the support structure 20. Specifically, one of the fourth pads 111 of the fourth functional device 110 is electrically connected to the first functional device 30 through the first interconnect layer 42, and the other fourth pad 111 of the fourth functional device 110 is electrically connected to the second wiring structure 80 through the first interconnect layer 42, and then electrically connected to the third functional device 100 through the second wiring structure 80.

[0273] The embodiments of this application do not limit the fourth functional device 110. For example, the fourth functional device 110 can be a bare die, where a die is a chip before it is packaged. Each die is an unpackaged chip with independent function, and it can consist of one or more circuits. Of course, the fourth functional device 110 can also be a packaging assembly that packages a single die; or a packaging assembly that packages multiple dies. The fourth functional device 110 may also not be a chip, but rather some device with circuit functions (e.g., a module that implements chip functions without relying on traditional semiconductor integrated circuit structures, but through microelectromechanical systems, photonic integration, carbon-based materials, or other equivalent technologies), which is not limited herein.

[0274] As can be seen from the foregoing, the aforementioned functional devices can be chips (such as bare chips or chip package components). When the aforementioned functional devices can be chips, each functional device can be a heterogeneous chip (i.e., the substrate materials of the chips are different). For example, the first functional device 30 and the fourth functional device 110 are both gallium arsenide (GaAs) chips, the second functional device 70 is a silicon (Si) chip, and the third functional device 100 is a gallium nitride (GaN) chip.

[0275] In summary, the packaging structure 10 provided in this application embodiment achieves smooth interconnection between the first functional device 30 and the first wiring structure 50 through the first interconnect layer 42 disposed on the first dielectric support layer 41, without the need for vias or metal wires. This effectively reduces interconnect parasitic inductance and interconnect transmission loss, and extends the operating frequency band. For example, it has been verified that the packaging structure 10 provided in this application embodiment reduces parasitic inductance and interconnect transmission loss by more than 10 times, and the operating bandwidth can be extended to more than 250GHz, effectively solving the problems of high interconnect loss, narrow bandwidth, and large parasitic parameters in existing packaging structures.

[0276] To illustrate this beneficial effect in detail, a comparison with related technologies is provided below.

[0277] Figure 15 The diagram illustrates the simulation relationship between the microstrip lines on the chip and the microstrip lines on the packaging substrate when interconnected using gold wire bonding. The packaging substrate is a glass substrate, and microstrip line 1 on the glass substrate has a linewidth of 104 μm and a characteristic impedance of 50 Ω. The chip substrate is made of GaAs material with a thickness of 50 μm and a relative permittivity ε. r The linewidth of microstrip line 2 on the chip is 29 μm, and the characteristic impedance is 50 Ω. The gap between the glass packaging substrate and the embedded GaAs chip is 80 μm. The diameter of the gold wire bonded to the chip is 18 μm, the arch height is 50 μm, and the span (i.e., arch length) is 300 μm.

[0278] The electrical performance simulation results and parasitic inductance distribution results are as follows: Figure 16a and Figure 16b As shown. Among them, Figure 16a and Figure 16b The horizontal axis represents frequency. Figure 16a The vertical axis represents the loss value, in dB. Figure 16b The vertical axis represents the inductance value, with the unit being nH. Figure 16a S11 and S21 in the figure are the return loss curve and the insertion loss curve, respectively.

[0279] The electrical performance simulation results show that: in the frequency band below 32.12GHz, the interconnect structure works well, with an overall return loss better than -15dB and an insertion loss less than 0.18dB; the return loss deteriorates rapidly in the high-frequency band (75GHz: return loss greater than -8dB, insertion loss greater than 0.9dB); the parasitic inductance value is between 0.22nH and 0.91nH, which is relatively large.

[0280] Figure 17 This diagram illustrates the simulation relationship between the isolation structure and the interconnect pads on the package substrate when interconnecting vias. Figure 17 Only one via is shown, where, Figure 17In the via, the diameter is 60μm (copper plated), the depth is 50μm, the dimension of one side W1 of the via pad is 30μm, the inner radius R1 of the isolation structure is 140μm, and the relative permittivity ε of the packaging substrate is... r The characteristic impedance is 3.47, the loss tangent is 0.014 (glass substrate or IC packaging substrate), and the characteristic impedance of the via coaxial structure is 50Ω.

[0281] The electrical performance simulation results and the distribution results of parasitic capacitances (including the coaxial capacitance of vias and the electromagnetic parasitic capacitance between vias and isolation structures) are as follows: Figure 18a and Figure 18b As shown. Among them, Figure 18a and Figure 18b The horizontal axis represents frequency. Figure 18a The vertical axis represents the loss value, in dB. Figure 18b The vertical axis represents the capacitance value, in nF. Figure 18a S11 and S21 in the figure are the return loss curve and the insertion loss curve, respectively.

[0282] The electrical performance simulation results show that: in the frequency band below 99GHz, the interconnect structure works well, with an overall return loss better than -15dB and an insertion loss of less than 0.18dB; the return loss gradually deteriorates in the high-frequency band, and the operating frequency band is less than 100GHz; in the frequency range of 10GHz to 75GHz, the parasitic capacitance value is 0.016pF.

[0283] Figure 19 The diagram illustrates the simulation relationships between the structures within the package structure when using the interconnection method described in this application. Figure 19 The diagram illustrates an interconnection where the first pad of the first functional device and the first wiring layer have a height difference (i.e., the height of the first wiring layer is higher than the height of the first pad located on the first functional device). Figure 19 In the first functional device, the first functional device is a gallium arsenide (GaAs) bare chip, the width of the first dielectric support layer is 60μm, the height of the portion of the first dielectric support layer 41 extending beyond the support structure 20 gradually increases to 30μm, and the height of the first interconnect layer gradually increases to 30μm.

[0284] The electrical performance simulation results and parasitic inductance distribution results are as follows: Figure 20a and Figure 20b As shown. Among them, Figure 20a and Figure 20b The horizontal axis represents frequency. Figure 20a The vertical axis represents the loss value, in dB. Figure 20b The vertical axis represents the inductance value, with the unit being nH. Figure 20a S11, S22, S21, and S22 in the figure represent the input return loss curve, output return loss curve, forward insertion loss curve, and reverse insertion loss curve, respectively.

[0285] The electrical performance simulation results show that the transmission loss of the interconnection method in this application is essentially zero, meaning that the interconnection method in this application has extremely low transmission loss and an extremely wide operating bandwidth. Furthermore, the parasitic inductance is nearly zero.

[0286] Figure 21 The diagram illustrates the simulation relationships between the structures within the package structure when using the interconnection method described in this application. Figure 21 This diagram illustrates an interconnection where the first pad of the first functional device and the first wiring layer have no height difference (i.e., the first wiring layer and the first pad of the first functional device have the same height). Figure 21 In this design, the first functional device is a gallium arsenide (GaAs) bare chip, and the width of the first dielectric support layer is 60 μm.

[0287] The electrical performance simulation results and parasitic inductance distribution results are as follows: Figure 22a and Figure 22b As shown. Among them, Figure 22a and Figure 22b The horizontal axis represents frequency. Figure 22a The vertical axis represents the loss value, in dB. Figure 22b The vertical axis represents the inductance value, with the unit being nH. Figure 22a S11, S22, S21, and S22 in the figure represent the input return loss curve, output return loss curve, forward insertion loss curve, and reverse insertion loss curve, respectively.

[0288] The electrical performance simulation results show that the transmission loss of the interconnection method in this application is essentially zero, meaning that the interconnection method in this application has extremely low transmission loss and an extremely wide operating bandwidth. Furthermore, the parasitic inductance is nearly zero.

[0289] To better illustrate the superior performance of the interconnection method in this application, a performance comparison is provided below between the interconnection method of this application and the gold wire bonding and via interconnection methods used in related technologies. In this application, the performance comparison is based on the fact that there is a height difference between the first pad of the first functional device and the first wiring layer (i.e., the height of the first wiring layer is higher than the height of the first pad located on the first functional device).

[0290] See Figure 23a and Figure 23b ,in, Figure 23a A simulation comparison graph of the insertion loss of related technologies and this application is shown. Figure 23b Simulation comparison diagrams of the parasitic inductance of related technologies and this application are shown, in which... Figure 23a and Figure 23bThe insertion loss and parasitic inductance of this application shown are the insertion loss and parasitic inductance when there is a height difference between the first pad of the first functional device and the first wiring layer (i.e., the height of the first wiring layer is higher than the height of the first pad of the first functional device).

[0291] In conjunction with Table 1, Table 1 compares the insertion loss and parasitic inductance of the interconnection method of this application with the interconnection method of gold wire bonding and via. In Table 1, (1) represents the gold wire bonding interconnection method, (2) represents the via interconnection method, and (3) represents the interconnection method of this application. The first pad of the first functional device and the first wiring layer have a height difference (i.e., the height of the first wiring layer is higher than the height of the first pad located on the first functional device). (3) / (1) represents the ratio of the value obtained by the interconnection method of this application to the value obtained by the interconnection method of gold wire bonding, and (3) / (2) represents the ratio of the value obtained by the interconnection method of this application to the value obtained by the interconnection method of via.

[0292] Table 1 compares the insertion loss and parasitic inductance of the interconnection method in this application with those of gold wire bonding and via interconnection methods.

[0293]

[0294] pass Figure 23a , Figure 23b As shown in Table 1, at lower frequencies, the insertion loss and parasitic inductance of the interconnection method proposed in this application, the gold wire bonding interconnection method, and the via interconnection method are all relatively small. However, the insertion loss and parasitic inductance of the interconnection method proposed in this application are still smaller than those of the gold wire bonding interconnection method and the via interconnection method. As the frequency increases, the insertion loss and parasitic inductance of the interconnection method proposed in this application, the gold wire bonding interconnection method, and the via interconnection method all increase. However, the insertion loss and parasitic inductance of the interconnection method proposed in this application are still superior to those of the gold wire bonding interconnection method and the via interconnection method.

[0295] Therefore, it can be concluded that the interconnection method provided in this application embodiment has significant advantages in terms of parasitic inductance and interconnection transmission loss: compared with the gold wire bonding interconnection method, the parasitic inductance and interconnection loss are reduced by more than 10 times; compared with the gold wire bonding interconnection method and the via interconnection method, the operating bandwidth can be extended to more than 250GHz.

[0296] It should be noted that the above comparison is based on the performance obtained when there is a height difference between the first pad of the first functional device and the first wiring layer (i.e., the height of the first wiring layer is higher than the height of the first pad of the first functional device). The performance obtained is not compared when there is no height difference between the first pad of the first functional device and the first wiring layer (i.e., the heights of the first wiring layer and the first pad of the first functional device are the same). However, the performance obtained when there is no height difference between the first pad of the first functional device and the first wiring layer (i.e., the heights of the first wiring layer and the first pad of the first functional device are the same) is better.

[0297] Based on the same technical concept, this application also provides a method for preparing a packaging structure, which can be used to prepare the packaging structures in some of the above embodiments. Since the principle of this preparation method in solving the problem is similar to that of the aforementioned packaging structure, the implementation of this preparation method can refer to the implementation of the packaging structure above, and repeated details will not be described again.

[0298] It should be noted that the packaging structure 10 of this application can have many different structures and can be implemented in various ways. The following embodiments are merely some preferred implementation methods used to illustrate the feasibility of the packaging structure described in this application and do not limit the scope of this application. Packaging structures implemented through other processes or sequences are also within the protection scope of this application.

[0299] by Figure 11a For example, please refer to the packaging structure shown below. Figure 24 and combined Figures 25a to 25g The packaging structure can be fabricated through the following steps:

[0300] S101. As Figure 25a As shown, the support structure 20 is placed on the grounding layer carrier plate 340, wherein the support structure 20 has a hollow portion 23.

[0301] In this step, the support structure 20 is placed on the grounding layer carrier plate 340, with the second surface 22 of the support structure 20 facing the grounding layer carrier plate 340.

[0302] The grounding layer carrier plate 340 has at least one grounding layer 34, which can be formed on the surface of the grounding layer carrier plate 340 or stacked inside the grounding layer carrier plate 340. Figure 25a The grounding layer carrier plate 340 shown includes three grounding layers 34, with at least one grounding layer 34 formed on the surface of the grounding layer carrier plate 340, as an example for illustration.

[0303] The aforementioned support structure 20 has a hollow portion 23. The support structure 20 may be placed on the grounding layer carrier plate 340 after the hollow portion 23 is formed on the support structure 20; or the hollow portion 23 may be formed on the support structure 20 after it is placed on the grounding layer carrier plate 340. This application embodiment does not limit this.

[0304] The method of forming the hollow part 23 on the support structure 20 is not limited in the embodiments of this application. For example, the hollow part 23 can be made on the support structure 20 by drilling.

[0305] S102. As Figure 25b As shown, the first functional device 30 is disposed in the hollow part 23 of the support structure 20, wherein the upper surface 31 of the first functional device 30 is provided with a first pad 33.

[0306] In this step, when the first functional device 30 is placed in the hollow portion 23 of the support structure 20, the lower surface 32 of the first functional device 30 faces the grounding layer carrier plate 340. The first pad 33 is used to bring out the connection point of the first functional device 30.

[0307] S103. For example Figure 25c As shown, a grounding connection layer 43 is formed in the hollow portion 23, and between the support structure 20 and the first functional device 30.

[0308] In this step, a ground connection layer 43 can be formed in the cutout portion 23 and between the support structure 20 and the first functional device 30 by additive manufacturing. Since one of the ground layers 34 is located on the surface of the ground layer carrier plate 340, the ground connection layer 43 can directly overlap with the ground layer 34 when the ground connection layer 43 is formed, thereby realizing an electrical connection with the ground layer 34.

[0309] S104. For example Figure 25d As shown, a first dielectric support layer 41 is formed in the hollow portion 23 and between the support structure 20 and the first functional device 30.

[0310] In this step, a first dielectric support layer 41 can be formed in the cutout portion 23 and between the support structure 20 and the first functional device 30 by additive manufacturing.

[0311] When a first dielectric support layer 41 is formed in the cutout portion 23 and between the support structure 20 and the first functional device 30, a portion of the first dielectric support layer 41 may extend beyond the first surface 21 of the support structure 20, and the height of the portion of the first dielectric support layer 41 extending beyond the first surface 21 of the support structure 20 gradually increases in the direction perpendicular to the first surface 21.

[0312] S105. (e.g.) Figure 25eAs shown, a first interconnect layer 42 is formed on the surface of the first dielectric support layer 41 on the side opposite to the ground connection layer 43, wherein the first interconnect layer 42 is electrically connected to the first pad 33.

[0313] In this step, the first interconnect layer 42 can be formed on the surface of the first dielectric support layer 41 on the side opposite to the ground connection layer 43 by additive manufacturing.

[0314] When the first interconnect layer 42 is formed, the first interconnect layer 42 can extend to the upper surface 31 of the first functional device 30 and overlap with the first pad 33 located on the upper surface 31, thereby realizing electrical connection with the first pad 33.

[0315] As the portion of the first dielectric support layer 41 extending beyond the first surface 21 of the support structure 20 gradually increases in height in the direction perpendicular to the first surface 21, the first interconnect layer 42 formed on the first dielectric support layer 41 will also gradually increase, that is, the distance between the first interconnect layer 42 and the plane where the first surface 21 is located gradually increases, such as increasing to the same height as one of the first wiring layers 51 in the first wiring structure 50 (which will be mentioned in subsequent steps), so that the first interconnect layer 42 can be electrically connected to the first wiring layer 51.

[0316] S106. For example Figure 25f As shown, a first wiring structure 50 and a second interconnection structure 60 are formed on the first surface 21 of the support structure 20.

[0317] The first wiring structure 50 includes a first wiring layer 51, a second wiring layer 51, a third wiring layer 51, a fourth wiring layer 51, and a first insulating layer 52 located between two adjacent wiring layers 51. A first interconnect layer 42 is electrically connected to both the first wiring layer 51 and the second wiring layer 51. Thus, one first pad 33 is electrically connected to the first wiring layer 51 via the first interconnect layer 42, and the other first pad 33 is electrically connected to the second wiring layer 51 via the first interconnect layer 42.

[0318] The second interconnect structure 60 includes a second dielectric support layer 61 and a second interconnect layer 62. Adjacent first wiring layers 51 are staggered. Each first insulating layer 52 has a second dielectric support layer 61 embedded within it, and the second interconnect layer 62 located on the second dielectric support layer 61 can electrically connect adjacent first wiring layers 51.

[0319] S107. For example Figure 25g As shown, a second functional device 70 is provided on the side of the first wiring structure 50 away from the support structure 20, wherein the second functional device 70 is electrically connected to the first wiring structure 50.

[0320] When the second functional device 70 is disposed on the side of the first wiring structure 50 away from the support structure 20, the first functional device 30 and the second functional device 70 can be interconnected through the first wiring structure 50 and the second interconnection structure 60.

[0321] See Figure 26 and combined Figures 27a-27m A first wiring structure 50 and a second interconnection structure 60 are formed on the first surface 21 of the support structure 20, which may include:

[0322] S1061. For example Figure 27a As shown, a first wiring layer 51 is formed on the first surface 21 of the support structure 20.

[0323] The first wiring layer 51 is electrically connected to the first interconnect layer 42, and one of the first pads 33 is electrically connected to the first wiring layer 51 through the first interconnect layer 42.

[0324] S1062. For example Figure 27b As shown, a second dielectric support layer 61 is formed.

[0325] In this step, the second dielectric support layer 61 can be formed by additive manufacturing.

[0326] S1063. For example Figure 27c As shown, a second interconnect layer 62 is formed on the second dielectric support layer 61.

[0327] In this step, the second interconnect layer 62 can be formed on the second dielectric support layer 61 by additive manufacturing.

[0328] The second interconnect layer 62 is directly connected to the first wiring layer 51, so that the second interconnect layer 62 and the first wiring layer 51 are electrically connected.

[0329] S1064. For example Figure 27d As shown, the first insulating layer 52 is formed.

[0330] The first insulating layer 52 covers the first wiring layer 51 and the second dielectric support layer 61, exposing a portion of the first interconnect layer 42 and a portion of the second interconnect layer 62.

[0331] S1065. For example... Figure 27e As shown, a second first wiring layer 51 is formed on the first insulating layer 52.

[0332] The second layer first wiring layer 51 overlaps with the exposed first interconnect layer 42 and the exposed second interconnect layer 62, so that the second layer first wiring layer 51 is electrically connected to the first interconnect layer 42 and the second interconnect layer 62, and then electrically connected to one of the first pads 33 through the first interconnect layer 42, and electrically connected to the first layer first wiring layer 51 through the second interconnect layer 62.

[0333] S1066. For example Figure 27f As shown, a second dielectric support layer 61 is formed.

[0334] In this step, the second dielectric support layer 61 can be formed by additive manufacturing.

[0335] S1067. For example Figure 27g As shown, a second interconnect layer 62 is formed on the second dielectric support layer 61.

[0336] In this step, the second interconnect layer 62 can be formed on the second dielectric support layer 61 by additive manufacturing.

[0337] The second interconnect layer 62 is directly connected to the second first wiring layer 51, so that the second interconnect layer 62 and the second first wiring layer 51 are electrically connected.

[0338] S1068. For example Figure 27h As shown, a second first insulating layer 52 is formed.

[0339] The second insulating layer 52 covers the second wiring layer 51 and the second dielectric support layer 61, exposing a portion of the second interconnect layer 62.

[0340] S1069. For example Figure 27i As shown, a third first wiring layer 51 is formed on the second first insulating layer 52.

[0341] In this configuration, the third layer first wiring layer 51 overlaps with the exposed second interconnect layer 62, thereby electrically connecting the third layer first wiring layer 51 with the second interconnect layer 62, and then achieving electrical connection between the second layer first wiring layer 51 and the third layer first wiring layer 51 through the second interconnect layer 62.

[0342] S10691. For example Figure 27j As shown, a second dielectric support layer 61 is formed.

[0343] In this step, the second dielectric support layer 61 can be formed by additive manufacturing.

[0344] S10692. For example Figure 27k As shown, a second interconnect layer 62 is formed on the second dielectric support layer 61.

[0345] In this step, the second interconnect layer 62 can be formed on the second dielectric support layer 61 by additive manufacturing.

[0346] The second interconnect layer 62 is directly connected to the third first wiring layer 51, so that the second interconnect layer 62 and the third first wiring layer 51 are electrically connected.

[0347] S10693. For example... Figure 27 As shown, the third layer of the first insulating layer 52 is formed.

[0348] The third insulating layer 52 covers the third wiring layer 51 and the second dielectric support layer 61, exposing a portion of the second interconnect layer 62.

[0349] S10694. (e.g.) Figure 27m As shown, a fourth first wiring layer 51 is formed on the third first insulating layer 52.

[0350] The fourth layer first wiring layer 51 overlaps with the exposed second interconnect layer 62, so that the fourth layer first wiring layer 51 is electrically connected to the second interconnect layer 62, and then the third layer first wiring layer 51 and the fourth layer first wiring layer 51 are electrically connected through the second interconnect layer 62.

[0351] by Figure 14 For example, please refer to the packaging structure shown below. Figure 28 and combined Figures 29a to 29i The packaging structure can be fabricated through the following steps:

[0352] S201. As Figure 29a As shown, the support structure 20 is placed on the temporary carrier plate 350, wherein the support structure 20 has a hollow portion 23.

[0353] In this step, when the support structure 20 is placed on the temporary carrier plate 350, the second surface 22 of the support structure 20 faces the temporary carrier plate 350.

[0354] S202. For example Figure 29b As shown, the first functional device 30 and the fourth functional device 110 are both disposed in the hollow part 23 of the support structure 20. The first functional device 30 is provided with a first pad 33 on its upper surface, and the fourth functional device 110 is provided with a fourth pad 111 on its upper surface.

[0355] The first pad 33 is used to bring out the connection point of the first functional device 30, and the fourth pad 111 is used to bring out the connection point of the fourth functional device 110.

[0356] In this step, when the first functional device 30 and the fourth functional device 110 are placed in the hollowed-out portion 23 of the support structure 20, the lower surface of the first functional device 30 (i.e., the surface without the first pad 33) and the lower surface of the fourth functional device 110 (i.e., the surface without the fourth pad 111) face the grounding layer carrier plate 340.

[0357] S203. For example Figure 29c As shown, a first dielectric support layer 41 is formed in the cutout portion 23, between the support structure 20 and the first functional device 30, and between the first functional device 30 and the fourth functional device 110.

[0358] In this step, a first dielectric support layer 41 can be formed in the cutout portion 23, between the support structure 20 and the first functional device 30, and between the first functional device 30 and the fourth functional device 110 by additive manufacturing.

[0359] S204. For example Figure 29d As shown, a first interconnect layer 42 is formed on the surface of the first dielectric support layer 41, wherein the first interconnect layer 42 is electrically connected to the first pad 33 and the fourth pad 111, respectively.

[0360] In this step, the first interconnect layer 42 can be formed on the surface of the first dielectric support layer 41 by additive manufacturing.

[0361] When forming the first interconnect layer 42, the first interconnect layer 42 can extend to the upper surface of the first functional device 30 and the upper surface of the fourth functional device 110, overlap with the first pad 33 located on the upper surface of the first functional device 30, and overlap with the fourth pad 111 located on the upper surface of the fourth functional device 110, thereby realizing electrical connection with the first pad 33 and the fourth pad 111.

[0362] S205. For example Figure 29e As shown, a first wiring structure 50 and a second interconnection structure 60 are formed on the first surface 21 of the support structure 20.

[0363] The specific structure and formation steps of the first wiring structure 50 and the second interconnection structure 60 can be found in [reference needed]. Figure 26 and Figures 27a-27m This will not be elaborated upon here.

[0364] S206. For example Figure 29f As shown, a second functional device 70 is provided on the side of the first wiring structure 50 away from the support structure 20, wherein the second functional device 70 is electrically connected to the first wiring structure 50.

[0365] When the second functional device 70 is disposed on the side of the first wiring structure 50 away from the support structure 20, the first functional device 30 and the second functional device 70 can be interconnected through the first wiring structure 50 and the second interconnection structure 60.

[0366] S207. For example Figure 29g As shown, the temporary carrier plate 350 is peeled off.

[0367] S208. For example Figure 29h As shown, a second wiring structure 80 and a third interconnection structure 90 are formed on the second surface 22 of the support structure 20, wherein the first interconnection layer 42 passes through the cutout portion 23 and is electrically connected to the second wiring structure 80.

[0368] The second wiring structure 80 includes a first second wiring layer 81, a second second wiring layer 81, a third second wiring layer 81, a fourth second wiring layer 81, and a second insulating layer 82 located between two adjacent second wiring layers 81. The first second wiring layer 81 is offset from the first pad 33 of the first functional device 30 along a direction perpendicular to the second surface 22.

[0369] The third interconnect structure 90 includes a third dielectric support layer 91 and a third interconnect layer 92. Adjacent second wiring layers 81 are staggered. Each second insulating layer 82 has a third dielectric support layer 91 embedded within it, and the third interconnect layer 92 located on the third dielectric support layer 91 can electrically connect to adjacent second wiring layers 81.

[0370] The specific steps for forming the second wiring structure 80 and the third interconnection structure 90 on the second surface 22 of the support structure 20 are similar to the specific steps for forming the first wiring structure 50 and the second interconnection structure 60 on the first surface 21 of the support structure 20. For details, please refer to the specific steps for forming the first wiring structure 50 and the second interconnection structure 60 on the first surface 21 of the support structure 20. These steps will not be repeated here.

[0371] When forming the first and second wiring layers 81, the ground layer of the first functional device 30 and the ground layer of the fourth functional device 110 can also be formed.

[0372] S209. For example Figure 29i As shown, a third functional device 100 is provided on the side of the second wiring structure 80 away from the support structure 20, wherein the third functional device 100 is electrically connected to the second wiring structure 80.

[0373] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A packaging structure, characterized in that, include: First functional device; A support structure having a hollowed-out portion, wherein the first functional device is disposed in the hollowed-out portion; A first interconnect structure, comprising a first dielectric support layer and a first interconnect layer, wherein the first dielectric support layer is located in the cutout portion and between the support structure and the first functional device; the first dielectric support layer at least partially surrounds the first functional device; the first interconnect layer is disposed on the first dielectric support layer and is electrically connected to the first functional device. A first wiring structure is provided on the support structure, and the first wiring structure is electrically connected to the first interconnect layer.

2. The packaging structure according to claim 1, characterized in that, The support structure includes a first surface, and the first wiring structure is disposed on the first surface; the electrical connection between the first interconnect layer and the first functional device and the first wiring structure are located on the same side of the first functional device.

3. The packaging structure according to claim 1 or 2, characterized in that, The first wiring structure includes at least one first wiring layer, and the first interconnect layer is electrically connected to at least one first wiring layer.

4. The packaging structure according to claim 2, characterized in that, The first wiring structure includes multiple first wiring layers stacked along a direction away from the first surface and a first insulating layer located between two adjacent first wiring layers; The first interconnect layer is electrically connected to the first wiring layer of the first layer and / or the first wiring layer of the second layer; wherein, the first wiring layer of the first layer is the first wiring layer disposed on the first surface; and along the direction perpendicular to the first surface, the first wiring layer of the second layer is the first wiring layer that is closest to the first wiring layer of the first layer.

5. The packaging structure according to claim 4, characterized in that, When the first interconnect layer is electrically connected to the first wiring layer of the second layer, the connection points of the first wiring layer of the second layer and the first functional device are staggered along the direction perpendicular to the first surface, and the surface of the first dielectric support layer on which the first interconnect layer is located gradually rises.

6. The packaging structure according to claim 4 or 5, characterized in that, It also includes a second interconnect structure, which includes a second dielectric support layer and a second interconnect layer; Along a direction perpendicular to the first surface, at least two adjacent first wiring layers are staggered, and the first insulating layer between the staggered adjacent first wiring layers contains the second dielectric support layer; the second interconnect layer is disposed on the second dielectric support layer and electrically connects the staggered adjacent first wiring layers.

7. The packaging structure according to claim 6, characterized in that, The plurality of second dielectric support layers and the first dielectric support layer are at least partially integrally formed.

8. The packaging structure according to claim 6 or 7, characterized in that, The surface of the second dielectric support layer, where the second interconnect layer is located, gradually rises.

9. The packaging structure according to any one of claims 1-8, characterized in that, It also includes a second functional device, which is located on the side of the first wiring structure away from the support structure; The second functional device is electrically connected to the first wiring structure.

10. The packaging structure according to any one of claims 2-9, characterized in that, The support structure further includes a second surface, which is opposite to the first surface; The packaging structure further includes a second wiring structure disposed on the second surface, and the first interconnect layer passes through the cutout and is electrically connected to the second wiring structure.

11. The packaging structure according to claim 10, characterized in that, The second wiring structure includes multiple layers of second wiring layers stacked along a direction away from the second surface and a second insulating layer located between two adjacent layers of second wiring layers; Along a direction perpendicular to the second surface, the connection points of the first layer of the second wiring layer and the first functional device are staggered; the first interconnect layer passes through the cutout and is electrically connected to the first layer of the second wiring layer; wherein, the first layer of the second wiring layer is the second wiring layer disposed on the second surface; The packaging structure further includes a third interconnect structure, which includes a third dielectric support layer and a third interconnect layer; at least two adjacent second wiring layers are staggered along a direction perpendicular to the second surface, and the third dielectric support layer is embedded in the second insulating layer between the staggered adjacent second wiring layers. The third interconnect layer is disposed on the third dielectric support layer and electrically connects the staggered adjacent second wiring layers.

12. The packaging structure according to claim 11, characterized in that, The surface of the third dielectric support layer, where the third interconnect layer is located, gradually rises.

13. The packaging structure according to any one of claims 10-12, characterized in that, It also includes a third functional device, which is located on the side of the second wiring structure opposite to the support structure; The third functional device is electrically connected to the second wiring structure.

14. The packaging structure according to any one of claims 1-13, characterized in that, It also includes a fourth functional device, which is also disposed in the hollow portion; a first dielectric support layer is also disposed between the first functional device and the fourth functional device; the fourth functional device is electrically connected to the first interconnect layer.

15. The packaging structure according to claim 4 or 10, characterized in that, The first dielectric support layer includes a plane and / or an inclined plane, wherein the plane is parallel to the first surface and the inclined plane has a preset angle with the first surface; when the first dielectric support layer includes an inclined plane, the first interconnect layer is disposed on the inclined plane.

16. The packaging structure according to any one of claims 2-15, characterized in that, The first functional device has a grounding layer on its back; The first interconnect structure further includes a ground connection layer, which is located on the surface of the first dielectric support layer away from the first interconnect layer, and the projection of the first interconnect layer on the first surface overlaps with the projection of the ground connection layer on the first surface. The surface of the first dielectric support layer having the ground connection layer is flush with the surface of the first functional device having the ground layer, and the ground connection layer is electrically connected to the ground layer.

17. The packaging structure according to any one of claims 1-16, characterized in that, The shape of the first interconnect layer includes rectangular branches or stepped branches.

18. The packaging structure according to any one of claims 1-17, characterized in that, The first functional device includes a bare chip, a chip package structure, or a device with circuit functions, wherein the chip package structure contains at least one bare chip.

19. An electronic device, characterized in that, It includes a printed circuit board and a packaging structure as described in any one of claims 1-18; the packaging structure is electrically connected to the printed circuit board.

20. A method for preparing a packaging structure, characterized in that, include: The first functional device is placed in the hollow part of the supporting structure; A first interconnection structure is formed in the hollowed-out portion and between the support structure and the first functional device. The first interconnection structure includes a first dielectric support layer and a first interconnection layer. The first dielectric support layer at least partially surrounds the first functional device. The first interconnection layer is disposed on the first dielectric support layer and is electrically connected to the first functional device. A first wiring structure is formed on the support structure, wherein the first wiring structure is electrically connected to the first interconnect layer.

21. The preparation method according to claim 20, characterized in that, The hollowed-out portion, and the first interconnection structure formed between the support structure and the first functional device, includes: The first dielectric support layer is formed in the hollowed-out portion and between the support structure and the first functional device; The first interconnect layer is formed on the first dielectric support layer.

22. The preparation method according to claim 21, characterized in that, The first dielectric support layer is formed in the hollowed-out portion and between the support structure and the first functional device, comprising: The first dielectric support layer is formed in the hollowed-out portion by additive manufacturing, and between the support structure and the first functional device; A first interconnect layer is formed on the first dielectric support layer, including: The first interconnect layer is formed on the first dielectric support layer by additive manufacturing.

23. The preparation method according to any one of claims 20-22, characterized in that, The support structure includes a first surface; A first wiring structure is formed on one side of the support structure, including: On the first surface, multiple layers of first wiring layers and a first insulating layer located between two adjacent layers of first wiring layers are sequentially formed. Wherein, the first interconnect layer is electrically connected to the first wiring layer of the first layer, and / or the first interconnect layer is electrically connected to the first wiring layer of the second layer, the first wiring layer of the first layer is the first wiring layer disposed on the first surface along a direction perpendicular to the first surface, the first wiring layer of the second layer is the first wiring layer that is closest to the first wiring layer of the first layer, and at least some of the adjacent first wiring layers are staggered. When forming multiple layers of first wiring layers and a first insulating layer located between two adjacent first wiring layers sequentially on the first surface, the method further includes: A second dielectric support layer is formed within the first insulating layer between two adjacent first wiring layers that are staggered; A second interconnect layer is formed on the second dielectric support layer; The second interconnect layer is electrically connected to two adjacent first wiring layers that are staggered.

24. The preparation method according to any one of claims 20-23, characterized in that, The support structure includes a second surface, which is the surface of the support structure facing away from the first wiring structure; After the first wiring structure is formed on one side of the support structure, the following is also included: A multilayer second wiring layer and a second insulating layer located between two adjacent second wiring layers are sequentially formed on the second surface; Wherein, along the direction perpendicular to the second surface, the connection points of the first layer of the second wiring layer and the first functional device are staggered, and at least two adjacent layers of the second wiring layer are staggered; the first interconnect layer passes through the cutout and is electrically connected to the first layer of the second wiring layer, and the first layer of the second wiring layer is the second wiring layer disposed on the second surface; When a multilayered second wiring layer and a second insulating layer located between two adjacent second wiring layers are sequentially formed on the second surface, the method further includes: A third dielectric support layer is formed within the second insulating layer between two adjacent, staggered second wiring layers; A third interconnect layer is formed on the third dielectric support layer, wherein the third interconnect layer is electrically connected to two adjacent second wiring layers that are staggered.

25. The preparation method according to claim 21, characterized in that, The support structure includes a first surface, and the first wiring structure is disposed on the first surface; the first interconnect layer and the first functional device are electrically connected at the same side as the first functional device; a ground layer is provided on the back of the first functional device; In the hollowed-out portion, and in forming a first interconnection structure between the support structure and the first functional device, the method further includes: A ground connection layer is formed on the surface of the first dielectric support layer on the side opposite to the first interconnect layer; Wherein, the projection of the first interconnect layer on the first surface overlaps with the projection of the ground connection layer on the first surface; the surface of the first dielectric support layer where the ground connection layer is provided is flush with the surface of the first functional device where the ground layer is provided, and the ground connection layer is electrically connected to the ground layer.

26. The preparation method according to claim 25, characterized in that, The support structure further includes a second surface, which is the surface of the support structure facing away from the first wiring structure; After the first wiring structure is formed on one side of the support structure, the following is also included: A multilayer second wiring layer and a second insulating layer located between two adjacent second wiring layers are sequentially formed on the second surface; In this configuration, along a direction perpendicular to the second surface, the connection points of the first layer of the second wiring layer and the first functional device are staggered. The first interconnect layer passes through the cutout and is electrically connected to the first layer of the second wiring layer. The first layer of the second wiring layer is the second wiring layer disposed on the second surface. The ground layer is disposed on the same layer as the first layer of the second wiring layer.

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