3c-sic / si / 3c-sic composite interposer and preparation and application thereof

Abstract

The application discloses a 3C-SiC / Si / 3C-SiC composite interposer and a preparation and application thereof, and comprises a lower 3C-SiC heat dissipation layer, a single crystal silicon substrate layer, an upper 3C-SiC heat dissipation layer and a metal wiring layer which are sequentially stacked; the lower 3C-SiC heat dissipation layer, the single crystal silicon substrate layer and the upper 3C-SiC heat dissipation layer are communicated through a longitudinally-through metal structure, and the metal structure is connected with the metal wiring layer; the 3C-SiC / Si / 3C-SiC composite interposer structure is adopted, 3C-SiC heat dissipation layers are arranged on both sides of the silicon substrate, the overall heat conduction capacity of the interposer can be improved, and therefore the heat management performance in high-power-density AI chip packaging can be improved.

Description

Technical Field

[0001] This invention relates to the field of SiC interposer technology, and more particularly to a 3C-SiC / Si / 3C-SiC composite interposer and its preparation and application. Background Technology

[0002] CoWoS (Chip-on-Wafer-on-Substrate) packaging technology is one of the important ways to improve the performance of AI high-computing-power chip systems. With the rapid growth in demand for AI computing power, the integration and power density of chips such as GPUs and AI accelerators continue to increase, and heat dissipation has become a key factor restricting the development of high-performance packaging. The interposer, as the core structure in CoWoS packaging, is mainly used to achieve high-density, high-speed interconnection between chips, while also undertaking a certain role in heat conduction and thermal stress buffering. Its material properties directly affect the heat dissipation capacity and reliability of the packaging system.

[0003] Currently, commonly used interposer materials include silicon, organic materials, glass, and ceramics. Among them, silicon interposers are widely used in high-performance computing packaging due to their mature technology, high wiring accuracy, and good dimensional stability. However, silicon has limited thermal conductivity, making it difficult to effectively dissipate the heat generated by the chip in a timely manner under high power density chip operating conditions. This can easily lead to localized heat accumulation, resulting in problems such as increased chip temperature, performance throttling, and decreased reliability, failing to meet the high-efficiency heat dissipation requirements of next-generation AI chips. In recent years, silicon carbide (SiC) materials have attracted attention due to their high thermal conductivity, excellent mechanical strength, and thermal stability. For example, the thermal conductivity of 4H-SiC single crystal material can reach approximately 490 W / (m·K), significantly higher than that of traditional silicon materials. Therefore, existing technologies have adopted 4H-SiC wafers to replace silicon interposers to improve the heat dissipation performance of CoWoS packaging structures. However, directly using 4H-SiC wafers as interposers still has significant shortcomings. First, 4H-SiC wafers are expensive, and their mass production size is mainly limited to 6-inch to 8-inch wafers, making it difficult to meet the large-size interposer requirements of CoWoS packaging. As GPU chip area and multi-chip integration scale continue to increase, the demand for interposer size also rises. Limited size reduces layout utilization and increases edge waste, thus driving up costs. Second, 4H-SiC has high hardness and is difficult to process; its cutting, thinning, grinding, and polishing processes are still immature. In particular, when thinning 4H-SiC wafers to approximately 100 μm, significant material loss and processing defects are easily generated, further increasing manufacturing costs and affecting yield.

[0004] Therefore, existing SiC interposer solutions still struggle to balance high heat dissipation performance, large size requirements, and large-scale low-cost manufacturing. Summary of the Invention

[0005] In view of this, this application provides a 3C-SiC / Si / 3C-SiC composite interposer layer and its preparation and application, in order to solve the problem of how to achieve SiC interposer while taking into account high heat dissipation performance and processing adaptability.

[0006] To achieve the above technical objectives, this application adopts the following technical solution: In a first aspect, this application discloses a 3C-SiC / Si / 3C-SiC composite interposer, comprising a lower 3C-SiC heat dissipation layer, a single-crystal silicon substrate layer, an upper 3C-SiC heat dissipation layer, and a metal wiring layer stacked sequentially; the lower 3C-SiC heat dissipation layer, the single-crystal silicon substrate layer, and the upper 3C-SiC heat dissipation layer are connected by a vertically penetrating metal structure, and the metal structure is connected to the metal wiring layer.

[0007] Preferably, the monocrystalline silicon is selected from <100> Crystal orientation <110> Crystal orientation or <111> Crystal-oriented silicon wafers; wafer sizes range from 6 to 18 inches.

[0008] Preferably, the thickness of both the lower and upper 3C-SiC heat dissipation layers is 20-50 μm; the thickness of the 3C-SiC / Si / 3C-SiC composite interlayer is 50-120 μm.

[0009] Preferably, the metal structure includes a first metal structure penetrating the upper 3C-SiC heat dissipation layer and a portion of the single-crystal silicon substrate layer, and a second metal structure penetrating the lower 3C-SiC heat dissipation layer and another portion of the single-crystal silicon substrate layer; the first metal structure and the second metal structure are electrically connected.

[0010] Secondly, this application provides a method for preparing a 3C-SiC / Si / 3C-SiC composite interposer, comprising the following steps: A 3C-SiC heat dissipation layer was epitaxially grown on one side surface of a single-crystal silicon substrate using chemical vapor deposition. A lower 3C-SiC heat dissipation layer was epitaxially grown on the other side surface of a single-crystal silicon substrate using chemical vapor deposition. A first via is formed in the upper 3C-SiC heat dissipation layer and part of the single crystal silicon substrate, and a first conductive structure is formed in the first via; a second via is formed in the lower 3C-SiC heat dissipation layer and another part of the single crystal silicon substrate, and a second conductive structure is formed in the second via; the first via and the second via are connected.

[0011] A metal wiring layer is formed on the surface of the upper 3C-SiC heat dissipation layer, and the metal wiring layer is connected to the first conductive structure.

[0012] Preferably, the first conductive structure is formed before the formation of the lower 3C-SiC heat dissipation layer, and the second conductive structure is completed after the formation of the lower 3C-SiC heat dissipation layer.

[0013] Preferably, both the first conductive structure and the second conductive structure are completed after the formation of the lower 3C-SiC heat dissipation layer.

[0014] Preferably, before epitaxially growing the upper 3C-SiC heat dissipation layer, the single crystal silicon substrate is further subjected to laser patterning; before epitaxially growing the lower 3C-SiC heat dissipation layer, the single crystal silicon substrate is further subjected to grinding and polishing.

[0015] Preferably, in steps S1 and S3, a carbonization treatment is included before chemical vapor deposition; the temperature of chemical vapor deposition is 1300℃-1350℃, the deposition pressure is 80-100 mbar, and the deposition time is 40-50 min; the temperature of carbonization treatment is 1000-1150℃, and the carbonization time is 10-15 min.

[0016] Secondly, this application provides a CoWoS packaging structure including a 3C-SiC / Si / 3C-SiC composite interposer, comprising an organic substrate, a 3C-SiC / Si / 3C-SiC composite interposer, and a device layer that are stacked sequentially and electrically connected; the metal wiring layer in the 3C-SiC / Si / 3C-SiC composite interposer is electrically connected to the device layer.

[0017] The beneficial effects of this application are as follows: Compared to existing solutions that directly use 4H-SiC wafers as the interposer, this invention employs a 3C-SiC / Si / 3C-SiC composite interposer structure. By placing 3C-SiC heat dissipation layers on both sides of the silicon substrate, the overall thermal conductivity of the interposer is improved, thereby enhancing thermal management performance in high-power-density AI chip packaging. Heat generated during chip operation is rapidly diffused through the upper 3C-SiC heat dissipation layer and further conducted to the organic carrier and external heat dissipation structures via the silicon intermediate layer and the lower 3C-SiC heat dissipation layer, reducing localized heat accumulation and improving the operational reliability of the CoWoS packaging structure.

[0018] This invention utilizes the characteristic that 3C-SiC can be directly epitaxially grown on silicon substrates, and can prepare composite interposers based on large-size silicon wafers. This is beneficial to meeting the demand for large-size interposers in CoWoS packaging, and reduces the dependence on large-size 4H-SiC wafers, thereby reducing material costs and edge waste. This invention prepares a 3C-SiC heat dissipation layer by chemical vapor deposition, which can precisely control the thickness of the heat dissipation layer and the overall thickness of the composite interposer. This avoids the large number of cutting, thinning, grinding and polishing processes required when directly using 4H-SiC wafers as the interposer, thereby reducing material loss, simplifying the manufacturing process and reducing costs.

[0019] This invention employs a double-sided 3C-SiC epitaxial structure, allowing for via and metal wiring processes to be performed from the front and back sides of the composite interposer layer, respectively. Compared to the integral SiC base interposer layer that requires forming through-hole high aspect ratio vias in a thick SiC material, this invention utilizes the upper and lower 3C-SiC layers as heat diffusion layers and the middle Si layer as the support and interconnect processing body. The Si via processing technology is mature and the thickness of the 3C-SiC layer is controllable, which can significantly reduce the difficulty of via processing and improve manufacturability and yield. Attached Figure Description

[0020] To more clearly illustrate the technical solution of this application, the accompanying drawings used in this application will be briefly described below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0021] Figure 1 This is a schematic diagram of a CoWoS packaging structure based on 4H-SiC wafers replacing silicon interposers. Figure 2 A schematic diagram of the structure of the 3C-SiC / Si / 3C-SiC composite interposer; Figure 3 XRD (a) and transmission electron microscopy (B) images of the interface of 3C-SiC / Si. Figure 4 This is a schematic diagram of the CoWoS packaging structure based on a 3C-SiC / Si / 3C-SiC interposer. Detailed Implementation

[0022] The embodiments of the technical solution of this application will be described in detail below. The following embodiments are only used to illustrate the technical solution of this application more clearly, and are therefore only examples, and should not be used to limit the scope of protection of this application.

[0023] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0026] Unless otherwise explicitly defined and specified herein, all technical and scientific terms used in this application shall have the generally accepted meanings understood by one of ordinary skill in the field of chemical and chemical materials technology (including but not limited to polymer chemistry, inorganic chemistry, organic synthesis, catalysis chemistry, materials processing, and chemical unit operations) based on their professional knowledge and conventional practice. The use of any terminology herein is intended to describe the specific embodiments of this application in the clearest and most accurate manner, so as to fully disclose the technical solution. Such use shall not in any way be construed as a limitation on the scope of the claims, nor does it imply the exclusion of equivalent technical solutions that could be reasonably known by one of skill in the art based on the concept of this application.

[0027] The terms "comprising," "including," "having," "containing," and any grammatical variations or similar expressions used in the specification and claims of this application are all open-ended and non-exhaustive descriptive terms. Their purpose is to explicitly describe the existence of technical features, components, steps, or parts, while explicitly allowing and covering the possibility that other features, components, steps, parts, or any combinations thereof not explicitly listed may exist or be added to the technical solution, as long as such additions do not destroy the integrity and inventiveness of the original technical solution.

[0028] When the terms "embodiments," "some embodiments," or "specific embodiments" are mentioned in the specification, they refer to examples that, in conjunction with the specific parameters, materials, steps, and results described in that section, constitute one or a group of examples for implementing the technical solutions of this application. These embodiments are used for full disclosure and illustrative purposes, not for exhaustive enumeration. Those skilled in the art should understand that, without departing from the overall inventive concept of this application, the various technical features disclosed in different embodiments can be combined, substituted, modified, or deleted to form other implementation methods that are not listed one by one in the specification but also fall within the protection scope of this application.

[0029] Unless otherwise expressly specified and limited, all terms related to chemical process operations, material preparation, processing and analytical testing involved in this application shall be interpreted in the broadest sense based on the conventional understanding of those skilled in the art.

[0030] Regarding performance testing and structural characterization, all testing and characterization methods involved in this application, unless otherwise specified, refer to conventional methods known in the art. Specific testing conditions may be selected and adjusted according to the sample properties and relevant national standards, international standards, or industry-standard methods. Test items may include mechanical properties (such as tensile, bending, and impact strength), thermal properties (such as DSC and TGA analysis), and chemical stability (such as solvent resistance and acid / alkali corrosion resistance). Structural characterization methods may include FT-IR, NMR, XRD, SEM, TEM, and BET. All test results should be understood to be within the allowable range of conventional experimental errors.

[0031] Regarding numerical values ​​and ranges, all parameter ranges expressed in this application in the form of "from a certain value to a certain value" should be understood as explicitly disclosing the endpoints of the range, each specific numerical point between the endpoints, and all sub-ranges formed by any two numerical points within the range. For example, "30℃ to 80℃" discloses 30, 31, ..., 80℃, as well as sub-ranges such as 30-50℃, 45-70℃, etc. When a numerical value is preceded by "about," "approximately," or similar words, it indicates that the numerical value is allowed to have reasonable errors recognized in the art under the measurement or control conditions, which can generally be understood as the deviation allowed by relevant standards or a normal fluctuation range of ±5% or ±10%.

[0032] This application provides a 3C-SiC / Si / 3C-SiC composite interposer, comprising a lower 3C-SiC heat dissipation layer, a single-crystal silicon substrate layer, and an upper 3C-SiC heat dissipation layer stacked sequentially, and a metal wiring layer disposed on the surface of the upper 3C-SiC heat dissipation layer; the lower 3C-SiC heat dissipation layer, the single-crystal silicon substrate layer, and the upper 3C-SiC heat dissipation layer are connected by a vertically penetrating metal structure, and the metal structure is connected to the metal wiring layer.

[0033] In this application, leveraging the characteristic that 3C-SiC can be directly epitaxially grown on a silicon substrate, 3C-SiC heat dissipation layers are formed on both the upper and lower surfaces of a single-crystal silicon substrate, thereby constructing a composite interposer layer with high thermal conductivity, good processing compatibility, and low manufacturing cost. Heat generated during chip operation is first transferred to the upper 3C-SiC heat dissipation layer closest to the device layer. Due to the high thermal conductivity of 3C-SiC, heat can rapidly diffuse within the upper 3C-SiC layer and further conduct through the single-crystal silicon substrate layer and the lower 3C-SiC heat dissipation layer to the organic carrier and external heat dissipation structure. Simultaneously, the metal structure in the composite interposer layer is used to realize electrical signal transmission between the device layer and the organic carrier, enabling the structure to simultaneously possess high-speed interconnection and efficient heat dissipation functions. Through the above structural design, the composite interposer layer retains the advantages of large silicon substrate size, mature technology, and relatively low cost, while utilizing double-sided 3C-SiC heat dissipation layers to improve the overall thermal conductivity of the interposer layer.

[0034] In some embodiments, single-crystal silicon is selected from <100> Crystal orientation <110> Crystal orientation or <111> Crystal-oriented silicon wafers; wafer sizes range from 6 to 18 inches.

[0035] In this embodiment, a single-crystal silicon substrate serves as the main support layer for the composite interposer. Using silicon wafers with different crystal orientations can meet the requirements for different epitaxial growth orientations, while the size range of 6 inches to 18 inches can meet the interposer area requirements of different sized CoWoS packaging structures.

[0036] In some embodiments, the thickness of both the lower and upper 3C-SiC heat dissipation layers is 20-50 μm; the thickness of the 3C-SiC / Si / 3C-SiC composite interposer is 50-120 μm.

[0037] In this embodiment, when a 3C-SiC heat dissipation layer is epitaxially grown on a single-crystal silicon substrate using chemical vapor deposition, the thickness of the heat dissipation layer can be precisely controlled by adjusting the deposition time, reaction temperature, reaction pressure, and reactant gas flow rate. The thickness of both the upper and lower 3C-SiC heat dissipation layers is controlled between 20 μm and 50 μm, and the overall thickness of the composite interposer is controlled between 50 μm and 120 μm. This ensures that the composite interposer has sufficient thermal conductivity while avoiding excessive overall thickness that could affect the package integration.

[0038] In some embodiments, the metal structure includes a first metal penetrating the upper 3C-SiC heat dissipation layer and a portion of the single-crystal silicon substrate layer, and a second metal penetrating the lower 3C-SiC heat dissipation layer and another portion of the single-crystal silicon substrate layer; the first metal and the second metal are electrically connected.

[0039] In this embodiment, a metal structure is formed by creating through-holes on both sides and filling them with metal. Compared to machining deep through-holes on one side, this reduces the difficulty of machining through-holes with high aspect ratios, and improves manufacturability and yield. After the first metal and the second metal are electrically connected, a vertical interconnect path is formed between the device layer and the organic substrate. The metal material filling the through-holes can be selected from tungsten, molybdenum, tantalum, titanium, titanium nitride, tungsten / titanium nitride composite structures, or other conductive materials that can withstand the subsequent 3C-SiC epitaxial temperature, in order to solve the problem of high-temperature compatibility of the metal.

[0040] In some embodiments, a metal wiring layer is also provided on the surface of the lower 3C-SiC heat dissipation layer.

[0041] In this embodiment, the metal wiring layer on the surface of the lower 3C-SiC heat dissipation layer is used for electrical connection to the organic carrier board.

[0042] This application provides a method for preparing a 3C-SiC / Si / 3C-SiC composite interposer, comprising the following steps: A 3C-SiC heat dissipation layer was epitaxially grown on one side surface of a single-crystal silicon substrate using chemical vapor deposition. A lower 3C-SiC heat dissipation layer was epitaxially grown on the other side surface of a single-crystal silicon substrate using chemical vapor deposition. A first via is formed in the upper 3C-SiC heat dissipation layer and part of the single crystal silicon substrate, and a first conductive structure is formed in the first via; a second via is formed in the lower 3C-SiC heat dissipation layer and another part of the single crystal silicon substrate, and a second conductive structure is formed in the second via; the first via and the second via are connected. A metal wiring layer is formed on the surface of the upper 3C-SiC heat dissipation layer, and the metal wiring layer is connected to the first conductive structure.

[0043] This application employs a double-sided 3C-SiC epitaxial structure, allowing for via and metal wiring processes to be performed from both the front and back sides of the composite interposer. Compared to single-sided deep via processing, this reduces the difficulty of processing high aspect ratio vias, improving manufacturability and yield. Simultaneously, the 3C-SiC heat dissipation layer is prepared using chemical vapor deposition, enabling precise control of its thickness. This avoids the extensive cutting, thinning, grinding, and polishing processes required when directly using 4H-SiC wafers as the interposer, thereby reducing material waste, simplifying the manufacturing process, and lowering costs. Heat generated during chip operation is rapidly diffused through the upper 3C-SiC heat dissipation layer and further conducted to the outside via the single-crystal silicon substrate and the lower 3C-SiC heat dissipation layer, achieving efficient heat dissipation.

[0044] In some embodiments, the first conductive structure is formed before the formation of the lower 3C-SiC heat dissipation layer, and the second conductive structure is completed after the formation of the lower 3C-SiC heat dissipation layer.

[0045] In this embodiment, the specific preparation steps are as follows: S1. A 3C-SiC heat dissipation layer is epitaxially grown on one side of a single-crystal silicon substrate using chemical vapor deposition. S2. A first through-hole is formed, penetrating the upper 3C-SiC heat dissipation layer and part of the single crystal silicon substrate, and filled with a first metal as a first conductive structure; S3. A lower 3C-SiC heat dissipation layer is epitaxially grown on the other side of a single-crystal silicon substrate using chemical vapor deposition. S4. A second through-hole is opened, penetrating the lower 3C-SiC heat dissipation layer and another part of the single crystal silicon substrate, and filled with a second metal as a second conductive structure; the first through-hole is connected to the second through-hole.

[0046] In this method, because the first conductive structure needs to withstand the high-temperature environment during the subsequent epitaxial growth of the lower 3C-SiC layer, the metal material filling the vias is selected from tungsten, molybdenum, tantalum, titanium, titanium nitride, tungsten / titanium nitride composite structures, or other conductive materials that can withstand the temperature of the subsequent 3C-SiC epitaxial growth. After the front via and metal wiring processes are completed, the back side of the Si substrate is ground and polished to control the Si substrate thickness to 50μm to 100μm, ensuring that the formed first via structure meets the requirements for subsequent electrical connections. Subsequently, the lower 3C-SiC heat dissipation layer is epitaxially grown on the back side of the Si substrate using chemical vapor deposition, with the epitaxial growth conditions being the same as the upper 3C-SiC heat dissipation layer. In the back via and metal wiring processes, a metal connection structure is formed on the surface of the lower 3C-SiC heat dissipation layer for connection with the organic carrier.

[0047] In some embodiments, both the first conductive structure and the second conductive structure are completed after the formation of the lower 3C-SiC heat dissipation layer.

[0048] In this embodiment, the specific preparation steps are as follows: S1. A 3C-SiC heat dissipation layer is epitaxially grown on one side of a single-crystal silicon substrate using chemical vapor deposition. S2. After the upper 3C-SiC heat dissipation layer is formed, only through-hole openings or blind holes are prefabricated; S3. A lower 3C-SiC heat dissipation layer is epitaxially grown on the other side of a single-crystal silicon substrate using chemical vapor deposition. S4. After the back side is thinned and the lower 3C-SiC heat dissipation layer is grown, the through-hole is connected, the insulating layer is deposited, the barrier layer is deposited and the metal is filled from the front and back sides respectively, so that the first through-hole is connected to the second through-hole.

[0049] This method involves first growing double-sided 3C-SiC, followed by metal filling. After the upper 3C-SiC heat dissipation layer is formed, only via openings or blind vias are pre-fabricated. After the back side is thinned and the lower 3C-SiC heat dissipation layer is grown, via penetration, insulating layer deposition, barrier layer deposition, and metal filling are performed from the front and back sides respectively. Since all conductive structures are formed after the epitaxial growth of the two 3C-SiC layers, there is no need to withstand the high-temperature epitaxial environment. Therefore, the metal material filling the vias can be a highly conductive material such as copper, reducing resistance and improving signal transmission speed. The back side of the Si substrate is ground and polished to control the Si substrate thickness to 50μm to 100μm. Finally, metal wiring layers and metal connection structures are formed on the front and back sides respectively for connection with device layers and organic substrates.

[0050] In some embodiments, before epitaxially growing the upper 3C-SiC heat dissipation layer, the single-crystal silicon substrate is further subjected to laser patterning.

[0051] In this embodiment, laser patterning can form microstructure patterns on the surface of a single-crystal silicon substrate, increasing the specific surface area, which is beneficial to the nucleation density during subsequent 3C-SiC epitaxial growth, improving the bonding strength between the 3C-SiC heat dissipation layer and the single-crystal silicon substrate, and improving the interfacial thermal conductivity.

[0052] In some embodiments, before epitaxially growing the lower 3C-SiC heat dissipation layer, the single-crystal silicon substrate is further subjected to grinding and polishing.

[0053] In this embodiment, the back side of the single-crystal silicon substrate is ground and polished to control the thickness of the silicon substrate to 50μm to 100μm. On the one hand, the overall thickness of the thinned composite interposer is more suitable for the CoWoS packaging structure. On the other hand, the back side polishing process is beneficial to the epitaxial growth quality of the subsequent 3C-SiC heat dissipation layer and ensures that the formed first through-hole structure meets the subsequent electrical connection requirements.

[0054] In some embodiments, a carbonization process is also included prior to chemical vapor deposition.

[0055] In this embodiment, the carbonization process forms an extremely thin SiC buffer layer on the surface of the single-crystal silicon substrate. This buffer layer can effectively reduce the interfacial stress between 3C-SiC and silicon caused by lattice mismatch and the difference in thermal expansion coefficient during subsequent high-temperature epitaxial growth, thereby improving the epitaxial growth quality and obtaining a 3C-SiC heat dissipation layer with good crystal quality.

[0056] In some embodiments, during chemical vapor deposition, the deposition temperature is 1300℃-1350℃, the deposition pressure is 80-100 mbar, and the deposition time is 40-50 min.

[0057] In this embodiment, a high growth rate and good crystal quality can be obtained within the above-mentioned deposition temperature, pressure, and time range. When trichlorosilane is used as the silicon source and ethylene as the carbon source, the silicon and carbon sources decompose sufficiently within this temperature range, and the epitaxial growth is controllable. This allows for precise control of the thickness of the monolayer 3C-SiC heat dissipation layer within the range of 20μm to 50μm, while ensuring that the density and thermal conductivity of the heat dissipation layer meet the heat dissipation requirements.

[0058] This application provides a CoWoS packaging structure including a 3C-SiC / Si / 3C-SiC composite interposer, comprising an organic substrate, a 3C-SiC / Si / 3C-SiC composite interposer, and a device layer stacked sequentially and electrically connected. A metal wiring layer is disposed in the composite interposer and is electrically connected to the device layer.

[0059] In this embodiment, the CoWoS packaging structure applies the aforementioned 3C-SiC / Si / 3C-SiC composite interposer between the device layer and the organic substrate. The device layer may include GPUs, AI accelerator chips, HBM memory chips, or other functional chips. A metal wiring layer is fabricated on the upper 3C-SiC heat dissipation layer to enable electrical connection with the chips in the device layer and achieve high-density interconnection between chips. The organic substrate is used to realize the electrical connection between the packaging structure and external circuit systems. While providing high-speed interconnection between chips, the composite interposer also rapidly diffuses and conducts heat generated during chip operation from the front and back sides of the composite interposer through the double-sided 3C-SiC heat dissipation layer, improving the thermal management performance in high-power-density AI chip packaging. Furthermore, the characteristic that 3C-SiC can be directly epitaxially grown on silicon substrates allows the composite interposer to be fabricated based on large-size silicon wafers, which is beneficial for meeting the CoWoS packaging's requirement for large-size interposers and reducing dependence on large-size 4H-SiC wafers.

[0060] The following specific embodiments further illustrate this solution.

[0061] Example 1 A 3C-SiC / Si / 3C-SiC composite interposer includes a lower 3C-SiC heat dissipation layer, a monocrystalline silicon substrate layer, an upper 3C-SiC heat dissipation layer, and a metal wiring layer disposed on the surface of the upper 3C-SiC heat dissipation layer, which are stacked sequentially. The lower 3C-SiC heat dissipation layer, the monocrystalline silicon substrate layer, and the upper 3C-SiC heat dissipation layer are connected by a longitudinally penetrating metal structure, which is connected to the metal wiring layer.

[0062] like Figure 2 As shown, the preparation method of the 3C-SiC / Si / 3C-SiC composite interposer includes the following steps: S1. 6 inches <100> A oriented monocrystalline silicon substrate was laser-patterned to construct a spatially periodic growth template. A 3C-SiC heat dissipation layer was then epitaxially grown on one side of the substrate using chemical vapor deposition (CVD). Ethylene was used as the carbon source at a flow rate of 10 sccm. The substrate was first carbonized at 1150℃ for 10 minutes, with ethylene introduced during carbonization but not trichlorosilane. After carbonization, trichlorosilane was used as the silicon source, introduced into the process chamber via H2 bubbling at a flow rate of 20 sccm, while ethylene continued to be introduced, raising the deposition temperature to 1350℃. Deposition was carried out for 40 minutes at a deposition pressure of 100 mbar. The resulting 3C-SiC heat dissipation layer had a thickness of 40 μm. The XRD pattern and interface microstructure of the 3C-SiC heat dissipation layer are shown below. Figure 3 As shown, the 3C-SiC layer has good crystal quality; S2. Through-hole processing is performed on the obtained structure to form a first through-hole in the upper 3C-SiC heat dissipation layer and part of the single crystal silicon substrate. Then, tungsten is filled in the first through-hole as the first conductive structure. Then, metal wiring layer is prepared on the upper 3C-SiC heat dissipation layer so that it can be electrically connected to the chip in the device layer and realize high-density interconnection between chips. S3. Grind and polish the back side (other side) of the Si substrate to control the thickness of the Si substrate to more than 50 μm, and ensure that the formed first through-hole structure meets the requirements of the subsequent electrical connection of the second through-hole structure. Then, grow the lower 3C-SiC heat dissipation layer on the back side of the Si substrate by chemical vapor deposition. The epitaxial growth conditions of the back 3C-SiC heat dissipation layer are the same as those of the upper 3C-SiC heat dissipation layer, so as to obtain a 3C-SiC / Si / 3C-SiC composite layer with 3C-SiC heat dissipation layer on both sides. S4. Through-hole processing is performed on the back side of the composite layer to open a second through-hole that penetrates the lower 3C-SiC heat dissipation layer and fills it with tungsten as a second conductive structure, so that the filling metal in the second through-hole is connected to the filling metal in the first through-hole, thereby forming a 3C-SiC / Si / 3C-SiC composite interposer structure that can realize vertical interconnection between the device layer and the organic substrate.

[0063] Example 2 A 3C-SiC / Si / 3C-SiC composite interposer includes a lower 3C-SiC heat dissipation layer, a monocrystalline silicon substrate layer, an upper 3C-SiC heat dissipation layer, and a metal wiring layer disposed on the surface of the upper 3C-SiC heat dissipation layer, which are stacked sequentially. The lower 3C-SiC heat dissipation layer, the monocrystalline silicon substrate layer, and the upper 3C-SiC heat dissipation layer are connected by a longitudinally penetrating metal structure, which is connected to the metal wiring layer.

[0064] The method for preparing a 3C-SiC / Si / 3C-SiC composite interposer includes the following steps: S1. 6 inches <100> A single-crystal silicon substrate was laser-patterned to construct a growth template with spatial periodicity. A 3C-SiC heat dissipation layer was epitaxially grown on one side of the treated substrate using chemical vapor deposition (CVD). Ethylene was used as the carbon source at a flow rate of 10 sccm. The substrate was first carbonized at 1150℃ for 10 minutes, with ethylene introduced during the carbonization process but not trichlorosilane. After carbonization, trichlorosilane was used as the silicon source, introduced into the process chamber via H2 bubbling at a flow rate of 20 sccm, while ethylene was continuously introduced, raising the deposition temperature to 1350℃. Deposition was carried out for 40 minutes at a deposition pressure of 100 mbar, resulting in an upper 3C-SiC heat dissipation layer with a thickness of 40 μm. A metal wiring layer was then fabricated on the upper 3C-SiC heat dissipation layer to enable electrical connection with the chips in the device layer and achieve high-density interconnection between chips. S2. After the upper 3C-SiC heat dissipation layer is formed, only through-hole openings or blind holes are prefabricated, and metal filling is not carried out for the time being; S3. Grind and polish the back side of the Si substrate to control the thickness of the Si substrate to more than 50 μm. Then, grow the lower 3C-SiC heat dissipation layer on the back side of the Si substrate by chemical vapor deposition. The epitaxial growth conditions of the lower 3C-SiC heat dissipation layer are the same as those of the upper 3C-SiC heat dissipation layer. S4. After the lower 3C-SiC heat dissipation layer is grown, the via penetration, insulating layer deposition, barrier layer deposition, and metal filling are completed from the front and back sides respectively. Specifically, on the front side, the via openings or blind holes prefabricated in S2 are further penetrated to form a first via penetrating the upper 3C-SiC heat dissipation layer and part of the single-crystal silicon substrate, and filled with metal to form a first conductive structure; on the back side, a second via penetrating the lower 3C-SiC heat dissipation layer and another part of the single-crystal silicon substrate is opened and filled with metal to form a second conductive structure; the first via and the second via are connected to each other, so that the first conductive structure and the second conductive structure are electrically connected, thereby forming a 3C-SiC / Si / 3C-SiC composite interposer structure that can realize vertical interconnection between the device layer and the organic substrate.

[0065] Example 3 A 3C-SiC / Si / 3C-SiC composite interposer is provided, which is otherwise the same as in Example 1, except that a metal wiring layer is also provided on the surface of the lower 3C-SiC heat dissipation layer.

[0066] Example 4 like Figure 4As shown, a CoWoS packaging structure including a 3C-SiC / Si / 3C-SiC composite interposer layer includes, from bottom to top, a carrier board, a 3C-SiC / Si / 3C-SiC composite interposer layer, and a device layer; a lower 3C-SiC heat dissipation layer, a single-crystal silicon substrate layer, and an upper 3C-SiC... The heat dissipation layer is connected by a vertically penetrating metal structure, which is connected to the metal wiring layer, forming a vertical interconnect path between the organic substrate, the 3C-SiC / Si / 3C-SiC composite interposer, and the device layer. The device layer is disposed above the composite interposer, and the organic substrate is disposed below the composite interposer. The 3C-SiC / Si / 3C-SiC composite interposer includes a single-crystal silicon substrate in the middle, an upper 3C-SiC heat dissipation layer disposed on the upper surface of the single-crystal silicon substrate, and a lower 3C-SiC heat dissipation layer disposed on the lower surface of the single-crystal silicon substrate. The metal wiring layer is disposed on the surface of the upper 3C-SiC heat dissipation layer for electrical connection with the chips in the device layer and to achieve high-density interconnection between chips. The lower 3C-SiC heat dissipation layer is connected to the organic substrate through another metal wiring layer. The device layer includes GPU, AI accelerator chips, HBM memory chips, or other functional chips. The organic substrate is used to realize the electrical connection between the packaging structure and the external circuit system.

[0067] When the chip operates, the heat generated is first transferred to the upper 3C-SiC heat dissipation layer near the device layer. Due to the high thermal conductivity of 3C-SiC, the heat can diffuse rapidly within the upper 3C-SiC layer and further conduct to the organic substrate and external heat dissipation structure via the single-crystal silicon substrate and the lower 3C-SiC heat dissipation layer. The upper and lower 3C-SiC heat dissipation layers are used to diffuse the heat generated during chip operation along the front and back sides of the composite interposer, respectively. Simultaneously, the first via, the second via, and the metal wiring layer in the composite interposer layer are used to enable electrical signal transmission between the device layer and the organic substrate, giving this packaging structure both high-speed interconnection and efficient heat dissipation capabilities.

[0068] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A 3C-SiC / Si / 3C-SiC composite interposer, characterized in that, It includes a lower 3C-SiC heat dissipation layer, a single crystal silicon substrate layer, an upper 3C-SiC heat dissipation layer, and a metal wiring layer stacked sequentially; the lower 3C-SiC heat dissipation layer, the single crystal silicon substrate layer, and the upper 3C-SiC heat dissipation layer are connected by a vertically penetrating metal structure, and the metal structure is connected to the metal wiring layer.

2. The 3C-SiC / Si / 3C-SiC composite interposer according to claim 1, characterized in that, The single-crystal silicon is selected from <100> Crystal orientation <110> Crystal orientation or <111> Crystal-oriented silicon wafers; the silicon wafers are 6-18 inches in size.

3. The 3C-SiC / Si / 3C-SiC composite interposer according to claim 1, characterized in that, The thickness of both the lower and upper 3C-SiC heat dissipation layers is 20-50 μm; the thickness of the 3C-SiC / Si / 3C-SiC composite interposer layer is 50-120 μm.

4. The 3C-SiC / Si / 3C-SiC composite interposer according to claim 1, characterized in that, The metal structure includes a first metal structure penetrating the upper 3C-SiC heat dissipation layer and a portion of the single-crystal silicon substrate layer, and a second metal structure penetrating the lower 3C-SiC heat dissipation layer and another portion of the single-crystal silicon substrate layer; the first metal structure and the second metal structure are electrically connected.

5. A method for preparing a 3C-SiC / Si / 3C-SiC composite interposer as described in any one of claims 1-4, characterized in that, Includes the following steps: A 3C-SiC heat dissipation layer was epitaxially grown on one side surface of a single-crystal silicon substrate using chemical vapor deposition. A lower 3C-SiC heat dissipation layer was epitaxially grown on the other side surface of a single-crystal silicon substrate using chemical vapor deposition. A first through-hole is formed in the upper 3C-SiC heat dissipation layer and a portion of the single-crystal silicon substrate, and a first conductive structure is formed in the first through-hole; a second through-hole is formed in the lower 3C-SiC heat dissipation layer and another portion of the single-crystal silicon substrate, and a second conductive structure is formed in the second through-hole; the first through-hole and the second through-hole are connected. A metal wiring layer is formed on the surface of the upper 3C-SiC heat dissipation layer, and the metal wiring layer is connected to the first conductive structure.

6. The method according to claim 5, characterized in that, The first conductive structure is formed before the formation of the lower 3C-SiC heat dissipation layer, and the second conductive structure is completed after the formation of the lower 3C-SiC heat dissipation layer.

7. The method according to claim 5, characterized in that, Both the first conductive structure and the second conductive structure are completed after the lower 3C-SiC heat dissipation layer is formed.

8. The method according to claim 5, characterized in that, Before epitaxially growing the upper 3C-SiC heat dissipation layer, the single-crystal silicon substrate is subjected to laser patterning; before epitaxially growing the lower 3C-SiC heat dissipation layer, the single-crystal silicon substrate is subjected to grinding and polishing.

9. The method according to claim 4, characterized in that, In steps S1 and S3, a carbonization treatment is included before the chemical vapor deposition; the temperature of the chemical vapor deposition is 1300℃-1350℃, the deposition pressure is 80-100 mbar, and the deposition time is 40-50 min; the temperature of the carbonization treatment is 1000-1150℃, and the carbonization time is 10-15 min.

10. A CoWoS packaging structure comprising a 3C-SiC / Si / 3C-SiC composite interposer as described in any one of claims 1-3, characterized in that, It includes an organic carrier board, a 3C-SiC / Si / 3C-SiC composite interposer, and a device layer that are stacked sequentially and electrically connected; the metal wiring layer in the 3C-SiC / Si / 3C-SiC composite interposer is electrically connected to the device layer.

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