Guided limited eutectic interconnect structure and eutectic interconnect method

Abstract

The application discloses a guided limited eutectic interconnection structure, comprising a plurality of hollow isolation sleeves prepared from poly-alpha-methylstyrene, and the two ends of the hollow isolation sleeves are sleeved into a PD pad and a TIA pad respectively; in the eutectic reaction stage of the chip, the chip is heated to above the eutectic temperature, after reaching the eutectic temperature, the TIA pad and the PD pad are completely melted, while the hollow isolation sleeve is not melted, the hollow isolation sleeve wraps the TIA pad and the PD pad, and the IMC is formed in the hollow isolation sleeve; after heating to the degradation temperature of the hollow isolation sleeve, the hollow isolation sleeve is completely degraded. The application further provides a guided limited eutectic interconnection method of a PD chip and a TIA chip. The application has the advantages that the structure of "guiding type, sacrificial type and clean thermal decomposition polymer as isolation wall" is innovatively provided, the solder point forming is changed from free flow to limited area, and the isolation wall is a clean thermal decomposition material.

Description

Technical Field

[0001] This invention relates to a guided confined eutectic interconnect structure and a eutectic interconnect method. Background Technology

[0002] To address the optical interconnect requirements of AI and data centers for 1.6T high-speed optical modules, the receiver integrates a photodetector (PD) flip-chip onto a transimpedance amplifier (TIA). This effectively shortens the electrical path, reduces parasitic effects, improves heat dissipation, and facilitates integration. However, traditional eutectic interconnects face significant challenges. 1. Performance Bottleneck: Each channel between the PD and TIA requires independent signal, power, and ground connections. The parasitic inductance introduced by the pads, along with the detector's own junction capacitance, forms a low-pass filter, limiting bandwidth.

[0003] 2. Alignment and packaging complexity: The precise alignment and bonding process between PD and TIA is complex, costly, and difficult to guarantee consistency. Traditional pick-and-place and reflow processes and eutectic processes have low alignment accuracy, efficiency, and yield.

[0004] 3. Thermo-mechanical reliability crisis: Traditional eutectic solder layers are prone to generating huge shear stress during temperature cycling, which can lead to solder layer cracking, chip warping, and long-term temperature cycling may cause over-soldering, resulting in brittle IMC (intermetallic compound).

[0005] 4. Existing technologies attempt to improve the system by optimizing solder composition, but none of them fundamentally reconstruct the interconnect system, making it difficult to simultaneously meet the triple limits of performance, alignment accuracy, and reliability required by the 1.6T system. Summary of the Invention

[0006] The primary objective of this invention is to propose a guided confined eutectic interconnect structure. This structure utilizes a unique guided, sacrificial polymer hollow isolation sleeve. The hollow isolation sleeve degrades near the eutectic point (i.e., the main product is gas, with no ash residue). The hollow isolation sleeve enables precise control over the flow and formation of the eutectic solder. Simultaneously, the surface tension generated by the molten solder achieves liquid self-alignment between chips, in-situ stress leveling, and the formation of highly consistent columnar or frustum-shaped IMCs.

[0007] The specific technical solutions adopted are as follows: A guided confined eutectic interconnect structure includes several sacrificial hollow isolation sleeves made of poly-α-methylstyrene. The two ends of the hollow isolation sleeves are respectively fitted into PD pads on a photodetector chip and TIA pads on a transimpedance amplifier chip. During the eutectic reaction stage of the chip, the chip is heated to above the eutectic temperature. After reaching the eutectic temperature, the TIA pads and PD pads completely melt, while the hollow isolation sleeves do not melt. The hollow isolation sleeves enclose the TIA pads and PD pads, forming an IMC within the hollow isolation sleeves. After further heating to the hollow isolation sleeve degradation temperature, the hollow isolation sleeves degrade completely.

[0008] A further optimization of the technical solution of the present invention involves interconnecting several hollow isolation sleeves to form a sacrificial isolation wall.

[0009] In a further preferred embodiment of the technical solution of the present invention, the hollow isolation sleeves are connected by an interconnecting frame, which is made of poly-α-methylstyrene.

[0010] In a further preferred embodiment of the technical solution of the present invention, the height of the hollow isolation sleeve is equal to the sum of the height of the PD pad and the height of the TIA pad.

[0011] The second objective of this invention is to propose a guided confined eutectic interconnect method for PD chips and TIA chips, which achieves ultra-low parasitic capacitance, self-alignment, and high reliability eutectic interconnect between PD chips and TIA chips.

[0012] The specific technical solutions adopted are as follows: A guided confined eutectic interconnect method for a PD chip and a TIA chip includes the following steps: S1. Prepare a sacrificial isolation wall; S2. The isolation wall is installed on the TIA pad on the TIA chip side; S3. Pick up the PD chip and place it on the isolation wall, guide the PD pads to fall into the inner diameter of the hollow isolation sleeve one by one, and apply slight contact pressure. S4. Place the mounted chip pair into a controlled atmosphere reflow oven, execute a precise temperature profile, and a eutectic reaction occurs, forming an IMC between the TIA pad and the PD pad; at the same time, the isolation wall is completely degraded. S5, chip cooling and molding.

[0013] A further preferred embodiment of the technical solution of the present invention, the preparation steps of S1 are as follows: S11. Temporary carrier preparation: Quartz or borosilicate glass is selected as the carrier and is cleaned and dried. S12. Prepare an anti-adhesion layer on the carrier; spin-coat a 100-200 nm polytetrafluoroethylene (PTFE) thin film coating on the carrier to obtain the anti-adhesion layer; S13. Prepare polyα-methylstyrene solution: Select polyα-methylstyrene powder with a molecular weight of 100,000 to 500,000 Daltons and add it to tetrahydrofuran at a concentration of 10 to 30 wt%. Complete the preparation of polyα-methylstyrene solution in a stirrer. S14. Spin coating to form a film, which is completed in a spin coater; S15, Baking; S16. Photolithography and development to prepare the isolation wall; S17. Laser demolding and transfer are used to obtain the isolation wall of the required height.

[0014] A further preferred embodiment of the technical solution of the present invention is that the specific method of S15 is to bake at 95°C for 60 seconds in a hot plate or oven.

[0015] A further optimization of the technical solution of the present invention, the specific method of S4 is as follows: S41, First stage: Preheating; Increase the temperature to the first plateau temperature of 180°C at a rate of 5-10°C / s, and hold for 3-5 seconds; S42, Second Stage: Heat Preservation; Heat to 220℃ and hold for 5 seconds; S43, Third stage: Eutectic reaction occurs and self-alignment occurs; the temperature is rapidly increased to above the eutectic temperature. After reaching the eutectic temperature, the TIA pads and PD pads completely melt, while the isolation wall does not melt. The hollow isolation sleeve wraps around the TIA pads and PD pads, forming IMC inside the hollow isolation sleeve; after the temperature is increased again to the isolation wall degradation temperature, the isolation wall is completely degraded.

[0016] In a further preferred embodiment of the technical solution of the present invention, the temperature range of the third stage is 260℃~320℃.

[0017] In a further optimization of the technical solution of the present invention, in the third stage, the controllable atmosphere reflux furnace is rapidly heated to 220°C.

[0018] The advantages of this invention compared to the prior art are as follows: 1. The present invention provides a guided confined eutectic interconnect structure, which innovatively proposes a structure of "guided, sacrificial, clean thermally degradable polymer (poly-α-methylstyrene) to prepare the isolation wall", which changes the solder joint forming from free flow to confinement (using the internal space of the hollow isolation sleeve to confine the area); and the isolation wall is a clean thermally decomposable material (i.e. the main product is gas, with no ash residue).

[0019] 2. The present invention provides a guided confined eutectic interconnect structure, which realizes "liquid self-alignment" based on the surface tension of molten alloy, greatly reducing the alignment threshold of high-density integration of vision systems and significantly improving production yield and efficiency.

[0020] 3. The present invention provides a guided confined eutectic interconnection method for PD chips and TIA chips, which introduces sacrificial isolation walls, makes the solder joint shape controllable, reduces parasitic capacitance and inductance, and improves bandwidth performance and mechanical reliability.

[0021] 4. The present invention provides a guided confined eutectic interconnection method for PD chips and TIA chips, which provides a complete set of processes from material selection to eutectic process control to ensure the harmonious decomposition of sacrificial polymer isolation walls and eutectic reaction. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the isolation wall of the present invention; Figure 2 This is a top view schematic diagram of the layout of the guided confined eutectic interconnect structure of the present invention; Figure 3 This is a cross-sectional view of the PD chip placed on the isolation wall; Figure 4 This is a cross-sectional view of the eutectic reaction occurring in an embodiment of the present invention; Figure 5 This is a cross-sectional view of the isolation wall after degradation according to an embodiment of the present invention; Among them, 1. TIA chip, 2. PD chip, 3. interconnect frame of hollow isolation sleeve, 4. isolation wall, 5. lens on PD, 6. PD pad, 7. TIA pad, 8. IMC. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the following description is provided in conjunction with the appendix. Figures 1-3 The present invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] This embodiment is an innovative eutectic interconnect structure and method. It uses a unique guided hollow isolation sleeve (with the two ends of the hollow isolation sleeve respectively fitted into the PD pad on the photodetector chip and the TIA pad on the transimpedance amplifier chip) to create a sacrificial hollow isolation sleeve (made of poly-α-methylstyrene). The hollow isolation sleeve is made of a material that can undergo clean thermal decomposition near the eutectic point (i.e., the main product is gas with no ash residue). The hollow isolation sleeve enables precise control over the flow and formation of the eutectic solder (after reaching the eutectic temperature, the TIA and PD pads completely melt, while the isolation wall remains unmelted; the hollow isolation sleeve encloses the TIA and PD pads, forming an IMC within the sleeve). Simultaneously, the surface tension generated by the molten solder achieves liquid self-alignment between the chips (the molten TIA and PD pads are enclosed by the hollow isolation sleeve), and in-situ stress leveling (forming an IMC within the sleeve), resulting in a uniformly high columnar or frustum-shaped IMC. This achieves ultra-low parasitic capacitance, self-alignment, and highly reliable eutectic interconnect between the PD and TIA chips.

[0025] like Figure 1 As shown, a guided confined eutectic interconnect structure includes several sacrificial hollow isolation sleeves 41 made of poly-α-methylstyrene. The two ends of the hollow isolation sleeves 41 are respectively fitted into PD pads 6 on a photodetector chip and TIA pads 7 on a transimpedance amplifier chip. During the eutectic reaction stage of the chip, the chip is heated to above the eutectic temperature. After reaching the eutectic temperature, the TIA pads and PD pads completely melt, while the isolation wall does not melt. The hollow isolation sleeves wrap around the TIA pads and PD pads, forming an IMC inside the hollow isolation sleeves. After heating to the hollow isolation sleeve degradation temperature, the hollow isolation sleeves degrade completely.

[0026] Furthermore, an IMC is formed inside the hollow isolation sleeve, appearing as columnar solder joints; this improves high-frequency performance (ultra-low capacitance and inductance), specifically: 1) Capacitance control: The solder joint size is precisely limited by the hollow isolation sleeve, which eliminates the capacitance fluctuation caused by the uncontrollable spread of solder in the traditional process. Parasitic capacitance can be reduced by 1 / 3 and the consistency is good.

[0027] 2) Inductance optimization: The columnar solder joints provide a shorter vertical current path, reducing loop inductance.

[0028] like Figure 1As shown, the hollow isolation sleeve is made of poly(α-methylstyrene) (PAMS). As is known to those skilled in the art, PAMS is a clean raw material that does not produce liquid, only volatilizes. PAMS degrades at 260-320°C, and degradation is nearly complete at 300°C, leaving no residue. The eutectic temperature of the TIA and PD pads is around 280°C, which is also the eutectic temperature of Au-Sn. Therefore, during the eutectic reaction stage of the chip, the chip temperature first reaches the Au-Sn eutectic reaction temperature. At this point, the TIA and PD pads completely melt, while the hollow isolation sleeve remains unmelted. The hollow isolation sleeve encloses the TIA and PD pads, and the unmelted hollow isolation sleeve acts as a confined space, strictly limiting the liquid solder within the pre-defined cylindrical space, preventing lateral spread. Furthermore, the unmelted hollow isolation sleeve also serves as a liquid self-alignment mechanism. The extremely high surface tension of the molten solder generates a powerful capillary force, automatically pulling the exposed wettable metal layer (Au) on the PD chip towards and positioning it at the center of the confined space (hollow isolation sleeve), achieving micron-level precision self-alignment. Once the temperature reaches the degradation temperature of the hollow isolation sleeve, the sleeve completely degrades; a clean thermal decomposition occurs, leaving no ash residue.

[0029] Furthermore, a guided confined eutectic interconnect structure possesses revolutionary process tolerance and self-alignment capability, specifically as follows: 1) "Liquid eye" alignment: It utilizes the high surface tension of molten solder to achieve micron-level precision self-alignment. Relying on in-situ stress leveling, it relaxes the precision requirements of chip mounting from submicron to several micron, significantly improving production yield and efficiency.

[0030] 2) Controllable morphology: The final shape of the weld joint is determined by the hollow isolation sleeve, rather than the randomness of liquid flow, resulting in extremely high process repeatability.

[0031] 3) Excellent thermomechanical reliability: The space inside the hollow isolation sleeve forms columnar weld points, which greatly improves the overall mechanical stability, shear resistance and fatigue resistance of the columnar weld points.

[0032] 4) Hollow isolation sleeves are materials that can undergo clean thermal decomposition near the eutectic point (i.e., the main product is gas with no ash residue).

[0033] 4) Suitable for ultra-high density integration: This architecture clears the interconnect technology barriers for future ultra-high channel count integration at speeds of 3.2T and above.

[0034] like Figure 1As shown, several hollow isolation sleeves are interconnected to form a sacrificial isolation wall. The hollow isolation sleeves are connected by interconnects made of poly(α-methylstyrene) (PAMS), and the interconnects and hollow isolation sleeves can be fabricated simultaneously. The isolation wall facilitates interconnection between chips during use. Furthermore, in the past, when PD chips and TIA chips were eutectic bonded, displacement adjustment was first performed in the placement equipment using a vision system to ensure placement accuracy. However, the isolation wall is fabricated using semiconductor processes, so during the placement process, the physically guided isolation wall allows for a faster and more efficient subsequent eutectic reaction.

[0035] like Figure 1 As shown, the method for preparing a sacrificial isolation wall mainly involves the following steps: temporary carrier preparation → anti-adhesion layer preparation → PAMS solution preparation → spin coating → baking → photolithography and development → laser demolding and transfer. The specific steps are as follows: S11. Temporary carrier preparation: Quartz or borosilicate glass is selected as the carrier and is cleaned and dried. S12. Prepare an anti-adhesion layer on the carrier; spin-coat a 100-200 nm polytetrafluoroethylene (PTFE) thin film coating on the carrier to obtain the anti-adhesion layer; S13. Prepare poly-α-methylstyrene solution; select poly-α-methylstyrene (PAMS) powder with a molecular weight of 100,000 to 500,000 Daltons and add it to tetrahydrofuran (THF) at a concentration of 10 to 30 wt%, and complete the preparation of poly-α-methylstyrene solution in a stirrer. S14. Spin coating to form a film, completed in a spin coater; the spin coating thickness is approximately 8 μm, and the uniformity is controlled within 5%. Further, the poly-α-methylstyrene solution is spin-coated on the spin coater to a height of approximately 8 micrometers in the hollow isolation sleeve. S15, Baking; Bake at 95℃ for 60 seconds to remove the solvent in a hot plate or oven, allowing the poly-α-methylstyrene solution film to cure. S16. Photolithography and development to prepare the isolation wall; Photolithography and development are used to pattern the structure to obtain the pattern structure; Further, a contact lithography machine is used to expose the PAMS film through a mask, and after development, an isolation wall with a height of about 8 micrometers (the height is determined by the sum of the height of the PD pad and the height of the TIA pad, with a 2μm tolerance) is obtained. S17. Laser demolding and transfer are used to obtain the isolation wall of the required height.

[0036] like Figure 2 As shown, the guided confined eutectic interconnect structure is used to connect the lower TIA chip and the upper PD chip, mainly including... On the TIA chip side: Around each TIA pad on the surface, a hollow isolation sleeve or barrier made of sacrificial cleaning material is fabricated (the purpose of forming the barrier is to complete the process for all TIA pads on the TIA chip side in a single operation). The hollow isolation sleeve or barrier uses polyalphamethylstyrene (PAMS) as a temporary, mechanically assisted, sacrificial interconnect barrier. The decomposition temperature of the hollow isolation sleeve is near the eutectic point of the TIA pad. The hollow isolation sleeve is a precisely confined cylindrical space with a diameter slightly larger than the diameter of the TIA pad (within a range of less than 1 μm). The height of the hollow isolation sleeve on the TIA chip side is greater than the height of the TIA pad.

[0037] On the PD chip side, pick up the PD chip and place it on the isolation wall.

[0038] Interconnect solder joints (TIA pads and PD pads): The interconnect solder joints are located within the confined space of the isolation wall of the hollow isolation sleeve (i.e., inside the hollow isolation sleeve). The interconnect solder joints are columnar or frustum-shaped, which fully improves the wettability of the TIA pads and accelerates the metallurgical bonding of the intermetallic compound IMC (formed after the eutectic connection of the TIA pads and PD pads).

[0039] like Figure 2 As shown, a guided confined eutectic interconnect method for a PD chip and a TIA chip includes the following steps: S1. Prepare a sacrificial isolation wall; S2. The isolation wall is installed on the TIA pad 7 of the TIA chip 1. The purpose of this step is to place the isolation wall on the TIA pad 7 before the eutectic reaction, providing a physical guiding space for the subsequent process. S3. Pick up the PD chip 2 and place it on the isolation wall. Guide the PD pads 6 to fall one by one into the inner diameter of the hollow isolation sleeve 4, and apply slight contact pressure. The pressure can be applied manually or by using a pick-and-place machine. The purpose of applying pressure is to bond the upper and lower pads (TIA pads 7 and PD pads 6). Preferably, the sum of the heights of the TIA pads 7 and PD pads 6 has a 2μm tolerance with respect to the height of the hollow isolation sleeve 4. Figure 3 As shown.

[0040] S4. Place the mounted chip pair into a controlled atmosphere reflow oven, execute a precise temperature profile, and a eutectic reaction occurs, forming an IMC between TIA pad 7 and PD pad 6; simultaneously, the isolation wall completely degrades; as... Figure 4 As shown, the specific method is as follows: S41, First stage: Preheating; The controlled atmosphere reflux furnace heats the temperature to the first platform temperature of 180°C at a rate of 5-10°C / s and holds for 3-5s. S42, Second stage: Heat preservation; rapid heating in a controlled atmosphere reflux oven (2s heating) to 220℃ and holding for 5s; S43, Third stage: Eutectic reaction occurs and self-alignment occurs; the temperature is rapidly increased to above the eutectic temperature. After reaching the eutectic temperature, the TIA pads and PD pads completely melt, while the isolation wall does not melt. The hollow isolation sleeve wraps around the TIA pads and PD pads, forming IMC 8 inside the hollow isolation sleeve; after the temperature is increased again to reach the isolation wall degradation temperature, the isolation wall is completely degraded.

[0041] The temperature range for this third stage is 260℃~320℃.

[0042] In this third stage, the metallurgical reaction occurs: Au and Sn undergo a eutectic reaction to form a uniform intermetallic compound (IMC). Simultaneously, a hollow isolation sleeve encapsulates the IMC and fills its space. Specifically, the temperature is rapidly increased to above the eutectic temperature (in this embodiment, the eutectic system of the TIA and PD pads is an Au-Sn system, with a eutectic temperature of approximately 280°C). When the temperature reaches approximately 280°C, the Au-Sn system undergoes a eutectic reaction. At this point, the Sn on the TIA pad completely melts, and the Au on the PD pad melts, while the isolation wall remains unmelted. The hollow isolation sleeve 4 within the isolation wall encapsulates the IMC. At this time, the hollow isolation sleeve 4 acts as a confined flow area, strictly limiting the liquid solder (Au-Sn system) within the pre-defined cylindrical space, preventing lateral spread. Furthermore, the unmelted hollow isolation sleeve 4 also serves as a liquid self-alignment mechanism. The extremely high surface tension of the molten solder generates a powerful capillary force, automatically pulling the exposed wettable metal layer (Au) on the PD chip 6 towards and positioning it at the center of the confined space (hollow isolation sleeve), achieving micron-level precision self-alignment. After heating to the hollow isolation sleeve's degradation temperature, the hollow isolation sleeve completely degrades; a clean thermal decomposition occurs, leaving no ash residue.

[0043] When the temperature in the third stage reaches approximately 320℃, the barrier wall volatilizes: the barrier wall undergoes complete clean thermal decomposition, leaving no ash residue; PAMS degradation temperature is 260~320℃, and degradation tends to be complete at 300℃, leaving no residue after degradation. The degradation of the barrier wall does not produce liquid, only volatilization. Figure 5 As shown.

[0044] S5. The chip undergoes cooling and shaping, with controlled cooling to form uniform, regularly shaped, and robust eutectic solder joints. The controlled atmosphere reflow oven has a temperature control system and rapid heating and cooling capabilities; therefore, it can quickly cool from 320°C to room temperature in 8 seconds. For example... Figure 5 As shown.

[0045] The guided confined eutectic interconnection method for PD chips and TIA chips of the present invention transforms the influence of polymers (poly-α-methylstyrene) into a positive and controllable factor, specifically as follows: 1) Material matching: Select a polymer material (poly-α-methylstyrene) with a clear degradation temperature and no residue to prepare the isolation wall, ensuring that its degradation is slightly delayed compared to the solder melting time.

[0046] 2) Structural guidance: The open design (hollow isolation sleeve) at the top of the isolation wall provides a pre-set escape channel for degradation gases; it can also be used to reduce oxides on the surface of solder pads and improve metal wettability.

[0047] 3) Process assurance: Specific temperature profiles are more controllable within the eutectic reaction window, ensuring a clean interface.

[0048] 4) Positive Role of the Cavity: The hollow isolation sleeve structure provides space for columnar solder joints, reducing parasitic capacitance and buffering thermal stress, which is crucial for improving bandwidth and reliability. In the interconnect structure between PD and TIA chips, parasitic capacitance mainly occurs at two locations: 1. The capacitance between the solder pad and ground, and the capacitance formed between the solder pad and the underlying ground layer (or adjacent ground pads); 2. The capacitance of the solder joint itself. The hollow isolation sleeve fabricated by PAMS physically restricts the solder area precisely within the inner diameter of the sleeve, resulting in a columnar solder joint with a diameter equal to the inner diameter of the sleeve, more than 50% smaller than traditional solder joints. The parallel capacitance between solder joints can be expressed as: (ε: dielectric constant, A: solder joint area, D: solder joint height). Thermal stress mainly originates from thermal expansion coefficient (CTE) mismatch. 1. The stress in the columnar solder joint changes from interface concentration to uniform distribution within the solder joint body, absorbing some strain energy through overall elastic bending, reducing the stress transmitted to the interface; 2. The hollow isolation sleeve acts as an internal cavity to buffer stress.

[0049] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A guided confined eutectic interconnect structure, characterized in that, This includes several sacrificial hollow isolation sleeves made of poly-α-methylstyrene. The two ends of the hollow isolation sleeves are respectively fitted into the PD pads on the photodetector chip and the TIA pads on the transimpedance amplifier chip. During the eutectic reaction stage of the chip, the chip is heated to above the eutectic temperature. After reaching the eutectic temperature, the TIA pads and PD pads completely melt, while the hollow isolation sleeves do not melt. The hollow isolation sleeves wrap around the TIA pads and PD pads, forming an IMC inside the hollow isolation sleeves. After the temperature is raised to the degradation temperature of the hollow isolation sleeve, the hollow isolation sleeve is completely degraded.

2. The guided confined eutectic interconnect structure according to claim 1, characterized in that: Several hollow isolation sleeves are interconnected to form a sacrificial isolation wall.

3. The guided confined eutectic interconnect structure according to claim 2, characterized in that: The hollow isolation sleeves are connected by an interconnect frame made of poly-α-methylstyrene.

4. The guided confined eutectic interconnect structure according to claim 1, characterized in that: The height of the hollow isolation sleeve is equal to the sum of the height of the PD pad and the height of the TIA pad.

5. A guided confined eutectic interconnect method for a PD chip and a TIA chip, characterized in that: Interconnection according to any one of claims 1-4 using the guided confined eutectic interconnect structure includes the following steps: S1. Prepare a sacrificial isolation wall; S2. The isolation wall is installed on the TIA pad on the TIA chip side; S3. Pick up the PD chip and place it on the isolation wall, guide the PD pads to fall into the inner diameter of the hollow isolation sleeve (1) one by one, and apply slight contact pressure. S4. Place the mounted chip pair into a controlled atmosphere reflow oven, execute a precise temperature profile, and a eutectic reaction occurs, forming an IMC between the TIA pad and the PD pad; at the same time, the isolation wall is completely degraded. S5, chip cooling and molding.

6. The eutectic interconnect method according to claim 5, characterized in that: The preparation steps of S1 are as follows: S11. Temporary carrier preparation: Quartz or borosilicate glass is selected as the carrier and is cleaned and dried. S12. Prepare an anti-adhesion layer on the carrier; spin-coat a 100-200 nm polytetrafluoroethylene (PTFE) thin film coating on the carrier to obtain the anti-adhesion layer; S13. Prepare polyα-methylstyrene solution: Select polyα-methylstyrene powder with a molecular weight of 100,000 to 500,000 Daltons and add it to tetrahydrofuran at a concentration of 10 to 30 wt%. Complete the preparation of polyα-methylstyrene solution in a stirrer. S14. Spin coating to form a film, which is completed in a spin coater; S15, Baking; S16. Photolithography and development to prepare the isolation wall; S17. Laser demolding and transfer are used to obtain the isolation wall of the required height.

7. The eutectic interconnect method according to claim 6, characterized in that: The specific method for S15 is to bake at 95°C for 60 seconds, either on a hot plate or in an oven.

8. The eutectic interconnect method according to claim 5, characterized in that: The specific method for S4 is as follows: S41, First stage: Preheating; Increase the temperature to the first plateau temperature of 180°C at a rate of 5-10°C / s, and hold for 3-5 seconds; S42, Second Stage: Heat Preservation; Heat to 220℃ and hold for 5 seconds; S43, Third stage: Eutectic reaction occurs and self-alignment occurs; the temperature is rapidly increased to above the eutectic temperature. After reaching the eutectic temperature, the TIA pads and PD pads completely melt, while the isolation wall does not melt. The hollow isolation sleeve wraps around the TIA pads and PD pads, and IMC is formed inside the hollow isolation sleeve. Once the temperature is raised to the degradation temperature of the barrier wall, the barrier wall will be completely degraded.

9. The eutectic interconnect method according to claim 8, characterized in that: The temperature range for the third stage is 260℃~320℃.

10. The eutectic interconnect method according to claim 8, characterized in that: In the third stage, the controlled atmosphere reflux furnace is rapidly heated to 220°C.

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