A packaging structure and a packaging method

Abstract

The application discloses a packaging structure and a packaging method, which comprises the following steps: electroplating metal layers on opposite surfaces of a substrate, etching circuit patterns on one of the metal layers, attaching a chip with the back surface facing the circuit patterns, electrically connecting the back surface electrodes of the chip with corresponding circuit pattern areas, and encapsulating the chip and the substrate; electroplating a column protruding from the encapsulating material on the front surface of the chip, etching the encapsulating material to expose the circuit pattern traction area; electroplating lines one, two and three, filling the etching area with the lines two and three and respectively interconnecting the lines two and three with the front surface electrodes of the chip through the column one; filling the etching area with the line one and interconnecting the line one with the back surface electrodes of the chip through the circuit patterns, and encapsulating the lines; vertically etching through holes on the encapsulating surface to expose the electrically conductive ends of the circuit patterns; and the packaging parameters, heat dissipation efficiency and other adverse factors of the whole packaging structure are significantly reduced, and the electrical performance and thermal management requirements of the module under high temperature and high pressure conditions are met.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and particularly relates to a packaging structure and packaging method. Background Technology

[0002] Power semiconductor devices are widely used in computers, network communications, consumer electronics, industrial control, automotive electronics, power systems and other fields. Silicon carbide-based power devices, with their advantages of high breakdown electric field strength, good thermal stability, high carrier saturation drift velocity and high thermal conductivity, will play an increasingly important role in future energy systems. At the same time, in power electronic products, providing more power in the same package space or less package space is a continuous trend.

[0003] When existing power semiconductor devices are packaged in parallel with multiple chips, traditional packaging processes and wiring layouts result in adverse factors such as packaging parameters, heat dissipation efficiency, and reliability that have a significant impact on product performance, making it difficult to meet the electrical performance and thermal management requirements of silicon carbide modules under high temperature and high pressure conditions. Summary of the Invention

[0004] To address the problems in the prior art, the present invention provides a packaging structure and packaging method.

[0005] To achieve the above objectives, the present invention proposes a packaging method comprising the following steps: Metal layers are electroplated on both sides of the substrate, and circuit patterns are etched on one of the metal layers. The chip is mounted with its back side facing the circuit pattern, and the back electrode of the chip is electrically connected to the corresponding circuit pattern area. The chip and the substrate are then encapsulated. One pillar on the front of the chip is flush with the encapsulation material, and the encapsulation material is etched to expose the circuit pattern pull area. Electroplated circuits 1, 2 and 3 are formed. Circuits 2 and 3 fill the etched area and are respectively interconnected with the front electrode of the chip through pillar 1. Circuit 1 fills the etched area and is interconnected with the back electrode of the chip through the circuit pattern, encapsulating each circuit. Through-holes are vertically etched into the encapsulation surface to expose the electrical leads of the circuit pattern; Cut into packaged product units.

[0006] Furthermore, the package is divided into two parts, A and B. Both parts are fitted with the same number of chips and have the same structure. Each group of chips has the same structure due to the same process steps in the packaging method. That is, both are provided with Line 1, Line 2, Line 3, Pillar 1, and via. The chips in the two parts form two circuit half-bridges through Line 1, Line 2, Line 3 and the circuit pattern area, respectively. The half-bridges are electrically connected to form a parallel circuit structure of the package chips. The circuit pattern etched on the metal layer of the substrate is set according to the actual product situation. Through the lines and circuit patterns, the electrical connection relationship and layout of the entire package structure are more complete, thereby realizing the product function.

[0007] Furthermore, the metal layer without etched circuit patterns on the substrate is flush with the package and exposed, and covered by a layer of solder pads. The solder pads completely cover the exposed metal layer, forming a large-area heat dissipation channel in the package structure.

[0008] Furthermore, the exposed electrical terminals of the circuit pattern through-hole are covered with a coating to prevent oxidation; the coating covers the edge where the encapsulant meets the metal surface of the electrical leads of the circuit pattern, but does not cover the final conductive contact surface of the electrical leads of the circuit pattern, thereby reducing the intrusion of moisture, sulfide gases, etc. into the plating area inside the package to prevent oxidation.

[0009] Furthermore, the electroplated conductive pillars inside the via are filled to the surface of the package to form external leads. The external leads realize the electrical connection relationship of the chip through the conductive pillars, lines one, two and three, pillar one, and circuit pattern. The external leads serve as the external medium for the electrical traction of the package.

[0010] An encapsulation structure includes an encapsulation body, the encapsulation body containing: The substrate has metal layers electroplated on both sides of the substrate. Circuit patterns are etched on one metal layer, and the other metal layer is flush with and exposed on one surface of the package. The chip is mounted with its back side facing the circuit pattern. The electrodes on the back of the chip are electrically connected to the corresponding circuit pattern area. The front of the chip is plated with a pillar. Lines 1, 2 and 3, and lines 2 and 3 are interconnected with the front electrode of the chip via post 1; line 1 is interconnected with the back electrode of the chip via the circuit pattern. A via exposes the electrical leads of the circuit pattern to the opposite surface of the exposed metal layer outside the package.

[0011] Furthermore, the package is divided into two parts, A and B. The two chip parts are connected by line one, line two, line three and circuit pattern area to form two circuit half bridges, and the half bridges are electrically connected to form a chip parallel circuit structure.

[0012] Furthermore, the metal layer on the substrate without etched circuit patterns is flush with and exposed to the package, and covered by an electroplated pad.

[0013] Furthermore, the electrical terminals of the exposed circuit pattern of the via are covered with a coating to prevent oxidation.

[0014] Furthermore, the electroplated conductive pillars inside the through-hole are filled to the surface of the package to form external leads.

[0015] The beneficial effects of this invention are as follows: By partitioning and conducting multiple chips, and using multiple lines to achieve parallel packaging, the path is thickened and the structure is designed for double-sided heat dissipation. Compared with traditional packaging, the packaging parameters, heat dissipation efficiency, reliability and other adverse factors of the entire packaging structure are significantly reduced, which meets the electrical performance and thermal management requirements of silicon carbide modules under high temperature and high pressure conditions. Attached Figure Description

[0016] Figures 1-3 This is a flowchart illustrating the initial chip encapsulation step of a first embodiment of the encapsulation method of the present invention. Figures 4-6 This is a schematic flowchart of the circuit plating steps in an embodiment of a packaging method of the present invention. Figures 7-9 This is a schematic flowchart of the circuit thickening electroplating step in an embodiment of a packaging method of the present invention; Figure 10 This is a flowchart illustrating the exposed electrical lead-out step of an embodiment of the packaging method of the present invention. Figures 11-12 This is a schematic flowchart of the pad plating step in an embodiment of a packaging method of the present invention. Figure 13 This is a perspective view of the package structure according to a first embodiment of the packaging method of the present invention; Figure 14 This is a top view of one embodiment of the packaging structure of the present invention; Figure 15 This is a bottom view of one embodiment of the packaging structure of the present invention; Figure 16 This is a cross-sectional view of a first embodiment of the packaging structure of the present invention; Figures 17-19 This is a flowchart illustrating the initial chip encapsulation step in a second embodiment of the encapsulation method of the present invention. Figure 20 This is a cross-sectional view of the package structure according to a second embodiment of the packaging method of the present invention; Figure 21 This is a perspective view of the package structure according to a second embodiment of the packaging method of the present invention.

[0017] In the diagram: 1. Substrate; 2. Circuit pattern; 3. Chip; 4. Line 1; 5. Line 2; 6. Line 3; 7. Pillar 1; 8. Pad; 9. Thickened layer; 10. Via; 11. Package. Detailed Implementation

[0018] The present invention will now be described in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout.

[0019] The directional terms used in this invention, such as up, down, left, right, front, back, inside, outside, front, back, side, etc., are merely for reference to the accompanying drawings. The embodiments and directional terms used in the following description with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Furthermore, the various specific processes and materials provided in this invention are examples that those skilled in the art will recognize for the application of other processes and / or the use of other materials.

[0020] Figures 1-13 This is a schematic cross-sectional view illustrating various stages in a packaging method for fabricating a package structure according to some embodiments of the present invention. It should be noted that the process steps described herein cover a portion of the manufacturing process used to fabricate the package structure. The embodiments are intended to provide further explanation and are not intended to limit the scope of the invention.

[0021] To better understand the purpose, structure, and function of this invention, a packaging structure and packaging method proposed in this invention will be described in further detail below with reference to the accompanying drawings. Figures 1-13 An exemplary flowchart illustrating the encapsulation method is provided.

[0022] The encapsulation method includes the following steps.

[0023] Metal layers are electroplated on both sides of the substrate 1, and a circuit pattern 2 is etched on one of the metal layers. The back side of the chip 3 is mounted with the circuit pattern 2 facing the back side. The back electrode of the chip 3 is electrically connected to the corresponding area of ​​the circuit pattern 2, and the chip 3 and the substrate 1 are encapsulated.

[0024] The front of chip 3 is plated flush with the encapsulant, exposed on pillar 7. The encapsulant is etched to expose the traction area of ​​circuit pattern 2.

[0025] Electroplated lines 4, 5, and 6 are used. Lines 5 and 6 fill the etched areas and are interconnected with the front electrode of chip 3 via pillar 7. Line 4 fills the etched areas and is interconnected with the back electrode of chip 3 via circuit pattern 2, thus encapsulating each line.

[0026] A via 10 is vertically etched into the encapsulation surface, exposing the electrical leads of the circuit pattern 2.

[0027] Cut into 11 product units of package body.

[0028] The specific process steps are illustrated in the examples. Example 1

[0029] When chip 3 is mounted onto the metal layer on substrate 1 with the circuit pattern 2 etched thereon, it is called chip 3 mounting. According to the product functional requirements and layout design, multiple chips 3 are mounted on substrate 1. After the chips 3 are firmly mounted, substrate 1, the metal layers plated on opposite sides of substrate 1, the circuit pattern 2 etched on one metal layer, and chip 3 are regarded as a whole power module. The front of chip 3 corresponds to the front of the whole power module, and the opposite surface is the back of the whole power module. The back of the whole is mounted facing the carrier board for subsequent process flow.

[0030] The specific steps are as follows.

[0031] S1: A substrate 1 is provided, the core of which is a ceramic layer, and the upper and lower surfaces of the substrate 1 are metal layers, such as copper layers. The middle ceramic layer (such as high-strength aluminum nitride) can insulate electrical circuits to prevent circuit conduction and provide a high thermal conductivity path. Moreover, the upper and lower copper metal layers can be etched into specific circuit patterns 2 according to the requirements of the process or structure, serving as the welding carrier and electrical connection medium for the chip 3.

[0032] A metal layer is electroplated on both the top and bottom surfaces of the ceramic layer. The thickness of both the ceramic layer and the metal layer is customized according to the actual product requirements. The electroplating process allows the metal layer to adhere firmly to both surfaces of the ceramic layer, resulting in better reliability. Other methods can also be used to form a composite structure of ceramic and metal, such as lamination. Then, the circuit pattern 2 is etched on one side of the metal layer according to the circuit conduction requirements, serving as the welding carrier and electrical connection medium for the chip 3.

[0033] The circuit pattern 2 etched on the metal layer of substrate 1 can be divided into the following areas: DC positive terminal (P), DC negative terminal (N terminal), AC terminal (AC terminal), gate signal terminal 1 (G1), source signal terminal 1 (S1), drain signal terminal 1 (D1), gate signal terminal 2 (G2), source signal terminal 2 (S2), and drain signal terminal 2 (D2). The product unit of package 11 is divided into two parts, A and B, and the circuit pattern 2 area extending onto substrate 1 is also divided into the same two parts, A and B. Part A can be divided into gate signal terminal 1 (G1), source signal terminal 1 (S1), drain signal terminal 1 (D1), and DC positive terminal (P); Part B can be divided into gate signal terminal 2 (G2), source signal terminal 2 (S2), drain signal terminal 2 (D2), DC negative terminal (N terminal), and AC terminal (AC terminal). The AC terminal (AC terminal) electrically connects parts A and B together.

[0034] S2: After etching the circuit pattern 2 on the metal layer of substrate 1, mount the chip 3 (e.g., ...) in the corresponding mounting area. Figure 1 and Figure 2 As shown, where Figure 2 for Figure 1 (Top view), the mounting area on the back of chip 3 on the circuit pattern 2 is mounted using bonding technology (such as reflow soldering with lead-free solder of tin-silver-copper alloy or sintering silver technology). The mounting area is greater than or equal to the mounting surface area of ​​chip 3 to ensure that chip 3 is fully supported. In this embodiment, the mounting area of ​​chip 3 faces the substrate 1. The electrodes on the back of chip 3 are electrically connected to the corresponding area of ​​the etched circuit pattern 2. According to product design requirements and functional settings, multiple sets of chips 3 are selectively mounted on the substrate 1, and the positional relationship and spacing between each set of chips 3 are evenly arranged. This invention does not limit this.

[0035] The product unit structure of the package 11 of the present invention is divided into two parts, A and B. These two parts constitute two circuit half-bridge structures. Taking the mounting of two sets of chips 3 as an example, one set of chips 3 is mounted in part A and another set of chips 3 is mounted in part B. Each set includes 4 chips 3 that are laid flat and evenly arranged. The mounting method of multiple chips 3 is the same (all are upright mounting with the back facing the circuit pattern 2). The present invention does not limit the number of chip 3 sets mounted on the same substrate 11.

[0036] Chip 3 in part A is mounted in the P terminal area of ​​circuit diagram 2, and chip 3 in part B is mounted in the AC terminal area of ​​circuit diagram 2.

[0037] Chip 3 is a power semiconductor chip 3, such as a SiC-MOSFET chip 3. The back of chip 3 is the drain (D) and the front of chip 3 has the source (S) and gate (G). The drain occupies all the area on the back of chip 3, the source occupies a larger area on the front of chip 3, and the gate occupies a smaller area on the front of chip 3. The number and distribution of the source and gate on the front of chip 3 are set according to the actual product situation. This invention does not limit this. Since the same chip 3 is mounted, the chip 3 has the same height and other dimensions after mounting.

[0038] The intermediate ceramic layer of substrate 1 can be high-strength aluminum nitride, etc. Therefore, the coefficient of thermal expansion of substrate 1 is close to that of chip 3, the thermal stress is small, and higher reliability can be provided.

[0039] In this embodiment, the chip 3 is mounted on the corresponding area of ​​the circuit pattern 2 etched on the metal layer of the substrate 1. The drain on the back of the chip 3 is electrically connected to the corresponding area of ​​the etched circuit pattern 2. The circuit pattern 2 pulls the drain on the back of each chip 3 to be arranged. The source and gate on the front of the chip 3 are exposed.

[0040] S3: The substrate 1, the metal layers plated on both sides of the substrate 1, the circuit pattern 2 etched on one of the metal layers, and the chip 3 are considered as a power module assembly. The front side of the chip 3 corresponds to the front side of the power module assembly, and the opposite surface is the back side of the power module assembly. The back side of this assembly is then mounted facing the carrier board. That is, the metal layer surface of the substrate 1 without the circuit pattern 2 is mounted facing the working area of ​​the carrier board, so that the power module assembly is mounted in the working area of ​​the carrier board. The carrier board can be a resin board commonly used in the packaging field. According to the carrying capacity of the carrier board, multiple evenly spaced power module assemblies can be selectively mounted. Each power module assembly undergoes the same process flow, and finally obtains the same structure, which is then cut and separated into individual package 11 product units. This invention takes the mounting of a single power module assembly as an example.

[0041] S4: The power module is completely encapsulated using encapsulation material, with the entire power module facing upwards. At this time, the substrate 1, the metal layers electroplated on both sides of the substrate 1, the circuit pattern 2 etched on the metal layer, and the chip 3 are all completely encapsulated in the encapsulation material. This is the first encapsulation in the entire process. After the encapsulation material is cured, it becomes the first encapsulation layer.

[0042] During encapsulation, a measured amount of preheated epoxy resin molding compound (EMC) powder, granules, or pre-formed cakes are placed evenly into the mold cavity of the lower mold of the encapsulation mechanism. The upper and lower molds are preheated to 170-190℃ and then the upper and lower molds are closed and high pressure (5-20MPa) is applied. The molding compound melts in place in the cavity, flows under pressure, and naturally and evenly fills the mold cavity, thus completing the initial encapsulation. The flow path of the molding compound in the mold is short and does not pass through long runners, resulting in a smoother filling process and reducing the likelihood of punctures or uneven filling. This effectively reduces residual stress after encapsulation. After curing, the mold is opened and the encapsulated structure is ejected.

[0043] After the encapsulation process is completed, an etching process (such as laser etching) is used to drill holes along the height direction of the encapsulation layer on the top surface of the first encapsulation layer until the front electrodes (source and gate) of chip 3 and part of the circuit pattern 2 (such as G1 terminal, N terminal, S1 terminal, P terminal, D1 terminal, AC terminal, G2 terminal, S2 terminal, D2 terminal) are exposed. Figure 3 (As shown) and through an electroplating process, a column 7 is electroplated into the drill hole of the exposed front electrode of chip 3 to completely fill the drill hole (as shown). Figure 4 As shown), post 7 is electrically connected to the front electrode of chip 3. The top surface of post 7 is flush with the surface of the encapsulation layer 1 through the drilled hole and exposed. The exposed end surface of post 7 electrically pulls the front source and gate of chip 3 to the surface of encapsulation layer 1.

[0044] S5: While plating pillar 7, plating lines 4, 5, and 6 are extended on the surface of the encapsulation layer. Line 5 is electrically connected to pillar 7 plated on the source electrode of chip 3, and line 6 is electrically connected to pillar 7 plated on the gate electrode of chip 3. When lines 5 and 6 are extended on the surface of the encapsulation layer, they also completely cover and fill the other drilling areas in step S3 (such as N-terminal, S1-terminal, P-terminal, D1-terminal, AC-terminal, S2-terminal, and D2-terminal). When line 4 is extended on the surface of the encapsulation layer, it also completely covers and fills the other drilling areas in step S3 (such as G1-terminal and G2-terminal). Figure 5 and Figure 6 As shown, where Figure 6 for Figure 5 (Top view).

[0045] Furthermore, due to independent gate drive control, the front gate electrical properties of chip 3 in part A are combined into one line by each line 4 through pillar 7 and then pulled into a layout, while the front gate electrical properties of chip 3 in part B are combined into one line by each line 4 through pillar 7 and then pulled into a layout.

[0046] The circuit connection method of this invention is exemplary. The electrical connections between these lines are selected according to the actual product function requirements. The P and N terminals are the DC power supply terminals of the power module. High-voltage DC is input to the positive terminal through the P terminal. The P terminal is generally connected to the drain of a half-bridge and is the high-voltage input terminal of the product module. The N terminal is generally connected to the source of the other half-bridge, forming a DC loop return line. The AC terminal is the connection point between the drain of one half-bridge and the source of the other half-bridge. Therefore, the circuit conduction direction of this embodiment of the invention is as follows: Half-bridge A section: P terminal → drain of each chip 3 in section A → vertical conduction inside chip 3 in section A → source of each chip 3 in section A → line 25 in section A → AC terminal (flow to load); Half-bridge B section: AC terminal (load return) → drain of each chip 3 in section B → section B Chip 3 is vertically conductive → source of each chip 3 in section B → line 2 5 in section B → N terminal; the gates of each chip 3 in section A are combined into one line, namely line 3 6 in section A, and electrically connected to the G1 terminal of section A; the gates of each chip 3 in section B are combined into one line, namely line 3 6 in section B, and electrically connected to the G2 terminal of section B. The G1 and G2 terminals are independently driven and controlled to realize the conduction of the A and B half-bridges respectively. The two groups of devices form a bridge arm circuit, forming a multi-device parallel circuit structure. The chip 3 group is not a single-path current amplification; the conduction path inside each chip 3 is the drain on the back of chip 3 → vertical conduction of the main body of chip 3 → output of the source on the front of chip 3, with independent gate drive and control; each line and chip 3, together with the circuit pattern 2 etched on the substrate 1, realize the electrical function of the entire package structure.

[0047] Then, the drain of chip 3 is led out to the D1 and D2 terminals on circuit diagram 2 through the corresponding line 4 of each part. At the same time, the corresponding source signals need to be led out to the S1 and S2 terminals on circuit diagram 2.

[0048] Multi-chip 3-zone mounting and zone conduction improve product reliability; multi-line traction enables parallel packaging with optimized path design, no excessively long traces, and high path current conduction capacity.

[0049] Furthermore, since multiple chips 3 are laid flat on the substrate 1 in this invention, and the multiple chips 3 are electrically connected in parallel through processes such as mounting and wiring, the thickness requirements of the circuits with different functions are different. The circuit layer that realizes the conduction of power current needs to be thicker (such as S1 terminal / S2 terminal / D1 terminal / D2 terminal / P terminal / N terminal / AC terminal), while the circuit layer that realizes signal control and driving does not need to be thick (such as G1 terminal / G2 terminal). Setting different thicknesses of circuits can not only reasonably control production costs, but also save packaging space.

[0050] For power lines (such as S1 / S2 / D1 / D2 / P / N / AC terminals), the total current carried by the line is as high as 200-600A, and even higher at peak times. The thin line layer, insufficient current flow, small cross-sectional area, high line resistance, and poor heat dissipation lead to severe heat generation, serious risk of local burn-out, and easy detachment of the line. Therefore, the line needs to be thickened to the minimum safe thickness limit.

[0051] For signal driving circuits (such as G1 / G2 terminals), the circuits are independently controlled and driven, and the layout space is limited. To achieve cost control, it is only necessary to refine the thin-layer electroplating of the circuits, without any thickness limit, so as to meet the normal operation requirements of the circuits during electroplating in the chip 3-packaging field.

[0052] Blindly plating a thick circuit layer directly during the initial electroplating process can directly affect the formation of fine circuit layers between chips 3 due to process limitations: the thicker the plating layer, the longer the plating time, and the greater the fine plating error; the worse the plating uniformity, the greater the functional differences on the circuit layer; and it is difficult to control the process partitioning plating according to different plating thickness requirements. Therefore, this invention completes the plating of power lines and signal lines on the basis of the initial thin plating, and then uses the same plating process to plating only the power line area. The power line area obtains the final minimum safe thickness limit through two or even more thin platings. The cumulative height of the two or more platings is the height of the thickened layer 9. This minimum safe thickness limit can be obtained by multiple experiments during the company's process verification stage, or it can be calculated in the packaging design stage in combination with theoretical knowledge. In this invention, the plating thickness of the signal line is between 20-35μm, and this embodiment takes 25μm as an example. The thickness of the thickened layer 9 plated on the power line is between 110-135μm, and this embodiment takes 125μm as an example. Of course, this invention does not limit this.

[0053] Through multiple cumulative electroplating processes, a thicker layer 9 (such as...) is electroplated onto the circuit layer. Figure 7 and Figure 8 As shown, where Figure 8 for Figure 7 (Top view) The initial thin-layer electroplating ensures the formation of a fine circuit layer. Each layer releases some stress, resulting in a lower total stress after stacking, and better anti-warping and anti-delamination effects. The current enrichment effect is weakened during layered electroplating, resulting in a more uniform circuit layer thickness, uniform resistance and temperature rise distribution, avoiding local hot spots, and improving product performance stability. Different electroplating thicknesses can be applied in sections, which is efficient and convenient, and also ensures the conductivity of power circuits.

[0054] S6: Based on the first encapsulation layer, the same encapsulation process is used a second time to completely encapsulate all circuits and the thickened layer 9 (e.g., ...). Figure 9As shown), it constitutes the second encapsulation layer. The second encapsulation layer and the first encapsulation layer are encapsulated and cured into a whole in the contact area, which is the product unit of the package 11.

[0055] S7: A through-hole 10 is formed by vertically drilling a hole on the surface of the encapsulation layer 2 using a laser etching process (e.g., ...). Figure 10 As shown), the via 10 penetrates the encapsulation material of the second encapsulation layer and the first encapsulation layer and is etched to the substrate 1; the bottom of the via 10 directly exposes part of the metal copper layer circuit pattern 2 area on the substrate 1, such as exposing part of the blank areas of the P terminal, AC terminal, N terminal, D1 terminal, G1 terminal, S1 terminal, D2 terminal, S2 terminal and G2 terminal of the circuit pattern 2, while avoiding the chip 3 or the line or the drill hole in these areas.

[0056] The exposed circuit diagram 2 electrical terminals constitute the package 11 product unit encapsulation material internal and external electrical connection ports. Through these ports, the package 11 is connected to corresponding external electrical components and other device structures to perform product functions.

[0057] Furthermore, the electrical terminals of the exposed circuit pattern 2 through the via 10 are covered with a coating to prevent oxidation; the coating covers the edge where the encapsulant meets the metal surface of the electrical lead of the circuit pattern 2, but does not cover the final conductive contact surface of the electrical lead of the circuit pattern 2, thereby reducing the intrusion of moisture, sulfide gases, etc. into the plating area inside the package 11 to prevent oxidation.

[0058] Furthermore, the electroplated conductive pillars inside the via 10 are filled to the surface of the package 11 to form external pins (not shown in the figure). The external pins realize the electrical connection relationship of the chip 3 through the conductive pillars, lines 4, 2 and 3, pillar 7, and circuit pattern 2. The external pins serve as the external medium for the electrical traction of the package 11.

[0059] Furthermore, to facilitate the use of end products and meet functional design requirements, the exposed partial through-holes 10 are filled with electroplated metal portions, such as the exposed AC, N, D2, S2, and G2 terminals of part B, which are filled with metal portions (e.g. Figure 6 and Figure 8 As shown), the filling can be completed in step S5, or it can be electroplated here.

[0060] S8: Since the power module was encapsulated with its front side facing up in step S4, the metal layer of the substrate 1 without circuit pattern 2 was directly mounted to the working area. After flipping the entire encapsulation, the copper layer of the substrate 1 without circuit pattern 2 was flush with and exposed to the package 11. In this area, the electroplated pads 8 covered (e.g., Figure 11 As shown), pad 8 completely covers the exposed copper metal layer and occupies a large area of ​​the entire surface, serving as a medium for external heat dissipation.

[0061] The solder pads 8 are electroplated and covered on the surface of the package 11, and are connected to the metal layer of the substrate 1 without circuit pattern 2. The heat of the chip 3 is dissipated directly from the large-area solder pads 8 through the intermediate core ceramic and metal layer, resulting in low thermal resistance and good heat dissipation.

[0062] Furthermore, in the case of mounting multiple power modules on a carrier board, after the multiple power modules are spaced apart and evenly arranged, there is a gap between each power module. After encapsulation, the gaps are filled with encapsulating material, and the gaps form the final cutting groove. After all the above processes are completed, each power module has the same structure. The package 11 of the whole is vertically cut in the cutting groove area to form the product unit (e.g., Figure 12 and Figure 13 As shown, where Figure 13 for Figure 12 (Perspective view).

[0063] Each package 11 includes the following structures (e.g.) Figure 14 , Figure 15 and Figure 16 (As shown).

[0064] Substrate 1, with metal layers electroplated on both opposite sides, circuit pattern 2 etched on one metal layer, and the other metal layer flush with and exposed on one surface of package 11; the metal layer on substrate 1 without etched circuit pattern 2 is flush with and exposed on package 11, and covered by a layer of solder pad 8 electroplated.

[0065] Chip 3 is mounted with its back side facing the circuit pattern 2. The electrodes on the back of chip 3 are electrically connected to the corresponding areas of the circuit pattern 2. The front side of chip 3 is plated with pillar 7.

[0066] Lines 1, 2, and 3, and lines 2, 5, and 3, 6 are interconnected with the front electrode of chip 3 via pillar 1, 7; line 1, 4 is interconnected with the back electrode of chip 3 via circuit pattern 2.

[0067] The via 10 exposes the electrical leads of the circuit pattern 2 to the opposite surface of the exposed metal layer of the package 11; the electrical leads of the circuit pattern 2 exposed by the via 10 are covered with a coating to prevent oxidation; the electroplated conductive pillars in the via 10 are filled to the surface of the package 11 to form external leads.

[0068] The package 11 is divided into two parts, A and B. The two parts of the chip 3 are respectively connected by line 1 4, line 2 5, line 3 6 and the circuit pattern 2 area to form two circuit half-bridges. The half-bridges are electrically connected to form a parallel circuit structure of chip 3.

[0069] Compared to the process of mounting the power module with the front side facing the carrier board, the power module in this embodiment is mounted with the back side facing the carrier board, which eliminates one encapsulation and grinding process and reduces costs.

[0070] The packaging structure is obtained by the above-described packaging method steps, but the packaging structure of the present invention is not limited to the packaging method steps described above. Other processes that form the same or similar packaging structures are also within the protection scope of the present invention.

[0071] The cross-sectional diagrams of the packaging structure and packaging method are attached. Figure 13 The direction of the cross section is obtained. Example 2

[0072] When chip 3 is mounted onto the metal layer on substrate 1 with the circuit pattern 2 etched thereon, it is called chip 3 mounting. According to the product functional requirements and layout design, multiple chips 3 are mounted on substrate 1. After the chips 3 are firmly mounted, substrate 1, the metal layers plated on opposite sides of substrate 1, the circuit pattern 2 etched on one metal layer, and chip 3 are regarded as a whole power module. The front of chip 3 corresponds to the front of the whole power module, and the opposite surface is the back of the whole power module. The front of the whole is mounted facing the carrier board for subsequent process flow.

[0073] Compared to the process of mounting the power module with the back side facing the carrier board, the difference in the process of mounting the power module with the front side facing the carrier board in this embodiment lies in some processes in steps S3, S4, and S8. Other processes and conditions are the same. In order to facilitate the comparison between the two embodiments, the process steps of the two embodiments are compressed to S1-S8.

[0074] In step S3 after steps S1 and S2 in Embodiment 1: the entire power module is mounted with its front side facing the carrier board. At this time, the source and gate of chip 3 are mounted with their front sides facing the working area of ​​the carrier board, so that the entire power module is mounted with its front side facing the carrier board in the working area of ​​the carrier board.

[0075] S4: Use encapsulating material to completely encapsulate the power module, resulting in the first encapsulation layer (e.g., ...). Figure 17 As shown), at this time, the metal layer of the substrate 1 without circuit pattern 2 is completely encapsulated in the encapsulating material. After the encapsulating material cures, the encapsulating layer 1 is peeled off from the carrier board and flipped upside down to be reattached to the carrier board. At this time, the source and gate of the chip 3 are flush with the same surface as the encapsulating layer 1 and exposed. Pillars 7 are electroplated on the exposed source and gate of the chip 3 (as shown). Figure 18 As shown, this pillar 7 differs from the pillar 7 in Embodiment 1. Since the pillar 7 here is directly electroplated on the electrode, the fully electroplated pillar 7 on each electrode is conductive. This is different from the pillar 7 in Embodiment 1, which is formed by drilling and filling holes. In Embodiment 1, multiple holes are drilled on each electrode to fill multiple pillar 7s. The process flow and process capabilities are different. Therefore, the pillar 7 in this embodiment has a larger size, making reasonable use of the packaging space. Especially for power lines, the conductivity requirement is greater, and the conductivity is greatly improved, thus improving product performance.

[0076] Based on encapsulation layer one, continue using encapsulating material to completely encapsulate column one 7, and then horizontally mechanically grind the top surface of the encapsulation until the end of column one 7 is exposed. This encapsulating material then cures to form encapsulation layer two (e.g., ...). Figure 19 As shown in the figure, the second encapsulation layer and the first encapsulation layer are cured and fused together in the contact area.

[0077] Subsequent electroplating of circuits 4, 2, 3 and thickened layer 9, etc., but in step S6, each circuit and thickened layer 9 are completely encapsulated to form encapsulation layer three. Encapsulation layer three, encapsulation layer two and encapsulation layer one are encapsulated and cured into a whole in the contact area, that is, the product unit of package 11.

[0078] The structure of each package 11 is similar to that of the package 11 in Embodiment 1, the only difference being the pillar 7. In this embodiment, the pillar 7 on each electrode on the front side of the chip 3 is completely and seamlessly connected (e.g., ...). Figure 20 and Figure 21 As shown, where Figure 21 for Figure 20 The perspective view, the cross-sectional direction of the attached drawing of Embodiment 2 is as follows Figure 21 (As shown in the mid-section direction), in Embodiment 1, the pillars 7 on each electrode on the front side of chip 3 are small-sized and widely distributed, with multiple pillars 7 conducting.

[0079] In this embodiment, in the subsequent electroplating pad 8 step, since the power module is mounted with its front facing the working area, and the metal layer of the circuit-free pattern 2 of the substrate 1 is also encapsulated in the encapsulation layer 1, the surface of the metal layer needs to be ground and exposed before the pad 8 is electroplated and covered.

[0080] Compared to the process of mounting the entire power module with the back facing the carrier board, the power module in this embodiment is mounted with the entire front facing the carrier board, which greatly increases the power line conductivity and improves product performance.

[0081] The packaging structure and method of this invention improve product reliability by mounting and conducting multiple chips in three zones; parallel packaging with multi-line traction and optimized path design eliminates excessively long traces, increases current conduction capacity, reduces stray inductance and other parameters within the module, releases SiC high-frequency performance, and reduces losses; the packaging is shock-free and stress-free, with low thermal resistance and double-sided heat dissipation, resulting in better packaging parameters; it saves lateral wiring space, resulting in smaller module size for the same current rating, which is beneficial for electronic control integration and automotive lightweighting; the overall packaging structure significantly reduces adverse factors such as packaging parameters, heat dissipation efficiency, and reliability compared to traditional packaging, meeting the electrical performance and thermal management requirements of silicon carbide modules under high temperature and high pressure conditions.

[0082] The process sequence in the above embodiments is not unique, and simple changes to the process without substantial changes are also within the scope of protection of this invention.

[0083] In all embodiments of this invention, the encapsulation steps involve encapsulation materials, specifically epoxy resin, cyanate ester, polyimide, etc., which are low in cost, have good curing performance, and play an important role in the semiconductor manufacturing field, mainly in protecting the chip, connecting the whole structure, supporting the structure, improving reliability, and promoting technological progress. During encapsulation, a measured amount of preheated epoxy resin encapsulation material (EMC) powder, granules, or pre-formed into a cake shape is placed evenly in the mold cavity of the lower mold of the encapsulation mechanism. The upper and lower molds are preheated to 170-190℃, and the molds are closed under high pressure (5-20MPa). The encapsulation material melts in situ within the cavity, flows under pressure, and naturally and evenly fills the mold cavity, thus completing the initial encapsulation. The flow path of the encapsulation material within the mold is short, avoiding long flow channels, resulting in a smoother filling process and reducing the likelihood of bridging or uneven filling. This effectively reduces residual stress after encapsulation. After curing, the mold is opened, and the encapsulated structure is ejected. Of course, other suitable encapsulation methods and materials can also be used.

[0084] In all embodiments of this invention, where the process involves grinding the encapsulating material, a three-stage progressive grinding method of coarse grinding, fine grinding, and polishing can be used. First, coarse grinding is performed using low-grit diamond grinding discs or wheels to quickly remove most of the encapsulating material. Then, fine grinding is performed using high-grit diamond abrasive belts or sandpaper to remove scratches from the coarse grinding, gradually grinding until the surface of the structure to be exposed is reached. Finally, polishing is performed using a polishing cloth. After grinding, the exposed structure is free of burrs, the chip 3 is free of microcracks, and the surface is smooth. Grinding to the exposed pillar 7 in each process flow of this invention can be performed using the above method. Furthermore, the degree of grinding can be selected according to the actual requirements of the product, and the above grinding process can be reasonably modified.

[0085] In all process steps of this invention involving electroplating, the process begins with the application of a photoresist film followed by photolithography techniques such as exposure and development to form a protective electroplating layer on the surface of the affected area. Areas not requiring electroplating are protected by the photoresist film, exposing the areas to be plated. Then, a metal seed layer is formed on the exposed area using appropriate methods such as sputtering or copper plating. This seed layer, made of copper or other metal, ensures adhesion between metals and between the metal and encapsulant during subsequent electroplating, and provides a surface for conductive ion adhesion, thus guaranteeing the electroplating effect. The entire electroplating process and the materials used are common knowledge in the field. In this invention, the chip 3 front pillar 7, all circuits, external pins, and pads 8 are all formed using electroplating. The metal plated in the electroplating process can be copper, and the protective layer can be nickel-gold, but this invention does not impose any limitations on these aspects.

[0086] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention are within the protection scope of this invention.

Claims

1. A packaging method, characterized in that, Includes the following steps: Metal layers are electroplated on both sides of the substrate, and circuit patterns are etched on one of the metal layers. The chip is mounted with its back side facing the circuit pattern, and the back electrode of the chip is electrically connected to the corresponding circuit pattern area. The chip and the substrate are then encapsulated. One pillar on the front of the chip is flush with the encapsulation material, and the encapsulation material is etched to expose the circuit pattern pull area. Electroplated circuits 1, 2 and 3 are formed. Circuits 2 and 3 fill the etched area and are respectively interconnected with the front electrode of the chip through pillar 1. Circuit 1 fills the etched area and is interconnected with the back electrode of the chip through the circuit pattern, encapsulating each circuit. Through-holes are vertically etched into the encapsulation surface to expose the electrical leads of the circuit pattern; Cut into packaged product units.

2. The packaging method according to claim 1, characterized in that, The package is divided into two parts, A and B. The chips in the two parts are connected by Line 1, Line 2, Line 3 and the circuit pattern area to form two circuit half-bridges. The half-bridges are electrically connected to form a parallel circuit structure of the package chips.

3. The packaging method according to claim 2, characterized in that, The unetched metal layer on the substrate is flush with and exposed to the package, and covered by an electroplated pad.

4. The packaging method according to claim 2, characterized in that, The exposed circuit pattern electrical terminals of the vias are covered with a coating to prevent oxidation.

5. The packaging method according to claim 4, characterized in that, The electroplated conductive pillars inside the through-hole are filled to the surface of the package to form external leads.

6. A packaging structure, comprising a packaging body, characterized in that, The package contains: The substrate has metal layers electroplated on both sides of the substrate. Circuit patterns are etched on one metal layer, and the other metal layer is flush with and exposed on one surface of the package. The chip is mounted with its back side facing the circuit pattern. The electrodes on the back of the chip are electrically connected to the corresponding circuit pattern area. The front of the chip is plated with a pillar. Lines 1, 2 and 3, and lines 2 and 3 are interconnected with the front electrode of the chip via post 1; line 1 is interconnected with the back electrode of the chip via the circuit pattern. A via exposes the circuit pattern leads to the opposite surface of the exposed metal layer outside the package.

7. The packaging structure according to claim 6, characterized in that, The package is divided into two parts, A and B. The two chip parts are connected by line one, line two, line three and circuit pattern area to form two circuit half bridges. The half bridges are electrically connected to form a chip parallel circuit structure.

8. The packaging structure according to claim 7, characterized in that, The unetched metal layer on the substrate is flush with and exposed to the package, and covered by an electroplated pad.

9. The packaging structure according to claim 7, characterized in that, The exposed circuit pattern electrical terminals of the vias are covered with a coating to prevent oxidation.

10. The packaging structure according to claim 9, characterized in that, The electroplated conductive pillars inside the through-hole are filled to the surface of the package to form external leads.

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