Bonding assemblies and methods of forming the same

Abstract

A bonded assembly can be formed by bonding a device wafer and a carrier wafer. The device wafer includes semiconductor devices, metal interconnect structures, and a device-side dielectric bonding material layer. The carrier wafer includes a carrier substrate, a buffer layer of amorphous or microcrystalline material (e.g., polysilicon or amorphous silicon) formed at least on a bevel of the carrier substrate, and a carrier-side dielectric bonding material layer that can be configured to provide a controlled warpage to match the warpage of the device wafer. The buffer layer enhances charge dissipation during surface activation, plasma treatment, and water rinse processes, thereby reducing electrostatic damage to the semiconductor devices in the device wafer. Additionally, the buffer layer can provide a heat dissipation path during bonding to prevent overheating of the semiconductor devices. Embodiments of the present disclosure also relate to bonded assemblies and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this disclosure relate to joining components and methods of forming the same. Background Technology

[0002] Due to the low conductivity of the two dielectric layers, related device wafer bonding methods using bonding between two dielectric layers often result in charge accumulation at the wafer device interface. This charge accumulation at the wafer device interface can damage the semiconductor devices within the bonded wafer. Furthermore, shape mismatch between the carrier wafer and the device wafer can lead to uneven bond strength. This mismatch can increase the variability of the overlay process in subsequent processing steps. Additionally, the limited thermal conductivity in the bonding layer can cause heat buildup during device operation in some individually bonded dies after dicing. Therefore, a method for providing uniform wafer bonding is desired. Summary of the Invention

[0003] Embodiments of this disclosure provide a method for forming a bonding assembly, comprising: providing a device wafer including a semiconductor device and a metal interconnect structure embedded in a dielectric material layer, and having a device-side dielectric bonding material layer on a front side of the device wafer; depositing a buffer layer at least on a slope of a carrier substrate including a carrier substrate material; depositing a carrier-side dielectric bonding material layer on a front side of the carrier substrate above the buffer layer; and bonding the carrier-side dielectric bonding material layer to the device-side dielectric bonding material layer by a dielectric-to-dielectric bonding.

[0004] Another embodiment of this disclosure provides a method for forming a bonding assembly, comprising: providing a device wafer including a semiconductor device and a metal interconnect structure embedded in a dielectric material layer, and having a device-side dielectric bonding material layer on a front side of the device wafer; depositing a buffer layer comprising an amorphous or microcrystalline material on at least a slope of a carrier substrate including a carrier substrate material; providing a carrier wafer by depositing a carrier-side dielectric bonding material layer on a front side of the carrier substrate above the buffer layer; performing a wafer rinsing process on the carrier wafer, wherein the buffer layer contacts a conductive surface of a processing device to release charge from the buffer layer; and bonding the carrier-side dielectric bonding material layer to the device-side dielectric bonding material layer by dielectric-to-dielectric bonding.

[0005] Another embodiment of this disclosure provides a bonding assembly, comprising: a device wafer including a semiconductor device, a metal interconnect structure embedded in a dielectric material layer, and a device-side dielectric bonding material layer located on the front side of the device wafer; and a carrier wafer including a carrier substrate, a buffer layer, and a carrier-side dielectric bonding material layer, the buffer layer comprising an amorphous or microcrystalline material and disposed at least on a slope of the carrier substrate, the carrier-side dielectric bonding material layer being disposed above the front side of the carrier substrate and bonded to the device-side dielectric bonding material layer by dielectric-to-dielectric bonding. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. Various components may not be drawn to scale, and some components may be omitted for clarity.

[0007] Figure 1A This is a vertical cross-sectional view of a device wafer 100 formed by depositing a device-side dielectric bonding material layer 80 on a device substrate (60, 50) according to an embodiment of the present disclosure.

[0008] Figure 1B This is a vertical cross-sectional view of the carrier substrate 910 after a buffer layer 920 has been deposited on the carrier substrate 910 according to an embodiment of the present disclosure.

[0009] Figure 1C This is a vertical cross-sectional view of a carrier wafer 900 formed by depositing a carrier-side dielectric bonding material layer 980 on a carrier substrate 910 according to an embodiment of the present disclosure.

[0010] Figure 1D This is a vertical cross-sectional view of a first exemplary structure after the device wafer 100 has been placed on a wafer washing apparatus and after the carrier wafer 900 has been placed above the device wafer 100, according to embodiments of the present disclosure.

[0011] Figure 1E This is a vertical cross-sectional view of a first exemplary structure at the start of a water rinsing process according to an embodiment of the present disclosure.

[0012] Figure 1F This is a vertical cross-sectional view of a first exemplary structure at the end of a water rinsing process according to an embodiment of the present disclosure.

[0013] Figure 1G This is a vertical cross-sectional view of a first exemplary structure after performing a bonding annealing process according to an embodiment of the present disclosure.

[0014] Figure 2AThis is a vertical cross-sectional view of a second exemplary structure according to embodiments of the present disclosure, after the carrier wafer 900 has been placed on a wafer washing apparatus and after the device wafer 100 has been placed above the carrier wafer 900.

[0015] Figure 2B This is a vertical cross-sectional view of a second exemplary structure at the start of a water rinsing process according to an embodiment of the present disclosure.

[0016] Figure 2C This is a vertical cross-sectional view of a second exemplary structure at the end of a water rinsing process according to an embodiment of the present disclosure.

[0017] Figure 2D This is a vertical cross-sectional view of a second exemplary structure after performing a bonding annealing process according to an embodiment of the present disclosure.

[0018] Figure 3 This is a vertical cross-sectional view of a third exemplary structure after performing a bonding annealing process according to an embodiment of the present disclosure.

[0019] Figure 4A This is a vertical cross-sectional view of a fourth exemplary structure during a water rinsing process according to an embodiment of the present disclosure.

[0020] Figure 4B This is a vertical cross-sectional view of a fourth exemplary structure after performing a bonding annealing process according to an embodiment of the present disclosure.

[0021] Figure 5A This is a vertical cross-sectional view of a fifth exemplary structure during a water rinsing process according to an embodiment of the present disclosure.

[0022] Figure 5B This is a vertical cross-sectional view of a fifth exemplary structure after performing a bonding annealing process according to an embodiment of the present disclosure.

[0023] Figure 6A This is a vertical cross-sectional view of a sixth exemplary structure during a water rinsing process according to an embodiment of the present disclosure.

[0024] Figure 6B This is a vertical cross-sectional view of a sixth exemplary structure after performing a bonding annealing process according to an embodiment of the present disclosure.

[0025] Figure 7 This is a first flowchart illustrating the steps for forming a bonding assembly according to an embodiment of the present disclosure.

[0026] Figure 8 This is a second flowchart illustrating the steps for forming a bonding assembly according to an embodiment of the present disclosure. Detailed Implementation

[0027] This disclosure describes various embodiments of the invention to illustrate its parts, components, and arrangements. These embodiments are exemplary and are not intended to limit the scope of the claims. Unless otherwise specified, the drawings are not drawn to scale. Elements having the same reference numerals represent the same elements and are assumed to have the same material composition and the same thickness range unless explicitly indicated otherwise. Unless explicitly disclosed otherwise, it is assumed that all parts of the original embodiments exist in any derived embodiments. Unless explicitly stated otherwise, embodiments in which multiple instances of any said element are repeated are expressly contemplated. Embodiments in which non-essential elements are omitted, even if such embodiments are not explicitly disclosed, are known in the art.

[0028] Additionally, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the geometrical features between the elements as shown in the figures. The first physical element is “embedded” within the second physical element if the entire volume of the first element is completely contained within a hypothetical volume. This hypothetical volume is defined by a set of surfaces that surround the entire outer surface of the second element, having the smallest total surface area among all such surrounding surfaces, and being topologically homeomorphic to a sphere. This set of hypothetical surfaces completely surrounds any openings or recesses on the outer surface of the second element, using the surface segments with the smallest possible area among all segments that close these openings. Besides the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation.

[0029] Structures or devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, the material composition of each structural element is assumed to be homogeneous. Unless otherwise expressly stated, each element having the same reference numerals is assumed to have the same material composition and thickness within the same thickness range. Unless otherwise expressly stated, all top and bottom surfaces are assumed to be horizontal or substantially horizontal (i.e., at an angle within 15 degrees to the horizontal plane) and without any steps. Unless otherwise specified or known to be performed at different temperatures, all measurements are assumed to be performed at standard temperature and pressure (20°C, 1 atm).

[0030] As used herein, removal of the first material is "selective" to the second material if the removal rate of the first material is at least three times greater than the removal rate of the second material. Unless otherwise specified, "selective removal" means that the selectivity ratio can be equal to or greater than 3, 10, 100, or even 1000. The first and second surfaces are "perpendicularly coincident" if one surface lies directly above or below another surface such that a perpendicular or substantially perpendicular plane encompasses both surfaces. A perpendicular plane is defined as a two-dimensional surface consisting of an uncountable infinite number of perpendicular lines and having a uniform one-dimensional horizontal cross-section that remains unchanged under perpendicular translation. If the cross-section is linear, the plane is Euclidean; otherwise, it is non-Euclidean. A substantially perpendicular line is a line that deviates from a perfectly perpendicular orientation by less than 5 degrees. A substantially perpendicular plane comprises a continuous set of such lines.

[0031] Embodiments of this disclosure may provide a bonding assembly including a device wafer and a carrier wafer, and a method of forming the same. The carrier wafer includes a buffer layer deposited on a carrier substrate. The buffer layer includes an amorphous or microcrystalline material, such as polycrystalline silicon or amorphous silicon. The buffer layer mitigates charge accumulation at the wafer device interface during the bonding process. The buffer layer reduces the risk of electrostatic damage to the semiconductor devices in the device wafer. A carrier-side dielectric bonding material layer (optionally including stressed silicon nitride) induces controlled warpage to match the shape of the device wafer. The carrier-side dielectric bonding material layer enhances bonding strength and coverage performance. The buffer layer provides higher thermal conductivity than the carrier-side dielectric bonding material layer. The buffer layer facilitates heat dissipation near the bonding interface during high-temperature processes, such as bonding annealing. A back-side capping layer optionally enhances charge dissipation. The bonding assembly achieves improved bonding strength, precise capping alignment, reduced charge accumulation, and enhanced thermal management. Various aspects of this disclosure will now be described with reference to the accompanying drawings.

[0032] refer to Figure 1A The image shows a device wafer 100, which includes a device-containing substrate (60, 50). Typically, the device-containing substrate (60, 50) can include any type of device-containing substrate known in the art, provided that the device-containing substrate (60, 50) includes a semiconductor device 20. In one embodiment, the device-containing substrate (60, 50) can include a device carrier substrate 60 and a device-containing structure 50.

[0033] Device carrier substrate 60 may include a semiconductor substrate (such as a single-crystal semiconductor wafer) or any other type of carrier substrate. Device-containing structure 50 includes a semiconductor device 20 and may include metal interconnect structures (38, 48) providing electrical connections to the semiconductor device 20. In a non-limiting illustrative example, device-containing structure 50 may include the semiconductor device 20 located on a thin semiconductor substrate 10, a front metal interconnect structure 38 embedded in a front dielectric layer 30 and electrically connected to the semiconductor device 20, and a back metal interconnect structure 48 embedded in a back dielectric layer 40 and electrically connected to the semiconductor device 20. Optionally, one or more of the thin semiconductor substrate 10, the front metal interconnect structure 38, and the back metal interconnect structure 48 may be omitted. Alternatively, device carrier substrate 60 may include a semiconductor substrate on which the semiconductor device 20 is formed. Typically, device carrier substrate 60 may include any structure suitable for mechanically supporting the semiconductor device 20. The front metal interconnect structure 38 and the back metal interconnect structure 48 provide electrical connections to the semiconductor device 20.

[0034] According to aspects of this disclosure, a device-side dielectric bonding material layer 80 is deposited on the front side of a device substrate (60, 50) to provide a device wafer 100. Thus, the device wafer 100 includes a semiconductor device 20 and metal interconnect structures (38, 48) embedded in the dielectric material layer, and has the device-side dielectric bonding material layer 80 on its front side. The device-side dielectric bonding material layer 80 includes a dielectric material suitable for dielectric-to-dielectric bonding. For example, the device-side dielectric bonding material layer 80 may include silicon nitride, undoped silicate glass, or doped silicate glass. In one embodiment, the device-side dielectric bonding material layer 80 includes a stress-generating dielectric material, such as silicon nitride generating tensile stress or silicon nitride generating compressive stress. In this embodiment, the stress-generating dielectric material can be used to reduce the overall warpage of the device wafer 100. The thickness of the device-side dielectric bonding material layer 80 can range from 1 nm to 2000 nm, but smaller or larger thicknesses can also be used. The thermal conductivity of the device-side dielectric bonding layer 80 can range from 0.7 W / m·K to 30 W / m·K, depending on the selected material (e.g., 0.7-1.5 W / m·K for undoped or doped silicate glass; 8-30 W / m·K for silicon nitride). According to aspects of this disclosure, the material of the device-side dielectric bonding layer 80 can be selected to provide high thermal conductivity between the two bonding layers and to effectively dissipate heat on the subsequently formed bonding assembly.

[0035] refer to Figure 1BA carrier substrate 910 is provided. The carrier substrate 910 may include a semiconductor material, such as single-crystal silicon. The carrier substrate 910 includes a carrier substrate material, which may be a semiconductor material. For example, the carrier substrate 910 may include a commercially available single-crystal silicon wafer. The thickness of the carrier substrate 910 may range from 300 micrometers to 1000 micrometers, but smaller or larger thicknesses may also be used.

[0036] According to aspects of this disclosure, a buffer layer 920 may be deposited at least on a slope of the carrier substrate 910. As used herein, a “buffer layer” refers to a layer configured to provide functionality not present in adjacent layers to alter the overall characteristics of the structure. According to aspects of this disclosure, the buffer layer 920 may be a charge dissipation layer that facilitates charge dissipation to prevent charge accumulation during wafer processing, thereby reducing the risk of electrostatic damage to the semiconductor device 20. Additionally, the buffer layer 920 may be a high thermal conductivity layer that facilitates lateral heat diffusion during heat transfer within the subsequently formed bonding assembly. Furthermore, the buffer layer 920 may be a stress relief layer that absorbs stress between the components of the bonding assembly and provides enhanced structural support within the bonding assembly. Thus, the buffer layer 920, as a multifunctional layer, enhances the performance and reliability of the bonding assembly and further improves the process yield of in-process structures such as bonding assemblies of two wafers during manufacturing. As used herein, a “slope” of the substrate refers to an edge region of the substrate, typically characterized by a sloping or circular surface connecting the front and back surfaces, which may contact processing equipment during manufacturing.

[0037] Typically, a buffer layer 920 may be deposited on a carrier substrate 910, covering at least a bevel of the carrier substrate 910, and optionally covering the front and back sides of the carrier substrate 910. In one embodiment, the buffer layer 920 covers the entire bevel of the carrier substrate 910. In one embodiment, the buffer layer 920 covers the entire back side of the carrier substrate 910. In one embodiment, the buffer layer 920 covers the entire front side of the carrier substrate 910. In one embodiment, the buffer layer 920 covers the entire physically exposed surface of the carrier substrate 910. In one embodiment, the buffer layer 920 may be deposited using a single conformal deposition process, such as chemical vapor deposition. Optionally, at least two conformal deposition processes may be used to deposit the buffer layer 920, such that the support area used to support the carrier substrate 910 in the deposition tool is varied in different deposition processes. Using multiple deposition processes ensures that the entire surface of the carrier substrate 910 is covered by the buffer layer 920.

[0038] Buffer layer 920 comprises an amorphous or microcrystalline material configured to enhance charge release through an amorphous or microcrystalline surface structure. In one embodiment, the amorphous or microcrystalline material of buffer layer 920 is a semiconductor material and comprises polycrystalline silicon or amorphous silicon. Depending on the material composition (such as polycrystalline silicon or amorphous silicon), buffer layer 920 may have a thickness ranging from 1 nm to 1000 nm and may exhibit properties from... to The electrical conductivity ranges from 50 W / m·K to 150 W / m·K. Compared to a flat single-crystal surface, amorphous or microcrystalline structures enhance charge release during processes such as plasma treatment or water rinsing by providing a surface morphology that promotes charge dissipation. According to aspects of this disclosure, the material of the buffer layer 920 can be selected to provide high thermal conductivity between the two bonding layers and to effectively dissipate heat on the subsequently formed bonding assembly.

[0039] In one embodiment, the buffer layer 920 may comprise polysilicon, which can be provided with a thickness ranging from 1 nm to 1000 nm. to The electrical conductivity ranges from 50 W / m·K to 100 W / m·K. In another embodiment, the buffer layer 920 may comprise amorphous silicon, which can provide conductivity from... to Electrical conductivity in the range of [value missing] and thermal conductivity in the range of 1 W / m·K to 4 W / m·K. Typically, single-crystal silicon with low dopant concentrations used for typical silicon wafers provides [value missing] electrical conductivity in the range of [value missing] and thermal conductivity in the range of 1 W / m·K to 4 W / m·K. to The electrical conductivity ranges from 130 W / m·K to 150 W / m·K. According to aspects of this disclosure, the buffer layer 920 reduces charge accumulation within the carrier substrate 910 by facilitating charge release through the textured surface. Typically, the buffer layer 920 has a higher electrical conductivity than the subsequently formed carrier-side dielectric bonding material layer.

[0040] refer to Figure 1C A carrier-side dielectric bonding material layer 980 may be deposited over the carrier substrate 910. The carrier-side dielectric bonding material layer 980 may be deposited on the front side of the carrier substrate 910 and over the front portion of the buffer layer 920 to provide a carrier wafer 900. Therefore, the carrier wafer 900 may include the carrier substrate 910 and the buffer layer 920, and may also include the carrier-side dielectric bonding material layer 980 located on the front side of the carrier substrate 910.

[0041] The carrier-side dielectric bonding material layer 980 includes a dielectric material suitable for dielectric-to-dielectric bonding. For example, the carrier-side dielectric bonding material layer 980 may include silicon nitride, undoped silicate glass, or doped silicate glass. Silicon nitride has a thermal conductivity in the range of 8 W / m·K to 30 W / m·K. Undoped and doped silicate glasses have thermal conductivity in the range of 0.7 W / m·K to 1.5 W / m·K. Therefore, the buffer layer 920 of this disclosure can provide a higher thermal conductivity than the carrier-side dielectric bonding material layer 980 and serves as a heat conduction path during subsequent processing steps. The thickness of the carrier-side dielectric bonding material layer 980 can range from 1 nm to 1000 nm, but smaller or larger thicknesses can also be used.

[0042] In one embodiment, the carrier-side dielectric bonding layer 980 includes a stress-generating dielectric material, such as silicon nitride generating tensile stress or silicon nitride generating compressive stress. In this embodiment, the stress-generating dielectric material can be used to match the overall warpage of the carrier wafer 900 with the warpage of the device wafer 100. In one embodiment, the carrier-side dielectric bonding layer 980 may include stretched silicon nitride and provide positive warpage to the carrier substrate 910, i.e., it can make the top surface of the carrier substrate 910 a concave surface and the bottom surface of the carrier substrate 910 a convex surface. In another embodiment, the carrier-side dielectric bonding layer 980 may include compressed silicon nitride and provide negative warpage to the carrier substrate 910, i.e., it can make the top surface of the carrier substrate 910 a convex surface and the bottom surface of the carrier substrate 910 a concave surface. By controlling the stress and thickness of the carrier-side dielectric bonding material layer 980 to change the warpage of the carrier substrate 910 to match the pre-existing warpage in the device wafer 100, the bonding strength between the device wafer 100 and the carrier wafer 900 can be improved.

[0043] Typically, the carrier wafer 900 includes a carrier substrate 910, a buffer layer 920, and a carrier-side dielectric bonding material layer 980. The buffer layer 920 comprises an amorphous or microcrystalline material and is disposed on at least a sloped surface of the carrier substrate 910. The carrier-side dielectric bonding material layer 980 is disposed above the front side of the carrier substrate 910. The carrier-side dielectric bonding material layer 980 is deposited on the front side of the carrier substrate 910 above the buffer layer 920.

[0044] Due to its amorphous or microcrystalline structure, the buffer layer 920 facilitates charge dissipation during subsequent processing steps, such as plasma treatment or water rinsing. This charge dissipation can prevent or at least mitigate electrostatic damage to the semiconductor device 20 in the device wafer 100. The carrier-side dielectric bonding material layer 980 (preferably comprising stressed silicon nitride) can be configured to induce controlled deformation through tensile or compressive stress to conform to the shape of the device wafer 100, enhancing bonding strength and coverage performance. The combination of the buffer layer 920 and the carrier-side dielectric bonding material layer 980 allows the carrier wafer 900 to conform to the contour of the physically exposed surface of the device-side dielectric bonding material layer 80 in the device wafer 100 and provides a thermal path near the bonding interface. The buffer layer 920 can also provide a higher thermal conductivity than the carrier-side dielectric bonding material layer 980.

[0045] Surface activation processes can be performed on the physically exposed surfaces of the buffer layer 920, such as the back surface of the buffer layer 920 and a section of the slope of the charge release layer 920. According to aspects of this disclosure, the surface morphology of the amorphous or microcrystalline material, relative to the surface morphology of a flat single-crystal surface (a comparative single-crystal material having the same material composition as the buffer layer 920), can enhance the release of excess charge from the buffer layer 920 during the surface activation process. In an illustrative example, the surface activation process may include a plasma treatment process that forms silanol radicals on the physically exposed surfaces of the buffer layer 920. The amorphous or microcrystalline material provides an enhanced charge release rate for the buffer layer 920 during the plasma treatment process, relative to a single-crystal material having the same material composition as the amorphous or microcrystalline material.

[0046] This surface activation process can prepare the carrier wafer 900 for bonding by altering surface chemistry and removing contaminants, while addressing potential charge buildup issues that could lead to electrostatic damage during subsequent steps, such as water rinsing or plasma exposure. The carrier substrate 910 is typically composed of a semiconductor material, such as single-crystal silicon, providing a surface with... to The substrate is mechanically robust with inherent electrical conductivity in the range of approximately 130 W / m·K to 150 W / m·K. However, the native oxide or smooth surface characteristics on the substrate 910 may hinder effective charge dissipation at critical contact points with the processing equipment.

[0047] Compared to a flat monocrystalline silicon surface of the same material composition, a buffer layer 920, including amorphous silicon or microcrystalline silicon, can enhance the release of excess charge during surface activation processes. This enhancement stems from differences in microstructure: in polycrystalline silicon (a preferred embodiment of buffer layer 920), high-density defects exist at grain boundaries between small grains, forming conductive leakage paths that make it easier for charge to dissipate to grounding devices or recombine. In amorphous silicon, the disordered atomic structure introduces a higher defect density, such as dangling bonds, which act as recombination centers for charge carriers, promoting the neutralization of excess charge. These structural elements ensure that buffer layer 920 provides a dedicated dissipation path above the surface of the potential insulating substrate, reducing the risk of electrostatic damage to the semiconductor device 20 in device wafer 100.

[0048] While the surface morphology of amorphous or microcrystalline materials may contribute to charge behavior, the primary mechanism for enhancing charge dissipation is likely defect-mediated conduction, rather than just roughness, as excessive roughness can hinder charge dissipation in some cases. In an illustrative example, the surface activation process may include a plasma treatment that functionalizes the exposed surface of the buffer layer 920, such as by forming silanol groups (Si-OH) through interaction with oxygen or water vapor radicals. This functionalization facilitates dielectric-to-dielectric bonding and leverages the material's structure to improve charge release relative to monocrystalline silicon, mitigating plasma-induced damage issues during the processing steps.

[0049] refer to Figure 1D This illustration shows a first exemplary structure after device wafer 100 has been placed on a wafer rinsing apparatus and after carrier wafer 900 has been placed above device wafer 100. The wafer rinsing apparatus may include a main support plate 710, a conductive retainer wall 712, a conductive contact ring 713 configured to contact device wafer 100 or carrier wafer 900, and a bottom flange 714 surrounding a bottom spray head 720. Additional wafer nozzles (not shown) are provided around and / or above the conductive contact ring 713. The conductive contact ring 713 is electrically grounded, for example, through the conductive retainer wall 712, to facilitate the discharge of excess charge from device wafer 100 and carrier wafer 900. The bottom spray head 720 may be configured to spray water onto the back side of the wafer located on the conductive contact ring 713. Typically, one of the device wafer 100 and the carrier wafer 900 can be disposed on the conductive contact ring 713, and the other of the device wafer 100 and the carrier wafer 900 can be held above the wafer washing apparatus, such that the two dielectric bonding material layers (80, 980) face each other. In the example shown, the device wafer 100 can be disposed on the wafer washing apparatus, and the carrier wafer 900 can be disposed above the device wafer 100, with a vertical spacing between them. The vertical spacing can be in the range of 1 mm to 30 mm, but smaller or larger vertical spacing can also be used.

[0050] A water rinsing process forms silanol groups on the surfaces of dielectric bonding material layers (80, 980) to fabricate device wafer 100 and carrier wafer 900 for dielectric-to-dielectric bonding. The water rinsing process removes contaminants from the surfaces of device wafer 100 and carrier wafer 900. The water rinsing process dissipates the charge accumulated during previous surface activation to prevent electrostatic damage to the semiconductor device 20 in device wafer 100. Figure 1E An exemplary discharge path EDP is illustrated. Back-side deionized water 990 is sprayed from a bottom nozzle 720 toward the back surface of device wafer 100. Front-side deionized water 90 is sprayed from an upper nozzle 730 (including a top nozzle 73A and a side nozzle 73B) toward the exposed surface of carrier wafer 900 and the top surface of device wafer 100. The deionized water flows outward with positive radial momentum toward conductive contact ring 713. Conductive contact ring 713 is electrically connected to ground via conductive retainer wall 712. Grounded conductive contact ring 713 provides discharge of excess charge from device wafer 100 and carrier wafer 900.

[0051] like Figure 1E As illustrated in the illustration, a water rinsing process provides water molecules to covalently bond two silanol groups to the surface of a dielectric bonding material layer 980 in a carrier wafer 900. During the water rinsing process following surface activation, silanol groups are formed on the dielectric bonding material layer 980, which comprises silicon nitride or silicate glass. The silanol groups are formed on a dielectric bonding material layer 80 in a device wafer 100 to enhance bonding compatibility. The silanol groups enhance the hydrophilicity of the dielectric bonding material layers (80, 980) to improve contact with deionized water. Improved contact with deionized water facilitates charge transfer to the grounded conductive contact ring 713. During subsequent bonding steps, the silanol groups promote hydrogen bonding or covalent bridging to strengthen the bonding interface between the device wafer 100 and the carrier wafer 900.

[0052] The buffer layer 920 in the carrier wafer 900 is composed of amorphous silicon or polycrystalline silicon, promoting charge dissipation during the water rinsing process. The carrier substrate 910 (typically monocrystalline silicon) provides conductivity in the... to A mechanically robust substrate within a range. The carrier substrate 910 exhibits thermal conductivity in the range of 130 W / m·K to 150 W / m·K. The native oxide on the carrier substrate 910 insulates the contact points from the processing equipment. The smooth surface characteristics of the carrier substrate 910 hinder efficient charge dissipation. A buffer layer 920 covers at least the bevel of the carrier substrate 910 and optionally covers the front and back sides. The buffer layer 920 maintains a position from... to The conductivity is within a certain range. Buffer layer 920 ensures that charge flows through deionized water to the grounded conductive contact ring 713.

[0053] Compared to a flat monocrystalline silicon surface of the same material composition, the buffer layer 920, made of amorphous or polycrystalline silicon, enhances charge dissipation. The polycrystalline silicon in the buffer layer 920 contains grain boundaries with a high defect density. These grain boundaries form conductive leakage paths, allowing charge to dissipate to grounding devices or recombine. The amorphous silicon in the buffer layer 920 has a disordered atomic structure with dangling bonds. These dangling bonds serve as recombination centers for charge carriers, facilitating the neutralization of excess charge. The structural features of the buffer layer 920 provide dedicated dissipation paths above the potentially insulating surface of the carrier substrate 910. The buffer layer 920 reduces the risk of electrostatic discharge damage to the semiconductor device 20 in the device wafer 100.

[0054] The surface morphology of the amorphous or polycrystalline silicon in the buffer layer 920 increases the surface area for charge transfer to deionized water. Defect-mediated conduction primarily drives the enhanced charge dissipation in the buffer layer 920. In some cases, excessive surface roughness in the buffer layer 920 may hinder charge dissipation. The buffer layer 920 exhibits thermal conductivity ranging from 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or 1 W / m·K to 4 W / m·K (for amorphous silicon). The buffer layer 920 provides higher thermal conductivity than the carrier-side dielectric bonding material layer 980, ranging from 0.7 W / m·K to 30 W / m·K. The buffer layer 920 facilitates heat dissipation near the bonding interface during high-temperature processes such as bonding annealing. The buffer layer 920 ensures robust charge and thermal management to improve the reliability and yield of the bonded wafer structure. A water rinsing process is performed while the device wafer 100 and the carrier wafer 900 are not in contact with each other.

[0055] refer to Figure 1FThe water rinsing process can continue while reducing the vertical spacing between device wafer 100 and carrier wafer 900 until the mating surfaces of device-side dielectric bonding material layer 80 and carrier-side dielectric bonding material layer 980 contact each other. Optionally, at least one drying process can be performed intermittently during the water rinsing process, which leaves silanol groups on the surfaces of device-side dielectric bonding material layer 80 and carrier-side dielectric bonding material layer 980. According to aspects of this disclosure, after device wafer 100 directly contacts carrier wafer 900, buffer layer 920 serves as a component of discharge path EDP. A flat or substantially flat mating surface (with unevenness due to the warpage of wafers (100, 900)) is provided between device wafer 100 and carrier wafer 900. The water rinsing process can be terminated after device wafer 100 contacts carrier wafer 900 at the contact surface. A post-bonding wafer cleaning process can be performed on the bonding assembly. During the post-bonding wafer cleaning process, the charge release layer 920 contacts the conductive surface of the processing equipment (e.g., a grounding chuck or retaining ring), thereby serving as a component of the discharge path (EDP) to release accumulated charge and prevent electrostatic damage to the semiconductor device 20. The post-bonding wafer cleaning process differs from the pre-bonding water rinsing process and enables the safe handling of bonded components in downstream manufacturing steps.

[0056] refer to Figure 1G The bonding annealing process induces covalent bonding between the device-side dielectric bonding material layer 80 of device wafer 100 and the carrier-side dielectric bonding material layer 980 of carrier wafer 900. Following surface preparation, a dielectric-to-dielectric bonding process brings the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980 into contact. Surface preparation processes (such as the plasma activation process discussed above) form silanol groups (Si-OH) on the surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. A water rinsing process increases the density of silanol groups on the surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. The water rinsing process removes surface contaminants from the device wafer 100 and the carrier wafer 900. Initial contact occurs when hydrogen bonds form between the silanol groups on the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. The bonding annealing process involves a reaction at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. The silanol groups are dehydrated. Dehydration releases water molecules from the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980.

[0057] In one embodiment, silicon nitride-on-silicon nitride bonding connects the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. A plasma activation process forms silanol (Si-OH) or amine groups (Si-OH) on the silicon nitride surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. The water rinsing process increases the density of silanol or amine groups on the silicon nitride surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Initial contact forms hydrogen bonds between the silanol or amine groups on the silicon nitride surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. The bonding annealing process for silicon nitride-to-silicon nitride bonding involves heating at a temperature from 350°C to 450°C for 1 to 2 hours. High-purity nitrogen with an oxygen content of less than 1 ppm is provided as an ambient atmosphere during the silicon nitride-to-silicon nitride bonding annealing process to prevent oxidation. The bonding annealing process is performed via methods such as... The reaction causes the silanol or amino groups to dehydrate, forming Si-N-Si or Si-O-Si covalent bonds at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Dehydration releases water vapor from the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980.

[0058] In another embodiment, silicon oxide-to-silicon oxide bonding connects the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. A plasma activation process forms silanol groups (Si-OH) on the silicon oxide surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. A water rinsing process increases the density of silanol groups on the silicon oxide surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Initial contact forms hydrogen bonds between the silanol groups on the silicon oxide surfaces of the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding layer 980. The bonding annealing process for silicon oxide-to-silicon oxide bonding involves heating at a temperature of 250°C to 350°C for 2 to 3 hours. During the bonding annealing process for silicon oxide-to-silicon oxide bonding, a clean, dry atmosphere with a nitrogen or water vapor content of less than 5 ppm is provided. The bonding annealing process is carried out via a reaction... The silanol groups are dehydrated to form Si-O-Si covalent bonds at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Dehydration creates a void-free interface by removing water molecules from the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980.

[0059] A buffer layer 920, composed of polycrystalline or amorphous silicon, conducts heat during the bonding annealing process to dissipate heat uniformly across the carrier wafer 900. The buffer layer 920 exhibits a thermal conductivity ranging from 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or from 1 W / m·K to 4 W / m·K (for amorphous silicon). The buffer layer 920 provides a higher thermal conductivity than the carrier-side dielectric bonding material layer 980, which exhibits a thermal conductivity ranging from 0.7 W / m·K to 30 W / m·K. The buffer layer 920 prevents thermal damage to the semiconductor device 20 in the device wafer 100 during the bonding annealing process. The buffer layer 920 (with a thermal conductivity ranging from...) to Within the range of the bonding process, the charge is dissipated to the grounded conductive contact ring 713 during surface activation and water rinsing. The polycrystalline silicon in the buffer layer 920 contains grain boundaries that form conductive leakage paths for charge dissipation. The amorphous silicon in the buffer layer 920 contains dangling bonds that serve as recombination centers for charge neutralization. The buffer layer 920 prevents electrostatic discharge damage to the semiconductor device 20 in the device wafer 100.

[0060] A carrier-side dielectric bonding material layer 980, including stress silicon nitride, induces controlled warpage in the carrier wafer 900 to align with the warpage of the device wafer 100. This controlled warpage ensures uniform contact pressure during the bonding annealing process at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. This uniform contact pressure minimizes voids at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. A buffer layer 920 and the carrier-side dielectric bonding material layer 980 provide different functions in the carrier wafer 900 to mitigate charge buildup, thermal stress, and bonding variability. The device wafer 100 and the carrier wafer 900 achieve robust bonding through the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Due to the controlled warpage, the device wafer 100 and the carrier wafer 900 maintain precise overlay alignment.

[0061] The bonding components (100, 900) disclosed herein may include: a device wafer 100 including a semiconductor device 20, metal interconnect structures (38, 48) embedded in a dielectric material layer, and a device-side dielectric bonding material layer 80 located on its front side; and a carrier wafer 900 including a carrier substrate 910, a buffer layer 920 and a carrier-side dielectric bonding material layer 980, wherein the buffer layer 920 comprises an amorphous or microcrystalline material and is disposed on at least a slope of the carrier substrate 910, and the carrier-side dielectric bonding material layer 980 is disposed above the front side of the carrier substrate 910 and is bonded to the device-side dielectric bonding material layer 80 via dielectric-to-dielectric bonding.

[0062] In one embodiment, the buffer layer 920 covers the front side and / or the back side of the carrier substrate 910. In one embodiment, the amorphous or microcrystalline material includes polycrystalline silicon or amorphous silicon.

[0063] In one embodiment, the buffer layer 920 comprises a material having a higher thermal conductivity than the material of the carrier-side dielectric bonding material layer 980.

[0064] In one embodiment, the carrier-side dielectric bonding material layer 980 comprises silicon nitride, which causes warping of the carrier substrate 910 by tensile or compressive stress.

[0065] refer to Figure 2A The second exemplary structure positions the carrier wafer 900 on a wafer washing apparatus and positions the device wafer 100 on the carrier wafer 900 at a vertical spacing. The second exemplary structure inverts the arrangement by placing the carrier wafer 900 on the wafer washing apparatus. Figure 1D The configuration of the first exemplary structure is shown. The wafer rinsing apparatus includes a main support plate 710, a conductive retainer wall 712, a grounded conductive contact ring 713, and a bottom spray head 720. The grounded conductive contact ring 713 contacts the buffer layer 920 on the bevel or back side of the carrier wafer 900. The grounded conductive contact ring 713 is electrically connected to ground through the conductive retainer wall 712. The vertical spacing between the device wafer 100 and the carrier wafer 900 is in the range of 1 mm to 30 mm. The bottom spray head 720 directs back-side deionized water to the back surface of the carrier wafer 900. The upper spray head 730 directs front-side deionized water to the front surface of the device wafer 100 and the exposed surface of the carrier wafer 900.

[0066] refer to Figure 2B ,like Figure 1E The water rinsing process described above prepares dielectric bonding material layers (80, 980) for dielectric-to-dielectric bonding. Buffer layer 920, composed of polycrystalline or amorphous silicon, promotes charge dissipation during the water rinsing process. Buffer layer 920 (conductivity ranging from...) to Within a certain range, the charge is conducted through deionized water to the grounded conductive contact ring 713. The buffer layer 920 prevents electrostatic discharge damage to the semiconductor device 20 in the device wafer 100. The carrier substrate 910 (typically monocrystalline silicon) provides a mechanically robust substrate with conductivity ranging from... to Within the range. The native oxide on the carrier substrate 910 insulates the contact points from the processing equipment. The smooth surface characteristics of the carrier substrate 910 hinder effective charge dissipation. The buffer layer 920 covers at least the bevel of the carrier substrate 910 and optionally covers the front and back sides.

[0067] Compared to a flat monocrystalline silicon surface of the same material composition, the buffer layer 920 enhances charge dissipation. The polycrystalline silicon in the buffer layer 920 contains grain boundaries that form conductive leakage paths. These conductive leakage paths allow charge to dissipate to grounding devices or recombine. The amorphous silicon in the buffer layer 920 has a disordered atomic structure with dangling bonds. These dangling bonds in the amorphous silicon act as recombination centers for charge carriers. These recombination centers in the amorphous silicon facilitate the neutralization of excess charge. The surface morphology of the buffer layer 920 increases the surface area for charge transfer to deionized water. Defect-mediated conduction primarily drives charge dissipation in the buffer layer 920. In some cases, excessive surface roughness in the buffer layer 920 may hinder charge dissipation.

[0068] Buffer layer 920 exhibits thermal conductivity ranging from 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or 1 W / m·K to 4 W / m·K (for amorphous silicon). Buffer layer 920 provides higher thermal conductivity than the dielectric bonding material layers (80, 980), which exhibit thermal conductivity ranging from 0.7 W / m·K to 30 W / m·K. Buffer layer 920 facilitates heat dissipation near the bonding interface during high-temperature processes. Buffer layer 920 ensures robust charge and thermal management to improve the reliability and yield of the bonded wafer structure.

[0069] refer to Figure 2C ,like Figure 1F The water rinsing process continues while reducing the vertical spacing between device wafer 100 and carrier wafer 900 until the dielectric bonding material layers (80, 980) contact each other. The drying process optionally intermittently retains silanol groups on the surfaces of the dielectric bonding material layers (80, 980) during the water rinsing process. After device wafer 100 contacts carrier wafer 900, buffer layer 920 facilitates the discharge path. A substantially flat mating surface is formed between the dielectric bonding material layers (80, 980), which is uneven due to the warpage of device wafer 100 and carrier wafer 900. The water rinsing process terminates after device wafer 100 contacts carrier wafer 900 at the contact surface.

[0070] refer to Figure 2D ,like Figure 1G The bonding annealing process causes covalent bonding between the dielectric bonding material layers (80, 980). In one embodiment, using... Figure 1G The described bonding annealing process connects silicon nitride to silicon nitride bonding dielectric bonding material layers (80, 980). The bonding annealing process for silicon nitride to silicon nitride bonding involves heating at a temperature ranging from 350°C to 450°C for 1 to 2 hours. During the bonding annealing process for silicon nitride to silicon nitride bonding, a high-purity nitrogen atmosphere with an oxygen content of less than 1 ppm is provided.

[0071] In another embodiment, silicon nitride-to-silicon nitride bonding connects device-side dielectric bonding material layer 80 and carrier-side dielectric bonding material layer 980. A plasma activation process forms silanol groups (Si-OH) on the silicon oxide surfaces of device-side and carrier-side dielectric bonding material layers 80 and 980. A water rinsing process increases the density of silanol groups on the silicon oxide surfaces of device-side and carrier-side dielectric bonding material layers 80 and 980. Initial contact forms hydrogen bonds between the silanol groups on the silicon oxide surfaces of device-side and carrier-side dielectric bonding material layers 80 and 980. The bonding annealing process for silicon oxide-to-silicon oxide bonding involves heating at a temperature from 250°C to 350°C for 2 to 3 hours. During the bonding annealing process for silicon oxide-to-silicon oxide bonding, a clean, dry atmosphere with a nitrogen or water vapor content of less than 5 ppm is provided. The bonding annealing process is carried out via a reaction... The silanol groups are dehydrated to form Si-O-Si covalent bonds at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Dehydration creates a void-free interface by removing water molecules from the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980.

[0072] A buffer layer 920, composed of polycrystalline or amorphous silicon, conducts heat during the bonding annealing process to dissipate heat uniformly across the carrier wafer 900. The buffer layer 920 exhibits a thermal conductivity ranging from 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or from 1 W / m·K to 4 W / m·K (for amorphous silicon). The buffer layer 920 provides a higher thermal conductivity than the carrier-side dielectric bonding material layer 980, which exhibits a thermal conductivity ranging from 0.7 W / m·K to 30 W / m·K. The buffer layer 920 prevents thermal damage to the semiconductor device 20 in the device wafer 100 during the bonding annealing process. The buffer layer 920 (with a thermal conductivity ranging from...) to Within the range of the bonding process, the charge is dissipated to the grounded conductive contact ring 713 during surface activation and water rinsing. The polycrystalline silicon in the buffer layer 920 contains grain boundaries that form conductive leakage paths for charge dissipation. The amorphous silicon in the buffer layer 920 contains dangling bonds that serve as recombination centers for charge neutralization. The buffer layer 920 prevents electrostatic discharge damage to the semiconductor device 20 in the device wafer 100.

[0073] A carrier-side dielectric bonding material layer 980, including stress silicon nitride, induces controlled warpage in the carrier wafer 900 to align with the warpage of the device wafer 100. This controlled warpage ensures uniform contact pressure during the bonding annealing process at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. This uniform contact pressure minimizes voids at the interface between the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. A buffer layer 920 and the carrier-side dielectric bonding material layer 980 provide different functions in the carrier wafer 900 to mitigate charge buildup, thermal stress, and bonding variability. The device wafer 100 and the carrier wafer 900 achieve robust bonding through the device-side dielectric bonding material layer 80 and the carrier-side dielectric bonding material layer 980. Due to the controlled warpage, the device wafer 100 and the carrier wafer 900 maintain precise overlay alignment.

[0074] refer to Figure 3 A third exemplary structure according to an embodiment of this disclosure illustrates a bonding assembly of a device wafer 100 and a carrier wafer 900 after a bonding annealing process. The focus is on the non-planar nature of the bonding interface due to pre-existing warpage in the device wafer 100. The device wafer 100 includes a device-containing substrate (60, 50) having a semiconductor device 20. The device wafer 100 includes metal interconnect structures (38, 48) embedded in a dielectric material layer. The device-side dielectric bonding material layer 80 has a concave bonding surface caused by inherent warpage.

[0075] The carrier wafer 900 includes a carrier substrate 910 composed of monocrystalline silicon. The carrier wafer 900 includes a buffer layer 920 made of an amorphous or microcrystalline material (such as polycrystalline silicon or amorphous silicon) covering at least a beveled surface of the carrier substrate 910. The carrier-side dielectric bonding material layer 980 is characterized by a convex bonding surface deposited over the front side of the carrier substrate 910. The curvature of the convex bonding surface of the carrier-side dielectric bonding material layer 980 matches the curvature of the device-side dielectric bonding material layer 80 caused by pre-existing warpage of the device wafer 100. Mechanical stress within the silicon nitride material in the carrier-side dielectric bonding material layer 980, controlled during the deposition process, provides the curvature. Depending on the process parameters, the silicon nitride material induces tensile or compressive stress. The complementary convex-concave bonding interface ensures uniform contact and bonding strength during the bonding annealing process. The bonding annealing process forms strong covalent bonds, such as Si-O-Si or Si-N-Si, resulting in minimal voids despite the warping of the device wafer 100 causing non-planar interfaces.

[0076] Buffer layer 920 mitigates electrostatic damage during previous processing steps, such as plasma treatment or water rinsing. The amorphous or microcrystalline structure of buffer layer 920 promotes charge dissipation. Buffer layer 920 protects the semiconductor device 20 in device wafer 100. Buffer layer 920 exhibits a thermal conductivity ranging from 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or from 1 W / m·K to 4 W / m·K (for amorphous silicon). The thermal conductivity of buffer layer 920 exceeds that of carrier-side dielectric bonding material layer 980, which ranges from 0.7 W / m·K to 30 W / m·K. Buffer layer 920 ensures effective heat dissipation during bonding annealing to prevent thermal damage. The carrier wafer 900 is adjusted to match the pre-existing warpage of device wafer 100, maintaining precise overlay alignment. The bump-and-dip bonding interface enables robust dielectric-to-dielectric bonding. Despite the non-ideal warpage of the device wafer 100, the bonding wafer structure enhances reliability and yield.

[0077] refer to Figure 4A The fourth exemplary structure illustrates a water rinsing process according to an embodiment of the present disclosure. The fourth exemplary structure can be derived from the carrier wafer 900 by modifying the carrier wafer 900 during fabrication. Figure 1D This is derived from the first exemplary structure. Specifically, a buffer layer 920 can be formed using a deposition method that prevents material of the buffer layer 920 from depositing on the back surface of the carrier substrate 910. For example, the buffer layer 920 is formed using a single-wafer deposition process, wherein the back surface of the carrier substrate 910 is in direct contact with the chuck. Direct contact with the chuck prevents deposition on the back surface of the carrier substrate 910. Therefore, the back surface of the carrier substrate 910 is not covered by the buffer layer 920.

[0078] Device wafer 100 can be placed on a wafer washing device. (See reference...) Figure 1D The carrier wafer 900 is disposed on the device wafer 100 at a vertical spacing. A reference can be executed. Figure 1E The described processing steps can reduce the vertical spacing until the device-side dielectric bonding material layer 80 contacts the carrier-side dielectric bonding material layer 980, as shown. Figure 1FThe device wafer 100 includes a device-containing substrate (60, 50) having a semiconductor device 20 and metal interconnect structures (38, 48). A carrier wafer 900 includes a carrier substrate 910, typically monocrystalline silicon. A buffer layer 920, composed of an amorphous or microcrystalline material (such as polycrystalline or amorphous silicon), covers only the bevel and front side of the carrier substrate 910. The back side of the carrier substrate 910 is in direct contact with front-side deionized water 90 sprayed from an upper spray nozzle 730. A water rinsing process forms silanol groups on dielectric bonding material layers (80, 980). The water rinsing process prepares dielectric bonding material layers (80, 980) for dielectric-to-dielectric bonding. The buffer layer 920 on the bevel and front side helps dissipate charge to a grounded conductive contact ring 713. The buffer layer 920 protects the semiconductor device 20 from electrostatic damage.

[0079] refer to Figure 4B It can be achieved by executing, such as Figure 1G The bonding annealing process is used to provide an assembly of device wafer 100 and carrier wafer 900. Bonding annealing induces covalent bonding between dielectric bonding material layers (80, 980), such as Si-O-Si or Si-N-Si. Bonding annealing produces a strong bond with minimal voids. Buffer layer 920 covers only the bevel and front side of carrier substrate 910. Buffer layer 920 facilitates charge dissipation during the preceding water rinsing process. Buffer layer 920 exhibits a thermal conductivity of 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or 1 W / m·K to 4 W / m·K (for amorphous silicon). Buffer layer 920 aids in heat dissipation during bonding annealing. The thermal conductivity of buffer layer 920 exceeds that of carrier-side dielectric bonding material layer 980, which ranges from 0.7 W / m·K to 30 W / m·K. Stressed silicon nitride in the carrier-side dielectric bonding material layer 980 ensures precise overlay alignment. Although the coverage of the buffer layer 920 is limited, the bonding wafer structure enhances bonding reliability.

[0080] refer to Figure 5A The fifth exemplary structure illustrates a water rinsing process according to an embodiment of the present disclosure. The fifth structure can be derived from the carrier wafer 900 by modifying the carrier wafer 900 during fabrication. Figure 1DThis is derived from the first exemplary structure. Specifically, the buffer layer 920 is modified such that it covers only the bevel and back side of the carrier substrate 910, but not the front side. The buffer layer 920 can be deposited using a single wafer deposition process. In the single wafer deposition process, the front side of the carrier substrate 910 directly contacts the chuck. Direct contact with the chuck prevents deposition on the front side of the carrier substrate 910. Alternatively, the buffer layer 920 can be formed using front-side gas purging to avoid deposition on the front side of the carrier substrate 910. The carrier-side dielectric bonding material layer 980 is deposited directly on the front surface of the carrier substrate 910. The edge portions of the buffer layer 920 and the carrier-side dielectric bonding material layer 980 may contact at the bevel of the carrier substrate 910.

[0081] Device wafer 100 is placed on a wafer washing device. (See reference...) Figure 1D The carrier wafer 900 is positioned on top of the device wafer 100 at a vertical spacing. A reference can be executed. Figure 1E The described water rinsing process involves deionized water 90 from the front of the upper spray head 730 directly contacting the back of the buffer layer 920. (See reference...) Figure 1F The vertical spacing decreases until the device-side dielectric bonding material layer 80 contacts the carrier-side dielectric bonding material layer 980. Device wafer 100 includes a device-containing substrate (60, 50) having a semiconductor device 20 and metal interconnect structures (38, 48). Carrier wafer 900 includes a carrier substrate 910, typically monocrystalline silicon. A water rinsing process forms silanol groups on the dielectric bonding material layers (80, 980). The water rinsing process prepares the dielectric bonding material layers (80, 980) for dielectric-to-dielectric bonding. A buffer layer 920 on the bevel and back side helps dissipate charge to the grounded conductive contact ring 713. The buffer layer 920 protects the semiconductor device 20 from electrostatic damage.

[0082] refer to Figure 5B The fifth exemplary structure illustrates a bonding assembly of device wafer 100 and carrier wafer 900 after a bonding annealing process, such as... Figure 1GThe bonding annealing induces covalent bonding, such as Si-O-Si or Si-N-Si, between the dielectric bonding material layers (80, 980). Bonding annealing produces a strong bond with minimal voids. Buffer layer 920 covers only the bevel and back side of the carrier substrate 910. Buffer layer 920 promotes charge dissipation during the preceding water rinsing process. Buffer layer 920 exhibits a thermal conductivity of 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or 1 W / m·K to 4 W / m·K (for amorphous silicon). Buffer layer 920 aids in heat dissipation during bonding annealing. The thermal conductivity of buffer layer 920 exceeds that of the carrier-side dielectric bonding material layer 980, which ranges from 7 W / m·K to 30 W / m·K. Stressed silicon nitride in the carrier-side dielectric bonding material layer 980 ensures precise overlay alignment. Despite the limited coverage of the buffer layer 920, the bonding wafer structure enhances bonding reliability.

[0083] refer to Figure 6A The sixth exemplary structure illustrates a water rinsing process according to an embodiment of the present disclosure. The sixth exemplary structure can be derived from the carrier wafer 900 by modifying the carrier wafer 900 during fabrication. Figure 1D This is derived from the first exemplary structure. Specifically, a back-side capping layer 930 may be deposited on the back-side surface of the buffer layer 920. The back-side capping layer 930 includes a material having a higher conductivity than the buffer layer 920. The back-side capping layer 930 may include doped semiconductor and / or metallic materials. For example, the back-side capping layer 930 may have a structure that... to The conductivity range is specified. The back-side capping layer 930 promotes enhanced charge dissipation. When the carrier wafer 900 contacts the processing equipment, the back-side capping layer 930 prevents short circuits or arcing.

[0084] For reference Figure 1DThe device wafer 100 is disposed on a wafer rinsing apparatus. A carrier wafer 900 is disposed on the device wafer 100 at a vertical spacing. The device wafer 100 includes a device-containing substrate (60, 50) having a semiconductor device 20 and metal interconnect structures (38, 48). The carrier wafer 900 includes a carrier substrate 910, typically monocrystalline silicon. A buffer layer 920 composed of an amorphous or microcrystalline material (such as polycrystalline silicon or amorphous silicon) covers the bevel, front side, and back side of the carrier substrate 910. A carrier-side dielectric bonding material layer 980 is deposited on the front surface of the buffer layer 920. A back-side capping layer 930 contacts front-side deionized water 90 sprayed from an upper spray nozzle 730. A water rinsing process forms silanol groups on the dielectric bonding material layers (80, 980). The water rinsing process prepares dielectric bonding material layers (80, 980) for dielectric-to-dielectric bonding. The buffer layer 920 and back-side cover layer 930 on the bevel and back side help dissipate charge to the grounded conductive contact ring 713. The buffer layer 920 and back-side cover layer 930 protect the semiconductor device 20 from electrostatic damage. (See reference...) Figure 1F The vertical spacing is reduced until the device-side dielectric bonding material layer 80 contacts the carrier-side dielectric bonding material layer 980.

[0085] refer to Figure 6B It can be executed Figure 1G The bonding annealing process described herein provides a bonding assembly for device wafer 100 and carrier wafer 900. Bonding annealing induces covalent bonding between dielectric bonding material layers (80, 980), such as Si-O-Si or Si-N-Si. Bonding annealing produces a robust bond with minimal voids. Buffer layer 920 covers the bevel, front side, and back side of carrier substrate 910. Back side capping layer 930 covers the back side surface of buffer layer 920. Buffer layer 920 and back side capping layer 930 facilitate charge dissipation during the preceding water rinsing process. Buffer layer 920 exhibits a thermal conductivity of 30 W / m·K to 100 W / m·K (for polycrystalline silicon) or 1 W / m·K to 4 W / m·K (for amorphous silicon). Buffer layer 920 contributes to heat dissipation during bonding annealing. The thermal conductivity of the buffer layer 920 exceeds that of the carrier-side dielectric bonding material layer 980, which ranges from 7 W / m·K to 30 W / m·K. The back-side capping layer 930, exhibiting the high thermal conductivity typical of metals (e.g., 100 W / m·K to 400 W / m·K), further enhances heat dissipation. Stressed silicon nitride in the carrier-side dielectric bonding material layer 980 ensures precise capping alignment. The combined charge and thermal management provided by the buffer layer 920 and the back-side capping layer 930 enhances bonding reliability in the wafer bonding structure.

[0086] Common Reference Figures 1A to 6BVarious embodiments of this disclosure may provide bonding assemblies (100, 900). Bonding assemblies (100, 900) include: a device wafer 100 including a semiconductor device 20, metal interconnect structures (38, 48) embedded in a dielectric material layer, and a device-side dielectric bonding material layer 80 located on its front side; and a carrier wafer 900 including a carrier substrate 910, a buffer layer 920, and a carrier-side dielectric bonding material layer 980, the buffer layer 920 comprising an amorphous or microcrystalline material and disposed on at least a slope of the carrier substrate 910, the carrier-side dielectric bonding material layer 980 disposed above the front side of the carrier substrate 910 and bonded to the device-side dielectric bonding material layer 80 by dielectric-to-dielectric bonding.

[0087] In one embodiment, buffer layer 920 covers the front side of carrier substrate 910. In one embodiment, buffer layer 920 covers the back side of carrier substrate 910. In one embodiment, the amorphous or microcrystalline material includes polycrystalline silicon or amorphous silicon. In one embodiment, buffer layer 920 includes a material having a higher thermal conductivity than the material of carrier-side dielectric bonding material layer 980.

[0088] In one embodiment, the carrier-side dielectric bonding material layer 980 comprises silicon nitride, which causes warping of the carrier substrate 910 by tensile or compressive stress. In one embodiment, the bonding assembly (100, 900) further includes a back-side capping layer 930 disposed on the back-side surface of the buffer layer 920, the back-side capping layer comprising a material having a higher conductivity than amorphous or microcrystalline materials.

[0089] refer to Figure 7 The first flowchart illustrates the steps for forming a bonding assembly according to an embodiment of the present disclosure.

[0090] Refer to step 710 and Figure 1A , Figure 2A , Figure 3 , Figure 4A , Figure 5A and Figure 6A A device wafer 100 is provided, which includes a semiconductor device 20 and metal interconnect structures (38, 48) embedded in a dielectric material layer, and has a device-side dielectric bonding material layer 80 on its front side.

[0091] Refer to step 720 and Figure 1B , Figure 2A , Figure 3 , Figure 4A , Figure 5A and Figure 6AA buffer layer 920 is deposited on at least a sloped surface of a carrier substrate 910, which includes a carrier substrate material. The buffer layer 920 comprises an amorphous or microcrystalline material configured to enhance charge release relative to a single-crystal material having the same material composition.

[0092] Refer to step 730 and Figure 1C , Figure 2A , Figure 3 , Figure 4A , Figure 5A and Figure 6A A carrier-side dielectric bonding material layer 980 is deposited on the front side of the carrier substrate 910 above the buffer layer 920.

[0093] Refer to step 740 and Figures 1D to 6B The carrier-side dielectric bonding material layer 980 is bonded to the device-side dielectric bonding material layer 80 by dielectric-to-dielectric bonding.

[0094] refer to Figure 8 The second flowchart illustrates the steps for forming a bonding assembly according to an embodiment of the present disclosure.

[0095] Refer to steps 810 and Figure 1A , Figure 2A , Figure 3 , Figure 4A , Figure 5A and Figure 6A A device wafer 100 is provided, which includes a semiconductor device 20 and metal interconnect structures (38, 48) embedded in a dielectric material layer, and has a device-side dielectric bonding material layer 80 on its front side.

[0096] Refer to step 820 and Figure 1B , Figure 2A , Figure 3 , Figure 4A , Figure 5A and Figure 6A A buffer layer 920 is deposited on at least a sloped surface of a carrier substrate 910, which includes a carrier substrate material. The buffer layer comprises an amorphous or microcrystalline material.

[0097] Refer to step 830 and Figure 1C , Figure 2A , Figure 3 , Figure 4A , Figure 5A and Figure 6A A carrier-side dielectric bonding material layer 980 is deposited on the front side of the carrier substrate 910 above the buffer layer 920.

[0098] Refer to step 840 and Figure 1D , Figure 1E , Figure 1F , Figure 2B , Figure 2C , Figure 3 , Figure 4A , Figure 5A and Figure 6A A wafer rinsing process is performed on the carrier wafer 900. The buffer layer 920 contacts the conductive surface of the processing equipment to release charge from the buffer layer 920.

[0099] Refer to step 850 and Figure 1G , Figure 2D , Figure 3 , Figure 4B , Figure 5B and Figure 6B The carrier-side dielectric bonding material layer 980 is bonded to the device-side dielectric bonding material layer 80 by dielectric-to-dielectric bonding.

[0100] According to various aspects of this disclosure, the method of forming the bonding components (100, 900) uses a buffer layer 920 within a carrier wafer 900. The buffer layer 920 comprises an amorphous or microcrystalline material, such as polycrystalline silicon or amorphous silicon, and is deposited at least on a sloped surface of the carrier substrate 910, as referenced. Figure 1B , Figure 2A , Figure 4A , Figure 5A and Figure 6A The carrier-side dielectric bonding material layer 980 induces controllable tensile or compressive stress to compensate for warpage within the device wafer 100, for example, as described above. Figure 3 As shown in the reference. Figure 1D , Figure 1E , Figure 2A , Figure 2B , Figure 4A , Figure 5A and Figure 6A The buffer layer 920 enhances charge dissipation during processes such as surface activation, plasma treatment, and water rinsing. The buffer layer 920 mitigates charge accumulation that could damage the semiconductor device 20. The buffer layer 920 provides a higher thermal conductivity than the dielectric bonding material layers (80, 980) within the bonding assemblies (100, 900). The buffer layer 920 enhances heat dissipation during bonding processes. The buffer layer 920 prevents overheating in the semiconductor device 20. Figure 6A As shown, a back-side capping layer 930 with high electrical conductivity is optionally deposited on the buffer layer 920 to enhance charge release during processing steps. The bonded wafer structure achieves stronger bonding strength, better coverage performance, reduced charge accumulation, and improved thermal management.

[0101] Embodiments of this disclosure provide a bonding assembly including a device wafer and a carrier wafer, and a method of forming the same. The carrier wafer includes a buffer layer deposited on a carrier substrate. The buffer layer includes an amorphous or microcrystalline material, such as polycrystalline silicon or amorphous silicon. The buffer layer mitigates charge accumulation at the wafer device interface during the bonding process. The buffer layer reduces the risk of electrostatic damage to the semiconductor devices in the device wafer. A carrier-side dielectric bonding material layer (optionally including stressed silicon nitride) causes controlled warpage to match the shape of the device wafer. The carrier-side dielectric bonding material layer enhances bonding strength and coverage performance. The buffer layer provides higher thermal conductivity than the carrier-side dielectric bonding material layer. The buffer layer promotes heat dissipation near the bonding interface during high-temperature processes, such as bonding annealing. A back-side capping layer optionally enhances charge dissipation. The bonding assembly achieves improved bonding strength, accurate capping alignment, reduced charge accumulation, and enhanced thermal management. Various aspects of this disclosure will now be described with reference to the accompanying drawings.

[0102] In exemplary applications of advanced semiconductor manufacturing according to embodiments of this disclosure, a power distribution network can be provided via a back-side metal interconnect structure 48 embedded within a back-side dielectric material layer 40, enabling efficient transfer of power signals from the back side of a thin semiconductor substrate 10 to a semiconductor device 20. The thin semiconductor substrate 10 may include a layer comprising nanosheets configured to form channel regions for advanced transistor architectures. Nanosheet field-effect transistors can be incorporated within the semiconductor device 20, utilizing a full-ring gate structure to enhance electrostatic control, drive current, and scaling capabilities, surpassing conventional fin-based designs. Furthermore, cutting-edge technologies such as 1.6nm and 1.4nm process nodes, complementary field-effect transistors, and advanced back-side power delivery solutions can be seamlessly integrated into the device wafer 100, enabling superior performance, higher transistor density, and lower power consumption in next-generation logic and high-performance computing applications.

[0103] One aspect of this application provides a method for forming a bonding assembly, comprising: providing a device wafer including a semiconductor device and a metal interconnect structure embedded in a dielectric material layer, and having a device-side dielectric bonding material layer on the front side of the device wafer; depositing a buffer layer at least on a slope of a carrier substrate including a carrier substrate material; depositing a carrier-side dielectric bonding material layer on the front side of the carrier substrate above the buffer layer; and bonding the carrier-side dielectric bonding material layer to the device-side dielectric bonding material layer by dielectric-to-dielectric bonding.

[0104] In some embodiments, the buffer layer comprises an amorphous or microcrystalline material configured to enhance charge release.

[0105] In some embodiments, the buffer layer covers at least one of the front side and the back side of the carrier substrate.

[0106] In some embodiments, the carrier substrate material is a semiconductor material; and the amorphous or microcrystalline material of the buffer layer is a semiconductor material.

[0107] In some embodiments, the amorphous or microcrystalline material includes polycrystalline silicon or amorphous silicon.

[0108] In some embodiments, the thermal conductivity of the buffer layer is higher than that of the carrier-side dielectric bonding material layer.

[0109] In some embodiments, the carrier-side dielectric bonding material layer comprises silicon nitride deposited in the carrier substrate under conditions that induce tensile or compressive stress.

[0110] In some embodiments, tensile or compressive stresses cause positive or negative warping in the carrier substrate.

[0111] In some embodiments, the method further includes depositing a back-side capping layer on the back-side surface of the buffer layer, the back-side capping layer comprising a material having a higher electrical conductivity than the amorphous or microcrystalline material.

[0112] In some embodiments, the method further includes performing a plasma treatment process to form silanol radicals on the surface of the buffer layer, wherein the amorphous or microcrystalline material provides an enhanced charge release rate to the buffer layer during the plasma treatment process, relative to a single-crystal material having the same material composition as the amorphous or microcrystalline material.

[0113] In some embodiments, the method further includes performing a water rinsing process prior to the bonding process of bonding the carrier-side dielectric bonding material layer to the device-side dielectric bonding material layer, wherein the surface morphology of the amorphous or microcrystalline material enhances charge release during the water rinsing process relative to the surface morphology of a flat single-crystal surface.

[0114] Another aspect of this application provides a method for forming a bonding assembly, comprising: providing a device wafer including a semiconductor device and a metal interconnect structure embedded in a dielectric material layer, and having a device-side dielectric bonding material layer on a front side of the device wafer; depositing a buffer layer comprising an amorphous or microcrystalline material on at least a slope of a carrier substrate including a carrier substrate material; providing a carrier wafer by depositing a carrier-side dielectric bonding material layer on the front side of the carrier substrate above the buffer layer; performing a wafer rinsing process on the carrier wafer, wherein the buffer layer contacts a conductive surface of a processing device to release charge from the buffer layer; and bonding the carrier-side dielectric bonding material layer to the device-side dielectric bonding material layer by dielectric-to-dielectric bonding.

[0115] In some embodiments, the method further includes performing a surface activation process on the buffer layer, wherein the surface morphology of the amorphous or microcrystalline material, relative to the surface morphology of a flat single-crystal surface, enhances charge release from the buffer layer during the surface activation process.

[0116] In some embodiments, the method further includes performing a water rinsing process on the buffer layer before bonding the carrier-side dielectric bonding material layer to the device-side dielectric bonding material layer, wherein the surface morphology of the amorphous or microcrystalline material, relative to the surface morphology of a flat single-crystal surface, enhances charge release from the buffer layer during the water rinsing process.

[0117] In some embodiments, the method further includes depositing a back-side capping layer on the back surface of the buffer layer such that the carrier-side dielectric bonding material layer contacts the front surface of the buffer layer.

[0118] In another aspect, this application provides a bonding assembly, comprising: a device wafer including a semiconductor device, a metal interconnect structure embedded in a dielectric material layer, and a device-side dielectric bonding material layer located on the front side of the device wafer; and a carrier wafer including a carrier substrate, a buffer layer, and a carrier-side dielectric bonding material layer, wherein the buffer layer comprises an amorphous or microcrystalline material and is disposed at least on the inclined surface of the carrier substrate, and the carrier-side dielectric bonding material layer is disposed above the front side of the carrier substrate and bonded to the device-side dielectric bonding material layer by dielectric-to-dielectric bonding.

[0119] In some embodiments, the buffer layer covers the front side and the back side of the carrier substrate; and the amorphous or microcrystalline material includes polycrystalline silicon or amorphous silicon.

[0120] In some embodiments, the buffer layer comprises a material having a higher thermal conductivity than the material of the carrier-side dielectric bonding material layer.

[0121] In some embodiments, the carrier-side dielectric bonding material layer includes silicon nitride, which causes warping of the carrier substrate by tensile or compressive stress.

[0122] In some embodiments, the bonding assembly further includes a back-side cover layer disposed on the back-side surface of the buffer layer and comprising a material having a higher electrical conductivity than the amorphous or microcrystalline material.

[0123] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Unless otherwise expressly disclosed herein, each embodiment described using the term “comprising” also inherently discloses additional embodiments, wherein “comprising” is replaced by “substantially consists of” or “consisting of”. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “may” is used in this disclosure to describe the execution of a step in the formation or processing of an element, embodiments in which such an element or such step is not performed are expressly contemplated, provided that the resulting apparatus or device can provide equivalent results. Therefore, the auxiliary verb “may” applied to the execution of a step in the formation or processing of an element should also be interpreted as “may” or “may or may not”, provided that omitting such a step in the formation or processing of an element can provide the same or equivalent results, including slightly better and slightly worse results. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method of forming a mating assembly, comprising: A device wafer is provided, the device wafer including a semiconductor device and a metal interconnect structure embedded in a dielectric material layer, and having a device-side dielectric bonding material layer on the front side of the device wafer; A buffer layer is deposited at least on the slope of the carrier substrate, which includes the carrier substrate material; A carrier-side dielectric bonding material layer is deposited on the front side of the carrier substrate above the buffer layer; as well as The carrier-side dielectric bonding material layer is bonded to the device-side dielectric bonding material layer via dielectric-to-dielectric bonding.

2. The method according to claim 1, wherein, The buffer layer comprises an amorphous or microcrystalline material configured to enhance charge release.

3. The method according to claim 1, wherein, The buffer layer covers at least one of the front side and the back side of the carrier substrate.

4. The method according to claim 1, wherein: The carrier substrate material is a semiconductor material; and The amorphous or microcrystalline material of the buffer layer is a semiconductor material.

5. The method according to claim 4, wherein, The amorphous or microcrystalline material includes polycrystalline silicon or amorphous silicon.

6. The method according to claim 1, wherein, The thermal conductivity of the buffer layer is higher than that of the dielectric bonding material layer on the carrier side.

7. The method according to claim 1, wherein, The carrier-side dielectric bonding material layer comprises silicon nitride deposited in the carrier substrate under conditions that induce tensile or compressive stress.

8. The method according to claim 7, wherein, The tensile or compressive stress causes positive or negative warping in the carrier substrate.

9. A method of forming a mating assembly, comprising: A device wafer is provided, the device wafer including a semiconductor device and a metal interconnect structure embedded in a dielectric material layer, and having a device-side dielectric bonding material layer on the front side of the device wafer; At least a buffer layer comprising amorphous or microcrystalline material is deposited on the inclined surface of the carrier substrate, which includes the carrier substrate material; A carrier wafer is provided by depositing a carrier-side dielectric bonding material layer on the front side of the carrier substrate above the buffer layer; A wafer rinsing process is performed on the carrier wafer, wherein the buffer layer contacts the conductive surface of the processing equipment to release charge from the buffer layer; as well as The carrier-side dielectric bonding material layer is bonded to the device-side dielectric bonding material layer via dielectric-to-dielectric bonding.

10. A joining assembly, comprising: A device wafer, the device wafer including a semiconductor device, a metal interconnect structure embedded in a dielectric material layer, and a device-side dielectric bonding material layer located on the front side of the device wafer; and A carrier wafer, the carrier wafer including a carrier substrate, a buffer layer and a carrier-side dielectric bonding material layer, the buffer layer including an amorphous or microcrystalline material and disposed at least on the inclined surface of the carrier substrate, the carrier-side dielectric bonding material layer being disposed above the front side of the carrier substrate and bonded to the device-side dielectric bonding material layer by dielectric-to-dielectric bonding.

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