Wafer preparation method and reconstituted wafer

Abstract

The application relates to the technical field of semiconductors, and discloses a wafer preparation method and a reconstructed wafer. The wafer preparation method comprises the following steps: hetero-bonding a die unit and a placeholder unit to a carrier wafer, the die unit comprising, in sequence from the carrier wafer, an epitaxial layer, an etching stop layer and a substrate; mechanically thinning the substrate; removing the remaining substrate by using a wet etching process and stopping at the etching stop layer; removing the etching stop layer to expose the epitaxial layer; depositing a passivation layer on the surface of the carrier wafer and the surface and sidewall of the epitaxial layer away from the carrier wafer; and performing a planarization treatment on the placeholder unit. Compared with the related art, the application can solve the problems of poor uniformity of wet etching, no protection of the epitaxial layer sidewall and warping in the related art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a wafer fabrication method and a reconstructed wafer. Background Technology

[0002] In the field of silicon photonics integration technology, indium phosphide (InP)-based materials, due to their direct bandgap characteristics, exhibit excellent photoelectric conversion efficiency in the 1310nm and 1550nm communication bands, making them a core material for fabricating active optoelectronic devices such as on-chip lasers, modulators, and detectors. However, silicon is an indirect bandgap semiconductor and cannot emit light efficiently. Therefore, silicon photonics integrated circuits require the introduction of III-V group materials such as InP as on-chip light sources, which has become a key bottleneck in achieving large-scale silicon photonics integration.

[0003] Currently, there are three main technical routes for integrating InP materials into silicon platforms: monolithic heteroepitaxial growth, wafer-level W2W (wafer-to-wafer) direct bonding, and die-to-wafer D2W (die-to-wafer) bonding. Heteroepitaxial growth is limited by the large lattice and thermal mismatch between InP and silicon (Si), resulting in high dislocation density in the epitaxial layer, which is difficult to meet the requirements of high-performance lasers. W2W bonding is limited by the size of InP wafers (typically 2 / 3 / 4 inches), making it incompatible with 8 / 12-inch advanced CMOS (Complementary Metal-Oxide-Semiconductor) process platforms, hindering large-scale mass production. In contrast, D2W heterogeneous bonding technology can transfer the die units after dicing small-size InP wafers to large-size carrier wafers (such as silicon wafers), maintaining the high crystal quality of epitaxial layers on small-size platforms, being compatible with advanced node microfabrication equipment, and enabling the screening of known good chips and flexible design. It is considered the most promising heterogeneous integration solution.

[0004] However, existing D2W heterobonding schemes suffer from poor uniformity in wet etching, lack of protection for epitaxial layer sidewalls, and warping issues, which limit device yield and mass production feasibility. Summary of the Invention

[0005] This invention provides a wafer fabrication method and a reconstructed wafer to solve the problems of poor uniformity of wet etching, lack of protection of epitaxial layer sidewalls, and warping in related technologies.

[0006] In a first aspect, the present invention provides a wafer fabrication method, comprising: The die unit and the occupant unit are heterobonded to the carrier wafer. The die unit includes an epitaxial layer, an etching barrier layer and a substrate arranged sequentially in a direction away from the carrier wafer. The substrate is mechanically thinned; The remaining substrate is removed using a wet etching process, stopping at the etching barrier layer; Remove the corrosion barrier layer to expose the epitaxial layer; A passivation layer is deposited on the surface of the carrier wafer and on the surface and sidewalls of the epitaxial layer opposite to the carrier wafer. The spacer unit is flattened.

[0007] Secondly, the present invention provides a reconstructed wafer, which is made based on the wafer fabrication method described above in this application.

[0008] This application employs a two-step method to remove the substrate using mechanical thinning and wet etching. Mechanical thinning quickly removes the main thickness portion of the substrate, followed by wet etching to remove the remaining thin substrate layer. Compared to related technologies that use pure wet etching on relatively thick substrates, this application significantly reduces the amount of etching, shortens etching time, and makes uniformity easier to control. This reduces the probability of micromask effects and lateral drilling, ensuring the flatness of the epitaxial layer's lower surface and the reliability of the bonding interface. Furthermore, after the substrate and etch barrier layer are completely removed, a passivation layer is deposited on the surface of the supporting wafer and on the surface and sidewalls of the epitaxial layer opposite to the supporting wafer, ensuring the passivation layer completely encapsulates the epitaxial layer. Compared to the process sequence of "depositing the passivation layer first and then removing the substrate" in related technologies, this application avoids wafer warpage caused by stress introduced by passivation layer deposition, eliminating the interference of warpage on the uniformity of subsequent thinning and CMP processes. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0010] Figure 1 This is a flowchart of a wafer fabrication method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the wafer structure after step S1 is completed according to the wafer fabrication method of the present invention. Figure 3 This is a schematic diagram of the structure of a grain unit according to an embodiment of the present invention; Figure 4 This is a layout diagram of the die units and place units on the carrier wafer according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the wafer structure after step S2 is completed according to the wafer fabrication method of an embodiment of the present invention. Figure 6 This is a schematic diagram of the wafer structure after step S3 is completed according to the wafer fabrication method of an embodiment of the present invention. Figure 7 This is a schematic diagram of the wafer structure after step S4 is completed according to the wafer fabrication method of the present invention. Figure 8 This is a schematic diagram of the wafer structure after step S5 is completed according to the wafer fabrication method of an embodiment of the present invention. Figure 9 This is a schematic diagram of the wafer structure after step S6 is completed in the wafer fabrication method according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the wafer structure after step S7 is completed in the wafer fabrication method according to an embodiment of the present invention.

[0011] Figure label: 100, Grain unit; 110, Epitaxial layer; 120, Etching barrier layer; 130, Substrate; 130', Remaining portion of the substrate; 200, Placement unit; 210, Second silicon wafer; 210', Remaining portion of the silicon wafer in the placement unit; 210'', Secondary thinning portion of the silicon wafer in the placement unit; 220, Second silicon dioxide film; 300, Carrier wafer; 310, First silicon wafer; 320, First silicon dioxide film; 400, Bonding interposer; 500, Passivation layer; 600, Device structure. Detailed Implementation

[0012] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0013] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0014] In a D2W heterobonding scheme employed in related technologies, substrate removal typically follows this process: after D2W heterobonding, the substrate, which is hundreds of micrometers thick, is selectively wet-etched using an HCl-based solution, utilizing an InGaAs layer as an etching barrier to remove the substrate in one step. However, this scheme has the following problems: Firstly, when using a pure wet etching method to etch substrates on the order of hundreds of micrometers over a large area, it is difficult to control the uniformity of the etching rate. The residues left during the etching process produce a micromask effect on the InGaAs barrier layer, which deteriorates the surface roughness of the active region of the epitaxial layer. At the same time, it causes a large amount of lateral drilling at the bonding interface, affecting the bonding reliability and the optoelectronic performance of the device.

[0015] Secondly, after the substrate is removed, the sidewalls of the epitaxial layer are directly exposed. During subsequent CMP planarization of the carrier wafer, the polishing slurry comes into direct contact with InP, causing chemical corrosion and mechanical scratches, which damages the structural integrity of the epitaxial layer.

[0016] Third, the related technologies employ a process sequence of first depositing a passivation layer and then removing the substrate. The stress introduced by the passivation layer deposition can cause wafer warping, interfering with the uniformity of subsequent thinning and CMP processes, and further reducing device yield.

[0017] To resolve at least one of the aforementioned technical issues, please refer to the following: Figures 1 to 3 This application provides a wafer fabrication method for integrating InP-based materials onto a large-size silicon-based platform to fabricate active optoelectronic devices such as on-chip lasers. The wafer fabrication method includes: Step S1: The die unit 100 and the occupancy unit 200 are heterobonded to the carrier wafer 300; Specifically, die unit 100 refers to a single chip unit (die) obtained by cutting from an epitaxial structure (including a circular substrate, an etch-barrier layer, and an epitaxial layer). Its size is typically in the millimeter range, such as 5mm × 5mm, 10mm × 10mm, etc., and the specific size can be determined according to actual design requirements. Die unit 100 is, for example, an indium phosphide (InP) die unit, which is a single die unit obtained by cutting from an InP epitaxial structure. This InP epitaxial structure includes a circular InP substrate and an etch-barrier layer and an InP epitaxial layer formed thereon. It is readily understood that although this application uses InP material as an example, those skilled in the art, inspired by the core concept of this application, can apply the method of this application to other material systems, such as GaAs, GaN, or LiNbO3, etc., and this application does not limit this application.

[0018] like Figure 2 and Figure 3 As shown, the die unit 100 includes an epitaxial layer 110, an etching barrier layer 120, and a substrate 130 sequentially disposed along a direction away from the supporting wafer 300. The epitaxial layer 110 is an active light-emitting layer structure containing quantum wells or quantum dot structures for subsequent fabrication of the light-emitting region of an on-chip laser. For the InP material epitaxial layer 110, the etching barrier layer 120 is made of materials such as InGaAs, used to prevent the etchant from eroding the epitaxial layer 110 during subsequent wet etching. The substrate 130 serves as a growth substrate, supporting the growth of the epitaxial layer 110 and the etching barrier layer 120.

[0019] The dummy die (also known as a virtual die or dummy chip) serves as a filler unit, used to fill vacancies in non-InP regions on the carrier wafer 300. These non-InP regions are the areas on the carrier wafer 300 other than the die unit 100. By using the dummy die 200 to fill these vacancies, the uniformity of subsequent planarization processes can be ensured.

[0020] In some embodiments, the occupant unit 200 may include, for example, a silicon wafer, which may be made of monocrystalline silicon or polycrystalline silicon, preferably the same material as the carrier wafer 300, so as to have consistent mechanical properties and processing characteristics in subsequent thinning and planarization processes.

[0021] In some embodiments, the size of the placeholder unit 200 is the same as the size of the die unit 100, so that the force per unit area of ​​each region on the surface of the supporting wafer 300 is consistent. During the subsequent planarization process, the pressure distribution between the grinding tool and the wafer surface is uniform, thereby ensuring the consistency of the flatness of the entire wafer surface. Of course, in practical applications, the size of the placeholder unit 200 can also be different from the size of the die unit 100. For example, a smaller placeholder unit 200 can be used in the edge region of the supporting wafer 300 to adapt to the irregular edge space, or a combination of placeholder units 200 of various sizes can be used to fill the space under specific layout requirements. As long as there is sufficient placeholder support in the area where all die units 100 are located and within a certain range around them, this application does not limit this.

[0022] In some embodiments, the carrier wafer 300 can be an SOI silicon photonics wafer or a TFLN-on-insulator wafer. The carrier wafer 300 is used to carry the die unit 100 and the placeholder unit 200, and serves as a substrate for reconstructing the wafer in subsequent processes. The size of the carrier wafer 300 is, for example, 8 inches (200 mm) or 12 inches (300 mm). Further, in some embodiments, the method for fabricating the carrier wafer 300 includes: First, such as Figure 2 As shown, a silicon dioxide film (hereinafter referred to as the first silicon wafer 310) is deposited on the silicon wafer 300 (hereinafter referred to as the first silicon wafer 310). Optionally, after depositing the first silicon dioxide film 320 on the first silicon wafer 310, the first silicon wafer 310 with the first silicon dioxide film 320 deposited thereon may be planarized.

[0023] In some embodiments, the die unit 100 and the placeholder unit 200 can be heterogeneously bonded to the carrier wafer 300 via a D2W (Die-to-Wafer) method, that is, each die unit 100 and each placeholder unit 200 is respectively bonded to a predetermined position on the carrier wafer 300. The specific distribution of the die unit 100 and the placeholder unit 200 on the carrier wafer 300 is, for example, as shown below. Figure 4 As shown.

[0024] In some embodiments, such as Figure 2 As shown, the grain unit 100 and the placeholder unit 200 are heterogeneously bonded to the carrier wafer 300 through a bonding intermediary layer 400. The material of the bonding intermediary layer 400 includes, for example, Al2O3 or SiO2. The bonding intermediary layer 400 can be located between the carrier wafer 300 and the grain unit 100, and between the carrier wafer 300 and the placeholder unit 200, to achieve high-quality bonding between heterogeneous materials.

[0025] In some other embodiments, the bonding intermediary layer 400 may be omitted, in which case the grain unit 100 is directly heterobonded to the carrier wafer 300.

[0026] In some embodiments, the method for preparing the grain unit 100 includes: First, a circular substrate is provided, and an etching barrier layer and an epitaxial layer are sequentially grown on the circular substrate to form an epitaxial structure. The materials of the circular substrate and the epitaxial layer are, for example, InP.

[0027] Then, the epitaxial structure is cut to obtain grain unit 100.

[0028] It should be noted that, in order to facilitate the distinction between the different forms before and after dicing, the complete wafer and its continuous film layer before dicing are referred to as "whole wafer" and "whole layer". That is, "whole wafer substrate" refers to the complete substrate that has not yet been diced, "etch barrier layer" and "epitaxy layer" refer to the complete etch barrier film and InP epitaxial film continuously covered on the complete substrate, respectively; the corresponding parts in the single grain unit obtained after dicing are referred to as "substrate 130", "etch barrier layer 120" and "epitaxy layer 110", respectively.

[0029] Furthermore, in an embodiment where the grain unit 100 and the occupant unit 200 are heterobonded to the carrier wafer 300 through the bonding interposer layer 400, a first sublayer of the bonding interposer layer can be formed on the entire surface of the epitaxial layer before the epitaxial structure is cut (described in detail below).

[0030] In some embodiments, the method for preparing the occupant unit 200 includes: First, a silicon dioxide film is deposited on a silicon wafer; Then, the silicon wafer with the deposited silicon dioxide film is cut to obtain the placeholder unit 200.

[0031] For example, such as Figure 2As shown, the occupancy unit 200 includes a silicon wafer (hereinafter referred to as the second silicon wafer 210) and a silicon dioxide film layer (hereinafter referred to as the second silicon dioxide film layer 220). Based on this, a first silicon dioxide film layer 320 is deposited on the first silicon wafer 310 in the carrier wafer 300, and the second silicon dioxide film layer 220 of the occupancy unit 200 is bonded to the first silicon dioxide film layer 320 of the carrier wafer 300 through a bonding intermediary layer 400. The second silicon dioxide film 220 and the first silicon dioxide film 320 serve as bonding buffer layers for the placeholder unit 200 and the carrier wafer 300, respectively. By setting this bonding buffer layer, on the one hand, the silicon dioxide film has good surface flatness and low surface roughness, which can provide a flat bonding interface for subsequent bonding and improve the bonding quality; on the other hand, the silicon dioxide film serves as an insulating layer, which can electrically isolate the die unit 100 and the placeholder unit 200 from the carrier wafer 300 and avoid leakage; furthermore, the silicon dioxide film can serve as a polishing stop layer in the subsequent thinning and CMP planarization process to help control the thinning thickness.

[0032] Furthermore, when the carrier wafer 300 is an SOI silicon photonics wafer, the SOI wafer itself contains a buried oxide layer (BOX layer). In this case, the first silicon dioxide film layer 320 on the surface of the carrier wafer 300 can form a multilayer insulating structure together with the buried oxide layer of the SOI wafer, further optimizing the electrical isolation effect. The bonding interlayer 400 can be made of Al2O3 or SiO2, which plays a role in connecting the second silicon dioxide film layer 220 and the first silicon dioxide film layer 320 during the bonding process, achieving high-quality bonding between heterogeneous materials.

[0033] Furthermore, after depositing the second silicon dioxide film 220 on the second silicon wafer 210, the second silicon wafer 210 with the deposited second silicon dioxide film 220 can be planarized.

[0034] In addition, in embodiments where the die unit 100 and the placeholder unit 200 are heterobonded to the carrier wafer 300 via a bonding interposer layer 400, the bonding interposer layer 400 may be formed only on the bonding surfaces of one or more of the die unit 100, the placeholder unit 200, and the carrier wafer 300. As an example, a first sub-layer of the bonding interposer layer may be formed on the surface of the epitaxial layer 110, a second sub-layer of the bonding interposer layer may be formed on the surface of the second silicon dioxide film layer 220 of the placeholder unit 200, and a third sub-layer of the bonding interposer layer may be formed on the surface of the carrier wafer 300. When the die unit 100, the placeholder unit 200, and the carrier wafer 300 are bonded, the first sub-layer, the second sub-layer, and the third sub-layer together constitute the aforementioned bonding interposer layer 400. As another example, the bonding interposer 400 may be formed only on the surface of the carrier wafer 300, while the bonding surfaces of the die unit 100 and the placeholder unit 200 may not have an interposer, and they may be directly bonded to the bonding interposer 400 on the carrier wafer 300. As yet another example, the bonding interposer 400 may be formed only on the bonding surface of the die unit 100, while the bonding surfaces of the carrier wafer 300 and the placeholder unit 200 may not have an interposer. That is, the bonding interposer 400 may exist only on one side of the bonding interface, or it may exist on both sides of the bonding interface. As long as the bonding interposer 400 is provided on at least one side of the bonding interface, heterogeneous bonding can be achieved, and this application does not limit this. In addition, in some embodiments, the bonding interposer 400 may be omitted, and the die unit 100 and the placeholder unit 200 may be directly heterogeneously bonded to the carrier wafer 300.

[0035] It should be noted that the steps of forming and cutting the bonding interposer layer 400 are all conventional processes in the field, and this application does not limit the specific process parameters.

[0036] Step S2 involves mechanically thinning the substrate 130 and the occupancy unit 200 (i.e., the second silicon wafer 210).

[0037] Specifically, the substrate 130 is mechanically thinned to remove the main thickness portion of the substrate 130. Figure 5 The diagram shows the remaining portion 130' of the substrate 130 and the remaining portion 210' of the second silicon wafer 210 after mechanical thinning. In some embodiments, mechanical thinning includes, for example, mechanical polishing, CMP polishing, or a combination of both.

[0038] By mechanically thinning the substrate 130 from its original thickness (e.g., approximately 350 μm) to a predetermined remaining thickness, a thinner residual layer of substrate 130 can be provided for subsequent wet etching. This reduces the amount and time required for wet etching, avoiding problems such as poor uniformity and lateral drilling associated with large-area wet etching. Furthermore, mechanical thinning is highly efficient and provides good uniformity, enabling the rapid removal of most of the substrate 130.

[0039] In some embodiments, after thinning the substrate 130, the thickness of the remaining substrate (i.e., the remaining portion 130') is less than or equal to 50 μm. For example, the thickness of the remaining substrate can be 50 μm, 45 μm, 40 μm, 35 μm, 30 μm, 25 μm, 20 μm, 15 μm, or 10 μm. Preferably, it is 30 μm.

[0040] By controlling the thickness of the remaining substrate (i.e., the remaining portion 130') to below 50 μm, the amount of subsequent wet etching can be significantly reduced, shortening the etching time and making uniformity easier to control, thereby reducing the probability of micromask effects and lateral drilling. On the other hand, if the remaining portion 130' is too thick, the wet etching time will be prolonged, increasing the risk of lateral penetration of the etchant into the bonding interface. Simultaneously, the etching selectivity ratio between the substrate 130 and the etching barrier layer 120 may fluctuate during long-term etching, increasing the risk of over-etching. If the remaining portion 130' is too thin, uneven thickness during mechanical thinning can easily lead to premature penetration in localized areas, damaging the underlying etching barrier layer 120 and epitaxial layer 110. Therefore, controlling the remaining portion 130' between 10 μm and 50 μm ensures the safety of mechanical thinning while providing an optimal process window for subsequent wet etching.

[0041] It is easy to understand that after mechanical thinning, the surface of the remaining portion 210' of the second silicon wafer 210 is approximately flush with the surface of the remaining portion 130' of the substrate 130. Since the initial thickness of the occupant unit 200 and the grain unit 100 may differ, the specific parameters of the thinning process (including polishing time, polishing pressure, etc.) can be adjusted according to actual needs, as long as the remaining thickness of the two is approximately the same after thinning. This application does not impose any limitations on this.

[0042] Step S3: The remaining substrate (i.e., the remaining portion 130') is removed using a wet etching process, and the process stops at the etching barrier layer 120.

[0043] Specifically, Figure 6 The wafer structure after the remaining substrate (i.e., the remaining portion 130') has been removed is shown.

[0044] In some embodiments, the wet etching process uses an etchant, for example, an HCl-based solution, which has a high selectivity for both InP and the material of the etching barrier layer 120 (e.g., InGaAs). Due to the small amount of etching (the thickness of the remaining portion 130' is the amount of etching, for example, about 35 μm), the etching time is short, and the etching uniformity is easily controlled, reducing the occurrence of micromask effects and lateral drilling. During etching, the HCl-based solution preferentially etches the remaining substrate (i.e., the remaining portion 130'). When etching reaches the etching barrier layer 120, the etching automatically stops at the etching barrier layer 120 because the etching rate of HCl on the material of the etching barrier layer 120 (e.g., InGaAs) is relatively low, thereby protecting the underlying epitaxial layer 110 from damage.

[0045] Step S4: Remove the etch barrier layer 120 to expose the epitaxial layer 110.

[0046] Specifically, Figure 7 The wafer structure after removing the etch barrier layer 120 is shown. After etching stops in step S3, another etchant can be used to remove the etch barrier layer 120, exposing the epitaxial layer 110 away from the surface of the supporting wafer. At this time, the sidewalls of the epitaxial layer 110 are exposed. The removal of the etch barrier layer 120 can be performed using an etchant selective for the etch barrier layer 120 (e.g., InGaAs), ensuring that the epitaxial layer 110 is not damaged during the removal of the etch barrier layer 120. Of course, in practical applications, other processes can also be used to remove the etch barrier layer 120, and this embodiment does not limit this.

[0047] Step S5: Deposit a passivation layer 500 on the surface of the carrier wafer 300 and on the surface and sidewalls of the epitaxial layer 110 away from the carrier wafer.

[0048] Specifically, such as Figure 8 As shown, after the epitaxial layer 110 is exposed, a passivation layer 500 is deposited on the surface of the carrier wafer 300 (including the remaining portion 210' of the second silicon wafer 210 facing away from the carrier wafer, the sidewalls of the second silicon dioxide film layer 220, and the exposed area on the upper surface of the bonding interposer layer 400), and on the surface and sidewalls of the epitaxial layer 110 facing away from the carrier wafer. The passivation layer 500 is a conformal passivation layer. A conformal passivation layer refers to a passivation layer 500 with uniform thickness, completely conforming to the surface of the carrier wafer 300 and the contour of the epitaxial layer 110 facing away from the carrier wafer, achieving three-dimensional full coverage of the epitaxial layer 110. The conformal passivation layer 500 is deposited by methods such as CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The material of the passivation layer 500 can be Si...x N y It can be either SiO2 or Al2O3.

[0049] It is important to emphasize that this application adopts a process sequence of "substrate removal first, passivation layer deposition later," that is, the passivation layer 500 is deposited only after the substrate 130 and the etch barrier layer 120 are completely removed. Compared with the process sequence of "passivation layer deposition first, then substrate removal" in related technologies, the process sequence of this application avoids wafer warpage caused by stress introduced by the deposition of the passivation layer 500, thereby eliminating the interference of warpage on the uniformity of subsequent thinning and CMP processes.

[0050] The passivation layer 500 serves as a protective layer for the epitaxial layer 110, completely encapsulating the epitaxial layer 110 away from the surface and sidewalls of the supporting wafer. During subsequent CMP planarization of the occupant unit 200, it isolates the CMP polishing slurry from direct contact with the epitaxial layer 110, preventing chemical corrosion of InP by the polishing slurry and mechanical scratching of InP by the polishing particles. Moreover, the passivation layer 500 can also serve as a CMP stop layer, automatically stopping polishing when it reaches the passivation layer 500 during the CMP planarization process, preventing over-polishing damage to the epitaxial layer 110. Thirdly, the passivation layer 500 serves as an optical stray light suppression layer, suppressing unwanted stray light generated when the epitaxial layer 110 emits light, thereby improving the optical performance of the final laser device.

[0051] Step S6: Flatten the occupant unit 200.

[0052] Specifically, Figure 9 The wafer structure after planarization of the placeholder cell 200 is shown. The placeholder cell 200 is planarized using a passivation layer 500 as a stop layer. The planarization process includes mechanical thinning and CMP planarization of the placeholder cell 200, ensuring that the height of the placeholder cell 200 (i.e., the secondary thinning portion 210'' after thinning the remaining portion 210' of the second silicon wafer 210) facing away from the surface of the carrier wafer is substantially the same as the height of the passivation layer 500 covering the epitaxial layer 110 facing away from the surface of the carrier wafer. This achieves the required flatness of the entire reconstructed wafer surface, meeting the substrate flatness requirements of subsequent standard CMOS processes such as photolithography. Because the epitaxial layer 110 is completely encapsulated by the passivation layer 500, it is protected from corrosion by the polishing slurry and scratches by polishing particles during the CMP planarization process.

[0053] In some embodiments, after completing step S6 above, the wafer fabrication method of this application may further include: Step S7: Fabricate device structure 600 on the carrier wafer 300 after the planarization process is completed.

[0054] Specifically, such as Figure 10As shown, a device structure 600 is fabricated on a planarized carrier wafer 300. The device structure 600 is, for example, an on-chip laser. Exemplarily, the on-chip laser is, for example, an edge-emitting laser or a vertical-cavity surface-emitting laser. Specific processes include standard CMOS processes such as photolithography, etching, metallization, and electrode fabrication to process the epitaxial layer 110 into an actual laser, ultimately obtaining a working on-chip laser source on a silicon-based platform.

[0055] Thus, the wafer fabrication method provided in this embodiment, by employing the above steps S1 to S7, obtains a reconstructed wafer that can be used for on-chip laser fabrication.

[0056] As another technical solution, this application embodiment also provides a reconstructed wafer, which is fabricated based on the wafer fabrication method described above in this application embodiment. Please refer to... Figure 10 The reconstructed wafer includes a carrier wafer 300, die units 100 bonded to the carrier wafer 300, and placeholder units 200. The die unit 100 includes an epitaxial layer 110, the upper surface of which (i.e., the surface of the epitaxial layer facing away from the carrier wafer) and sidewalls are covered by a passivation layer 500. After planarization, the upper surface of the placeholder unit 200 is substantially at the same height as the upper surface of the passivation layer 500 covering the epitaxial layer 110, thereby achieving the required flatness of the entire reconstructed wafer surface and meeting the substrate flatness requirements of subsequent standard CMOS processes such as photolithography.

[0057] In some embodiments, the carrier wafer 300 is an SOI silicon photonics wafer or a TFLN-on-insulator wafer. The die unit 100 and the occupant unit 200 are bonded to the carrier wafer 300 via a bonding interposer layer 400, the material of which is, for example, Al2O3 or SiO2. The passivation layer 500 is a conformal passivation layer, and its material is Si. x N y Or Al2O3 or SiO2.

[0058] When the die unit 100 is bonded to the carrier wafer 300, it sequentially includes an epitaxial layer 110, an etch barrier layer 120, and a substrate 130 in a direction away from the carrier wafer 300. In the final structure of the reconstructed wafer, the substrate 130 and the etch barrier layer 120 are completely removed, leaving only the epitaxial layer 110. The upper surface and sidewalls of the epitaxial layer 110 are completely encapsulated by a passivation layer 500, which functions as a protective layer, a CMP stop layer, and an optical stray light suppression layer.

[0059] The placeholder unit 200 is a dummy die, made of, for example, monocrystalline silicon or polycrystalline silicon, preferably the same material as the carrier wafer 300. The size of the placeholder unit 200 is the same as the size of the die unit 100, or a combination of different sizes can be used depending on the layout requirements. The die unit 100 and the placeholder unit 200 are arranged in an array on the carrier wafer 300, with the placeholder unit 200 filling the empty areas between the die units 100, together covering the entire surface of the carrier wafer 300.

[0060] In summary, this application employs a two-step method of mechanical thinning and wet etching to remove the substrate 130. First, mechanical thinning rapidly removes the main thickness portion of the substrate 130, followed by wet etching to remove the remaining substrate (i.e., the remaining portion 130'). Compared to related technologies that use pure wet etching to remove relatively thick substrates, this application significantly reduces the amount of etching, shortens the etching time, and makes uniformity easier to control. This reduces the probability of micromask effects and lateral drilling, ensuring the flatness of the epitaxial layer's lower surface and the reliability of the bonding interface. Furthermore, after the substrate 130 and the etching barrier layer 120 are completely removed, a passivation layer 500 is deposited on the surface of the carrier wafer and on the surface and sidewalls of the epitaxial layer 110 away from the carrier wafer, ensuring that the passivation layer 500 completely encapsulates the epitaxial layer 110. Compared to the process sequence of "depositing a passivation layer first and then removing the substrate" in related technologies, this application can avoid wafer warpage caused by stress introduced by the deposition of the passivation layer 500, eliminating the interference of warpage on the uniformity of subsequent thinning and CMP processes. Simultaneously, during subsequent CMP planarization of the site cells 200, the passivation layer 500 can isolate the CMP polishing slurry from direct contact with the epitaxial layer, preventing chemical corrosion of InP by the polishing slurry and mechanical scratching of InP by polishing particles, thus ensuring the structural integrity of the epitaxial layer.

[0061] In addition, the passivation layer 500 can also serve as a CMP stop layer to prevent excessive wear damage to the epitaxial layer 110 during the CMP planarization process; at the same time, the passivation layer 500 can also serve as an optical stray light suppression layer to suppress unwanted stray light generated when the epitaxial layer 110 emits light, thereby improving the optical performance of the final device.

[0062] This application uses placeholder units 200 to fill the vacancies in non-InP regions on the carrier wafer, ensuring uniform stress on the entire carrier wafer surface during subsequent planarization and guaranteeing the consistency of the wafer surface flatness. After planarization, the surface of the placeholder units 200 facing away from the carrier wafer is substantially consistent with the upper surface of the passivation layer 500 covering the epitaxial layer, forming a flat reconstructed wafer surface that can be directly imported into a standard CMOS process line for subsequent photolithography, etching, metallization, and other processes.

[0063] The wafer fabrication method and reconstructed wafer of this application can overcome the limitations of InP wafer size, realize high-quality integration of InP materials on large-size silicon-based platforms, and can be directly applied to the fabrication of on-chip lasers, meeting the needs of various applications such as silicon photonics on-chip computing, lidar, and biosensing.

[0064] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0065] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of protection of the present invention is determined by the scope of the appended claims.

Claims

1. A wafer fabrication method, characterized in that, include: The die unit and the occupant unit are heterobonded to the carrier wafer. The die unit includes an epitaxial layer, an etching barrier layer and a substrate arranged sequentially in a direction away from the carrier wafer. The substrate and the occupancy unit are mechanically thinned; The remaining substrate is removed using a wet etching process, stopping at the etching barrier layer; Remove the corrosion barrier layer to expose the epitaxial layer; A passivation layer is deposited on the surface of the carrier wafer and on the surface and sidewalls of the epitaxial layer opposite to the carrier wafer. The spacer unit is flattened.

2. The wafer fabrication method according to claim 1, characterized in that, The carrier wafer includes SOI silicon photonics wafers or TFLN-on-insulator wafers.

3. The wafer fabrication method according to claim 1, characterized in that, The grain unit and the occupant unit are heterobonded to the carrier wafer through a bonding intermediary layer.

4. The wafer fabrication method according to claim 3, characterized in that, The material of the bonding interlayer includes Al2O3 or SiO2.

5. The wafer fabrication method according to claim 1, characterized in that, The mechanical thinning includes mechanical grinding, CMP grinding, or a combination of mechanical grinding and CMP grinding.

6. The wafer fabrication method according to claim 1, characterized in that, The method for preparing the grain unit includes: An epitaxial structure is provided, the epitaxial structure comprising a circular substrate and an etching barrier layer and an epitaxial layer sequentially disposed along a direction away from the circular substrate; The epitaxial structure is cut to obtain the grain unit.

7. The wafer fabrication method according to claim 1, characterized in that, The method for preparing the placeholder unit includes: Depositing a silicon dioxide film on a silicon wafer; The silicon wafer on which the silicon dioxide film is deposited is cut to obtain the placeholder unit.

8. The wafer fabrication method according to claim 1, characterized in that, The size of the occupant unit is the same as the size of the grain unit; and / or, the material of the occupant unit is the same as the material of the carrier wafer.

9. The wafer fabrication method according to claim 1, characterized in that, After the substrate is thinned, the remaining thickness of the substrate is less than or equal to 50 μm.

10. The wafer fabrication method according to claim 1, characterized in that, The flattening process for the occupant unit includes: The occupant unit is mechanically thinned and planarized.

11. A reconstructed wafer, characterized in that, It is made according to the wafer fabrication method according to any one of claims 1 to 10.

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