Load adaptive noise margin testing of circuit design

Abstract

To address noise impact on functional testing of logic cell of a circuit design, load adaptive processing is provided. The processing includes obtaining a plurality of noise margin data curves for different potential capacitive load on a logic cell. The processing includes performing noise impact on functional testing of a logic cell instance within the circuit design. The performing includes selecting a noise margin data curve of the plurality of curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional testing based on comparing a noise pulse at the logic cell instance with the selected noise margin data curve. Further, the processing includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance based on the logic cell instance of the circuit design failing the noise impact on the functional testing.

Description

BACKGROUND

[0001] The present disclosure relates, in one or more aspects, to facilitating a circuit design process within a computing environment, and more specifically, to noise margin verification testing of one or more logic cell instances of a circuit design.

[0002] Electronic design automation (EDA) tools utilize computer-aided design to aid in the development of complex electronic systems, such as integrated circuits, including very large scale integrated circuits, microprocessors, integrated circuit chips, and the like. Electronic design automation tools are used for circuit design simulation, design, and verification. These tools allow developers to predict circuit behavior before the circuit is manufactured, assemble circuit components, and predict the performance of the final circuit design.

[0003] Electronic design automation tools facilitate analysis and verification of a circuit design or physical design. Physical verification facilitates ensuring that the final integrated circuit functions correctly and meets specifications. SUMMARY

[0004] Certain shortcomings of the prior art are overcome and additional advantages are provided through the provision of a computer-implemented method that facilitates a circuit design process within a computing environment. The computer-implemented method includes obtaining a plurality of noise margin data curves for different potential capacitance loads on a logic cell of a circuit design. Additionally, the computer-implemented method includes performing a noise impact on a functional test of a logic cell instance of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitance load on the logic cell instance of the circuit design and determining whether the logic cell instance fails the noise impact on the functional test based on comparing a noise impulse at the logic cell instance during the noise impact on the functional test with the selected noise margin data curve. Additionally, the computer-implemented method includes initiating one or more actions to facilitate addressing the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test.

[0005] On the other hand, a computer program product is provided to facilitate circuit design processes within a computing environment. The computer program product includes a set of one or more computer-readable storage media, and program instructions commonly stored in the set of one or more computer-readable storage media, for causing at least one processor group to perform operations, wherein the operations include: acquiring multiple noise tolerance data curves for different potential capacitive loads on logic units of a circuit design, and subjecting a functional test of an instance of a logic unit within the circuit design to noise. This execution includes selecting a noise tolerance data curve from the multiple noise tolerance data curves based on the capacitive load of the logic unit instance of the circuit design, and determining whether the logic unit instance fails the noise effect on the functional test based on a comparison of a noise impulse at the logic unit instance during the noise effect on the functional test. Furthermore, the operations include initiating one or more actions based on a logic unit instance of the logic circuit design that fails the noise effect on the functional test, to resolve the failure of the logic unit instance during the noise effect on the functional test.

[0006] On the other hand, a computer system is provided to facilitate circuit design processes within a computer environment. The computer system includes at least one processor group, one or more computer-readable storage media, and program instructions, all stored in the one or more computer-readable storage media, for causing the at least one processor group to perform computer operations. The computer operations include obtaining multiple noise tolerance data curves of different potential capacitive loads on logic units of the circuit design, and performing noise impact testing on an instance of the logic unit within the circuit design. This execution includes selecting a noise tolerance data curve from the multiple noise tolerance data curves based on the capacitive load on the logic unit instance of the circuit design, and determining whether the logic unit instance fails the noise impact testing of the functional test based on a comparison of a noise impulse at the logic unit instance during the noise impact testing of the functional test with the selected noise tolerance data curve. Furthermore, the operation includes initiating one or more actions based on the failure of the logic unit instance of the circuit design to pass the noise impact testing of the functional test, to resolve the failure of the logic unit instance during the noise impact testing of the functional test.

[0007] This document describes and claims protection for computer-implemented methods, computer program products, and computer systems related to one or more aspects. Each embodiment of the computer-implemented method may be an embodiment of each computer program product and / or computer system, and vice versa. Furthermore, each embodiment is separable from and optional of each other. Furthermore, embodiments may be combined with each other. Each embodiment of the computer-implemented method may be combined with aspects and / or embodiments of each computer program product and / or computer system, and vice versa. In addition, services related to one or more aspects are also described and claimed herein.

[0008] Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein, and are considered a part of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0009] A preferred embodiment of the present application will now be described, by way of example only, and with reference to the following drawings:

[0010] Figure 1 One example of a computing environment including and / or using one or more embodiments of the present disclosure is depicted;

[0011] Figures 2A-2C One or more embodiments of a computer program product having an adaptive noise margin module in accordance with one or more embodiments of the present disclosure are depicted;

[0012] Figures 3A-3B One embodiment of an adaptive noise margin process in accordance with one or more embodiments of the present disclosure is described;

[0013] Figure 4 One example of a logic cell instance of a circuit design in accordance with one or more embodiments of the present disclosure is shown, and noise margin data curves associated therewith are characterized based on capacitive loads on the logic cell instance;

[0014] Figure 5 Multiple noise margin data curves for different potential capacitive loads on a logic cell instance of a circuit design in accordance with one or more embodiments of the present disclosure are illustrated;

[0015] Figure 6 One embodiment of a process of characterizing a noise margin data set for a logic cell of a circuit design in accordance with one or more embodiments of the present disclosure is shown;

[0016] Figure 7 One embodiment of a process of performing noise impact for functional testing of a logic cell instance of a circuit design using a noise margin data set in accordance with one or more embodiments of the present disclosure is described;

[0017] Figure 8 is a flow diagram of a design process for semiconductor design, fabrication, and / or test in accordance with one or more embodiments of the present disclosure;

[0018] Figure 9 Another example of integrated circuit fabrication in accordance with one or more embodiments of the present disclosure is depicted, including generating physical design data; and

[0019] Figure 10An exemplary high-level electronic design automation (EDA) tool flow through which embodiments of the present disclosure can be implemented is shown. DETAILED DESCRIPTION

[0020] In one or more aspects, a computer-implemented method of facilitating a circuit design process within a computing environment is provided. The computer-implemented method includes obtaining a plurality of noise margin data curves (i.e., noise immunity curves) for different potential capacitive loads on a logic cell of a circuit design. Additionally, the computer-implemented method includes performing a noise impact on a functional test of a logic cell instance of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design and determining whether the logic cell instance fails the noise impact on the functional test based on comparing a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the computer-implemented method includes initiating one or more actions to facilitate addressing the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test.

[0021] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design and selecting a particular noise margin data curve of the plurality of noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to the specified load capacitance on the logic cell instance, which conserves resources by reducing the number of false noise violations during testing and improves overall productivity of the circuit design process.

[0022] In embodiments, the different potential capacitive loads of the logic cell include a plurality of fixed capacitive loads of the logic cell. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting the different potential capacitive loads for the logic cell in one of a plurality of ways. In one approach, the plurality of fixed capacitive loads of the logic cell are defined for the logic cell, i.e., for a plurality or all instances of the logic cell of the circuit design. This approach of using the same fixed capacitive loads for the plurality or all logic cells can reduce the processing required to obtain the plurality of noise margin data curves for the different potential capacitive loads across the plurality of instances of the logic cell within the circuit design.

[0023] In embodiments, the different potential capacitive loads of the logic cell are selected for the logic cell in one of a plurality of ways. In one approach, the different potential capacitive loads of the logic cell are selected based on historical capacitive loads on one or more instances of the logic cell within one or more circuit designs, which facilitates obtaining a plurality of noise margin data curves for instances of the logic cell within a circuit design based on historically derived capacitive loads on the instances.

[0024] In embodiments, the different potential capacitive loads of the logic cell are selected to achieve a spaced apart noise margin data curve between a noise margin data curve for a selected minimum capacitive load condition of the logic cell and a noise margin data curve for a selected maximum capacitive load condition of the logic cell. According to one or more embodiments, the circuit design process within a computing environment can include selecting the different potential capacitive loads for the logic cell in one of a plurality of ways. In one approach, the different potential capacitive loads of the logic cell are selected to achieve a spaced apart noise margin data curve between a noise margin data curve for a selected minimum capacitive load condition and a noise margin data curve for a selected maximum capacitive load condition, which facilitates good span coverage between the noise margin data curves for the minimum and maximum load conditions, thereby facilitating good data curve coverage for a variety of capacitive loads on the logic cell.

[0025] In embodiments, at least one of the plurality of noise margin data curves is for a given capacitive load on the logic cell and is an interpolated data curve between representative noise margin data curves having specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads. By determining a given capacitive load on an instantiated logic cell and interpolating a noise margin data curve between representative noise margin data curves having specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads, a circuit design process within a computing environment is facilitated. In this manner, a useful noise margin data curve is facilitated.

[0026] In embodiments, performing includes determining the capacitive load on the logic cell instance as the sink load capacitance on the output pin of the logic cell instance. Advantageously, the load adaptive noise margin testing based on the sink load capacitance on the output pin of the logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be saved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load.

[0027] In embodiments, selecting a noise margin data curve of the plurality of noise margin data curves based on the capacitive load on the logic cell includes selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic cell instance that is closest to and below the determined sink load capacitance. By selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic cell instance that is closest to and below the determined sink load capacitance, the noise margin data curve better adapts to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional testing.

[0028] In embodiments, the selecting includes generating a noise margin data curve for the capacitive load on the logic cell instance, wherein the generating includes referencing one or more noise margin data curves of the plurality of noise margin data curves that are closest to one or more capacitive loads of the capacitive load on the logic cell instance, and generating another noise margin data curve for the capacitive load on the logic cell instance by interpolating. In one or more embodiments, the other noise margin data curve is the selected noise margin data curve used to determine whether the logic cell instance of the circuit design passes the noise impact on the functional testing. By interpolating the other noise margin data curve for the capacitive load on the logic cell instance, the selected noise margin data curve better adapts to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional testing.

[0029] In embodiments, the obtaining includes referencing a cell library file of the logic cell during the noise impact on the functional testing of the logic cell instance to select the noise margin data curve from the plurality of noise margin data curves. Advantageously, the plurality of noise margin data curves can be pre-characterized and stored in the cell library file of the logic cell for use during the noise impact on the functional testing of one or more logic cell instances, particularly to select the noise margin data curve based on the capacitive load on the output pin of the sink logic cell instance for use during the noise impact on the functional testing.

[0030] In another aspect, a computer program product is provided for facilitating a circuit design process within a computing environment. The computer program product includes a set of one or more computer-readable storage media and program instructions collectively stored in the set of one or more computer-readable storage media for causing at least one set of processors to perform operations including obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of a logic cell instance within the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional test based on comparing a noise pulse at the logic cell instance during the noise impact on the functional test with the selected noise margin data curve. Further, the operations include initiating one or more actions based on the logic cell instance of the logic circuit design failing the noise impact on the functional test to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test.

[0031] Advantageously, the computer program product facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the plurality of noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the impact of noise on a functional test of the logic cell instance is adapted or more closely adapted to the specified load capacitance on the logic cell instance, which conserves resources by reducing the number of false noise violations during testing, and improves overall productivity of the circuit design process.

[0032] In an embodiment of the computer program product, the different potential capacitive loads of the logic cell include a plurality of fixed capacitive loads of the logic cell. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting the different potential capacitive loads for the logic cell in one of a plurality of ways. In one approach, the plurality of fixed capacitive loads of the logic cell are defined for the logic cell, i.e., for a plurality or all instances of the logic cell of the circuit design. This approach of using fixed capacitive loads for the plurality or all logic cells can reduce the processing required to obtain a plurality of noise margin data curves for different potential capacitive loads on a plurality of instances of the logic cell within the circuit.

[0033] In embodiments of the computer program product, the different potential capacitive load of the logic cell is selected for the logic cell in one of a plurality of ways. In one approach, the different potential capacitive load of the logic cell is selected to achieve a spaced apart noise margin data curve between a noise margin data curve of a selected minimum capacitive load condition of the logic cell and a noise margin data curve of a selected maximum capacitive load condition of the logic cell. In this way, good data curve coverage of various capacitive loads on the logic cell is facilitated.

[0034] In embodiments of the computer program product, the different potential capacitive load of the logic cell is selected to achieve a spaced apart noise margin data curve between a noise margin data curve of a selected minimum capacitive load condition of the logic cell and a noise margin data curve of a selected maximum capacitive load condition of the logic cell. In one approach, the different potential capacitive load of the logic cell is selected to achieve a spaced apart noise margin data curve between a noise margin data curve of a selected minimum capacitive load condition of the logic cell and a noise margin data curve of a selected maximum capacitive load condition of the logic cell. In this way, good data curve coverage of various capacitive loads on the logic cell is facilitated.

[0035] In embodiments of the computer program product, at least one of the plurality of noise margin data curves is for a given capacitive load on the logic cell and is an interpolated data curve between representative noise margin data curves having specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads. In this way, a circuit design process within a computing environment is facilitated by selecting or determining a given capacitive load on the logic cell and interpolating a noise margin data curve between representative noise margin data curves having specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads. In this way, a useful noise margin data curve is facilitated.

[0036] In an embodiment of the computer program product, the performing includes determining a capacitive load on the output unit instance as a sink load capacitance on an output pin of the logic unit instance, and selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive load on the logic unit includes selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic unit instance that is closest to and below the determined sink load capacitance. Advantageously, the load adaptive noise margin testing based on the sink load capacitance on the output pin of the logic unit instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be saved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic unit instance that is closest to and below the determined sink capacitance, the noise margin data curve better adapts to the sink load capacitance on the logic unit instance, thereby reducing or minimizing false noise violations during the noise impact on functional testing.

[0037] In an embodiment of the computer program product, the performing includes determining a capacitive load on the output unit instance as a sink load capacitance on an output pin of the logic unit instance, and selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive load on the logic unit includes selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic unit instance that is closest to and below the determined sink load capacitance. Advantageously, the load adaptive noise margin testing based on the sink load capacitance on the output pin of the logic unit instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be saved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic unit instance that is closest to and below the determined sink capacitance, the noise margin data curve better adapts to the sink load capacitance on the logic unit instance, thereby reducing or minimizing false noise violations during the noise impact on functional testing.

[0038] In another aspect, a computer system is provided for facilitating a circuit design process within a computing environment. The computer system includes at least one processor complex, a set of one or more computer-readable storage media, and program instructions collectively stored in the set of one or more computer-readable storage media for causing the at least one processor complex to perform computer operations. The computer operations include obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell within the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load on the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Further, the operations include initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance of the circuit design failing the noise impact on the functional test.

[0039] Advantageously, the computer system facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the plurality of noise margin data curves based on a capacitive load on a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to the specified load capacitance on the logic cell instance, which conserves resources by reducing the number of false noise violations during testing, and improves overall productivity of the circuit design process.

[0040] In an embodiment of the computer system, the performing includes determining the capacitive load on the logic cell instance as a sink load capacitance on an output pin of the logic cell instance. Advantageously, the load-adaptive noise margin test based on the sink load capacitance on the output pin of the logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or address false noise violations, significant resources can be conserved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load.

[0041] In an embodiment of the computer system, selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive load on the logic cell includes selecting the noise margin data curve based on a hypothetical capacitive load on an output pin of the logic cell instance that is closest to and below the determined sink load capacitance. By selecting the noise margin data curve based on a hypothetical capacitive load on an output pin of the logic cell instance that is closest to and below the determined sink load capacitance, the noise margin data curve better accommodates the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0042] In an embodiment of the computer system, the selecting includes generating a noise margin data curve for the capacitive load on the logic cell instance, where the generating includes referencing one or more noise margin data curves of the plurality of noise margin data curves that are closest to one or more capacitive loads of the capacitive load on the logic cell instance, and generating another noise margin data curve for the capacitive load on the logic cell instance by interpolating. In one or more embodiments, the other noise margin data curve is the selected noise margin data curve used to determine whether the logic cell instance of the circuit design passed the noise impact on the functional test. By interpolating the other noise margin data curve for the capacitive load on the logic cell instance, the selected noise margin data curve better accommodates the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0043] In another aspect, a computer-implemented method, computer program product, and computer system implementing a process are provided, the process including obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance failed the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions to facilitate addressing the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test. In one embodiment, the different potential capacitive loads for the logic cell include a plurality of fixed capacitive loads for the logic cell. Moreover, the performing includes determining the capacitive load on the instance as a sink load capacitance on an output pin of the logic cell instance, and selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive

[0044] Advantageously, the computer-implemented method facilitates the circuit design process within a computing environment, particularly by reducing false noise violations, facilitating noise margin verification testing of one or more logic cell instances of a circuit design. By providing multiple noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the multiple noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on functional testing of the logic cell instance is adapted or more closely adapted to the specified load capacitance on the logic cell instance, which conserves resources and improves overall productivity of the circuit design process by reducing the number of false noise violations during testing. According to one or more embodiments, facilitating the circuit design process within a computing environment can include selecting different potential capacitive loads for a logic cell in one of a plurality of ways. In one approach, a plurality of fixed capacitive loads for a logic cell are defined for the logic cell, i.e., for a plurality or all instances of the logic cell of the circuit design. This approach of using the same fixed capacitive load for a plurality or all of the logic cells can reduce the processing required to obtain multiple noise margin data curves for different potential capacitive loads across multiple instances of the logic cells within the circuit design. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be conserved. Advantageously, the selected noise margin data curve is appropriate for the driving load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By selecting the noise margin data curve based on the closest and lower than the determined sink capacitance load of the assumed capacitive load on the output pin of the logic cell instance, the noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on functional testing.

[0045] In another aspect, a computer-implemented method, computer program product, and computer system are provided that implement a process that includes obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance failed the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test. In one embodiment, the different potential capacitive loads for the logic cell are based on historical capacitive loads on one or more instances of the logic cell within one or more circuit designs. Moreover, the performing includes determining the capacitive load on the instance as a sink load capacitance on an output pin of the logic cell instance, and selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive load of the cell includes selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic cell instance that is closest to and below the determined sink load capacitance.

[0046] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing multiple noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the multiple noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to a specified load capacitance on the logic cell instance, which saves resources by reducing the number of false noise violations during testing, and improves overall productivity of the circuit design process. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting different potential capacitive loads for a logic cell in a variety of ways. In one approach, different potential capacitive loads for a logic cell can be based on historical capacitive loads on one or more instances of the logic cell within one or more circuit designs, which can facilitate obtaining multiple noise margin data curves for logic cell instances within a circuit design based on historically derived capacitive loads on the instances. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be saved. Advantageously, the selected noise margin data curve is appropriate for the driving load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By selecting a noise margin data curve based on hypothetical capacitive loads on an output pin of a logic cell instance that are closest to and below a determined sink capacitance load, the noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on functional testing.

[0047] In another aspect, a computer-implemented method, computer program product, and computer system are provided that implement a process that includes obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance failed the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. In addition, the process includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test. In one embodiment, the different potential capacitive loads of the logic cell are selected to implement a spaced apart noise margin data curve between a noise margin data curve for a selected minimum capacitive load condition of the logic cell and a noise margin data curve for a selected maximum capacitive load condition of the logic cell of the circuit design. Further, the performing includes determining the capacitive load on the instance to be a sink load capacitance on an output pin of the logic cell instance, and selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive load of the cell includes selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic cell instance that is closest to and below the determined sink load capacitance.

[0048] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the plurality of noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact of a functional test of the logic cell instance is adapted or more closely adapted to a specified load capacitance on the logic cell instance, which conserves resources and improves overall productivity of the circuit design process by reducing the number of false noise violations during testing. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting different potential capacitive loads for a logic cell in one of a plurality of ways. In one approach, different potential capacitive loads are selected for the logic cell to obtain a spaced apart noise margin data curve between a noise margin data curve for a selected minimum capacitive load condition and a noise margin data curve for a selected maximum capacitive load condition, which facilitates good spaced apart coverage of the span between the noise margin data curves for the minimum and maximum load conditions, thereby facilitating good data curve coverage for a variety of capacitive loads on the logic cell. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations from testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, a significant amount of resources can be conserved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By selecting a noise margin data curve based on an assumed capacitive load closest to and below a determined sink capacitance load on an output pin of a logic cell instance, the noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the impact of noise on functional testing.

[0049] In another aspect, a computer-implemented method, computer program product, and computer system are provided that implement a process that includes obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance failed the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test. In one embodiment, at least one of the plurality of noise margin data curves is for a given capacitive load on the logic cell, and is an interpolated data curve between characterized noise margin data curves for the logic cell having specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads. Moreover, the performing includes determining the capacitive load on the instance to be a sink load capacitance on an output pin of the logic cell instance, and selecting the noise margin data curve of the plurality of noise margin data curves based on the capacitive load of the cell includes selecting the noise margin data curve based on a hypothetical capacitive load on the output pin of the logic cell instance that is closest to and below the determined sink load capacitance.

[0050] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve from the plurality of noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to a specified load capacitance on the logic cell instance, which saves resources by reducing the number of false noise violations during testing, and improves overall productivity of the circuit design process. By selecting or determining a given capacitive load on a logic cell, and interpolating between noise margin data curves having representations of specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads, facilitates a circuit design process within a computing environment. In this way, useful noise margin data curves are obtained. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the work to identify and / or process false noise violations, significant resources can be saved. Advantageously, the selected noise margin data curve is appropriate for the driving load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By selecting a noise margin data curve based on the closest and lower than the determined sink capacitance load on an output pin of a logic cell instance, the noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0051] In another aspect, a computer-implemented method, computer program product, and computer system are provided that implement a process that includes obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the instance of the logic cell of the circuit design, and determining whether the instance of the logic cell fails the noise impact on the functional test based on a comparison of a noise pulse at the instance of the logic cell during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions based on the instance of the logic cell of the circuit design failing the noise impact on the functional test to facilitate resolution of the failure of the instance of the logic cell during the noise impact on the functional test. In one embodiment, the different potential capacitive loads of the logic cell include a plurality of fixed capacitive loads of the logic cell. Moreover, the performing includes determining the capacitive load on the instance as a sink load capacitance on an output pin of the instance of the logic cell, and the selecting includes generating a noise margin data curve for the capacitive load on the instance of the logic cell. The generating includes interpolating another noise margin data curve for the capacitive load on the instance of the logic cell by referencing one or more noise margin data curves that are closest to the capacitive load of the plurality of noise margin data curves, where the other noise margin data curve is the selected noise margin data curve used to determine whether the instance of the logic cell of the circuit design passes the noise impact on the functional test.

[0052] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing multiple noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the multiple noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to the particular load capacitance on the logic cell instance, which conserves resources and improves overall productivity of the circuit design process by reducing the number of false noise violations during testing. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting different potential capacitive loads for a logic cell in one of a plurality of ways. In one approach, a plurality of fixed capacitive loads for a logic cell are defined for the logic cell, i.e., for a plurality or all instances of the logic cell of the circuit design. This approach of using the same fixed capacitive load for a plurality or all of the logic cells can reduce the processing required to obtain multiple noise margin data curves for different potential capacitive loads across multiple instances of the logic cells within the circuit design. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be conserved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By interpolating another noise margin data curve for a capacitive load on the logic cell instance, the selected noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0053] In another aspect, a computer-implemented method, computer program product, and computer system are provided that implement a process that includes obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance of the circuit design failing the noise impact on the functional test. In one embodiment, the different potential capacitive loads for the logic cell are based on historical capacitive loads on one or more instances of the logic cell within one or more circuit designs. Moreover, the performing includes determining the capacitive load on the instance as a sink load capacitance on an output pin of the logic cell instance, and the selecting includes generating a noise margin data curve for the capacitive load on the logic cell instance. The generating includes interpolating another noise margin data curve for the capacitive load on the logic cell instance by referencing one or more noise margin data curves that are closest to one or more capacitive loads of the capacitive load on the logic cell instance, where the other noise margin data curve is the selected noise margin data curve used to determine whether the logic cell instance of the circuit design passes the noise impact on the functional test.

[0054] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing multiple noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the multiple noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to the particular load capacitance on the logic cell instance, which saves resources by reducing the number of false noise violations during testing, and improves overall productivity of the circuit design process. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting different potential capacitive loads for a logic cell in a variety of ways. In one approach, the different potential capacitive loads for a logic cell can be based on historical capacitive loads on one or more instances of the logic cell within one or more circuit designs, which can facilitate obtaining multiple noise margin data curves for logic cell instances within a circuit design based on historically derived capacitive loads on the instances. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, a significant amount of resources can be saved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By interpolating another noise margin data curve for a capacitive load on the logic cell instance, the selected noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0055] In another aspect, a computer-implemented method, computer program product, and computer system implementing a process are provided, the process including obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance of the circuit design failing the noise impact on the functional test. In one embodiment, the different potential capacitive loads of the logic cell are selected to implement a spaced apart noise margin data curve between a noise margin data curve for a selected minimum capacitive load condition of the logic cell and a noise margin data curve for a selected maximum capacitive load condition of the logic cell of the circuit design. Moreover, the performing includes determining the capacitive load on the instance to be a sink load capacitance on an output pin of the logic cell instance, and the selecting includes generating a noise margin data curve for the capacitive load on the logic cell instance. The generating includes interpolating another noise margin data curve for the capacitive load on the logic cell instance by referencing one or more noise margin data curves closest to one or more capacitive loads of the capacitive load of the plurality of noise margin data curves, where the other noise margin data curve is the selected noise margin data curve used to determine whether the logic cell instance of the circuit design passes the noise impact on the functional test.

[0056] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve of the plurality of noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to a specified load capacitance on the logic cell instance, which conserves resources and improves overall productivity of the circuit design process by reducing the number of false noise violations during testing. According to one or more embodiments, facilitating a circuit design process within a computing environment can include selecting different potential capacitive loads for a logic cell in one of a plurality of ways. In one approach, different potential capacitive loads for a logic cell are selected to obtain a spaced apart noise margin data curve between a noise margin data curve for a selected minimum capacitive load condition and a noise margin data curve for a selected maximum capacitive load condition, which facilitates a good interval coverage of a span between the noise margin data curves for the minimum and maximum load conditions, thereby facilitating a good data curve coverage for a variety of capacitive loads on the logic cell. Advantageously, load adaptive noise margin testing based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, a significant amount of resources can be conserved. Advantageously, the selected noise margin data curve is tailored to the driving load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By interpolating another noise margin data curve for a capacitive load on the logic cell instance, the selected noise margin data curve is better adapted to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0057] In another aspect, a computer-implemented method, computer program product, and computer system implementing a process are provided, the process including obtaining a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and performing a noise impact on a functional test of an instance of the logic cell of the circuit design. The performing includes selecting a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional test based on a comparison of a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Additionally, the process includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance during the noise impact on the functional test based on the logic cell instance failing the noise impact on the functional test. In one embodiment, at least one of the plurality of noise margin data curves for different potential capacitive loads of the logic cell is for a given capacitive load on the logic cell, and is an interpolated data curve between characterized noise margin data curves having specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads. Further, the performing includes determining the capacitive load on the instance as a sink load capacitance on an output pin of the logic cell instance, and the selecting includes generating a noise margin data curve for the capacitive load on the logic cell instance. The generating includes interpolating another noise margin data curve for the capacitive load on the logic cell instance by referencing one or more noise margin data curves closest to one or more capacitive loads of the capacitive load of the plurality of noise margin data curves, where the other noise margin data curve is the selected noise margin data curve used to determine whether the logic cell instance of the circuit design passes the noise impact on the functional test.

[0058] Advantageously, the computer-implemented method facilitates a circuit design process within a computing environment, particularly a noise margin verification test of one or more logic cell instances of a circuit design, by reducing false noise violations. By providing a plurality of noise margin data curves for different potential capacitive loads on a logic cell of a circuit design, and selecting a particular noise margin data curve from the plurality of noise margin data curves based on a capacitive load of a logic cell instance of the circuit design, the noise impact on a functional test of the logic cell instance is adapted or more closely adapted to a specified load capacitance on the logic cell instance, which conserves resources and improves overall productivity of the circuit design process by reducing the number of false noise violations during testing. By selecting or determining a given capacitive load on a logic cell, and interpolating between noise margin data curves having representations of specified capacitive loads on the logic cell, where the given capacitive load is between the specified capacitive loads, the circuit design process within a computing environment is facilitated. In this way, a useful noise margin data curve is obtained. Advantageously, the load adaptive noise margin test based on sink load capacitance on an output pin of a logic cell instance reduces or minimizes false noise violations in testing, which improves productivity of the circuit design process. By minimizing the effort to identify and / or process false noise violations, significant resources can be conserved. Advantageously, the selected noise margin data curve is tailored to the drive load, thereby avoiding the inherent negative impact of existing noise on functional testing using a constant minimum load. By interpolating another noise margin data curve for a capacitive load on the logic cell instance, the selected noise margin data curve better adapts to the sink load capacitance on the logic cell instance, thereby reducing or minimizing false noise violations during the noise impact on the functional test.

[0059] Aspects of the disclosure, and certain features and details thereof, will be described in connection with (multiple) non-limiting examples shown in the figures. Descriptions of well-known systems, devices, tools, techniques, etc. will be omitted so as not to unnecessarily complicate the detailed description. It should be understood, however, that the detailed description and specific examples, while indicating aspects of the disclosure, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and / or arrangements, within the spirit and / or scope of the underlying inventive concept, can be made by those skilled in the art. Further, it should be noted that the figures are not drawn to scale and that the dimensions of the various features can be exaggerated for the sake of clarity. It should be further noted that many of the aspects and features described herein can be combined with each other and / or combined with other aspects and features described herein, unless the context clearly dictates otherwise.

[0060] It is also noted that the following describes illustrative embodiments using only the handiest of the numerous illustrative examples of circuits, codes, designs, architectures, protocols, layouts, schematics, systems, and tools as examples and not limitation. Additionally, some of the illustrative examples described herein are described as, and can implicitly reference, material, an action and / or actions, or steps and / or steps of a method, process, and / or procedure. The same, or similar, reference numbers can be used in the figures and / or the specification as they represent the same or similar functionalities of the illustrative embodiments. Unless otherwise specified, an illustrative embodiment can be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When the software and / or firmware is involved, an illustrative embodiment can be implemented as any desirable piece of code, or any set of codes, that contain one or more instructions for implementing a specified task or tasks. An illustrative embodiment can be implemented using one or more computer programs or code, and / or one or more computer program products.

[0061] As understood by those skilled in the art, program code referred to in this application can include software and / or hardware. For example, program code in certain embodiments of the present disclosure can utilize a software-based implementation of the described functionality, while other embodiments can include fixed-function hardware. Certain embodiments combine both types of program code. Examples of program code, also referred to as one or more programs, are shown in Figure 1 include an operating system 122 and an adaptive noise margin module 200 stored in persistent storage 113.

[0062] One or more aspects of the present disclosure are incorporated into, performed by, and / or used with a computing environment. As an example, a computing environment can have various architectures and various types, including but not limited to: personal computing, client-server, distributed, virtual, emulated, partitioned, non-partitioned, cloud-based, quantum, grid, time-shared, clustered, peer-to-peer, mobile, having one or more nodes, having one or more processors, and / or any other type of environment and / or configuration, etc. A processing (or multiple processing) capable of performing, for example, adaptive noise margin processing, as disclosed herein. Aspects of the present disclosure are not limited to a specified architecture or environment.

[0063] Before further description of the detailed embodiments of the present disclosure, reference is made to the following Figure 1 Discussion includes and / or uses examples of computing environments incorporating and / or using one or more aspects of the present disclosure.

[0064] Various aspects of the present disclosure are described in terms of illustrative embodiments disclosed in the descriptive text, flow charts, block diagrams, and / or diagrams of computer systems and / or machine logic included in computer program product (CPP) embodiments. With respect to any flow chart, flow diagrams can be regarded, from a technical perspective, as an algorithm designed to achieve a technical result. The order in which operations are described is not necessarily the order in which the operations are performed. For example, two operations shown in succession can in fact be executed substantially concurrently or in the reverse order that described. Also, specific logical circuitry, software, hardware, tools and / or data processing environments referred to in the description above are examples only.

[0065] A computer program product embodiment (“CPP embodiment” or “CPP”) is a term used in this disclosure to describe any set of one or more storage media (also referred to as “media”) that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” refers to any tangible device capable of holding and storing instructions for use by a computer processor. Without limitation, computer-readable storage media can be electronic, magnetic, optical, electromagnetic, semiconductor, mechanical, or any suitable combination of the foregoing. Some known types of storage devices comprising these media include: magnetic disks, hard drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random access memory (SRAM), compact discs read-only memory (CD-ROM), digital versatile discs (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch-cards or holes / tabs, or any suitable combination of the foregoing. Computer-readable storage media, as used in this disclosure, should not be construed as being a storage of storage per se in the form of a transitory signal, such as radio or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or optical cables, optical pulses through optical cables, electronic signals through wire cables, and / or other transmission media. As those skilled in the art will readily appreciate, data is typically moved at some incidental point in time during normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not render the storage device transitory, as the data is not transitory while stored.

[0066] The computing environment 100 contains an example of an environment for running at least some computer code involved in performing the methods of the present invention, such as the adaptive noise margin module 200. For the module 200, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including a processing circuit 120 and a cache 121), a communication fabric 111, a volatile memory 112, a persistent storage 113 (including an operating system 122 and the module 200 as described above), a peripheral device set 114 (including a user interface (UI) device set 123, a storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud coordination module 141, a host physical machine set 142, a virtual machine set 143, and a container set 144.

[0067] The computer 101 can take the form of a desktop computer, a laptop computer, a tablet computer, a smart phone, a smart watch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device capable of running a program, accessing a network, or querying a database, such as the remote database 130. As is well known in the computer arts, and depending on the technology, the performance of the computer-implemented method can be distributed among multiple computers and / or among multiple locations. On the other hand, in this presentation of the computing environment 100, the detailed discussion is centered on a single computer, specifically the computer 101, to make the presentation as simple as possible. The computer 101 can be located in the cloud, even though it is not shown in the figure. On the other hand, the computer 101 need not be in the cloud, unless that can be affirmatively stated to any degree. Figure 1

[0068] The processor complex 110 includes one or more computer processors of any type now known or developed in the future. The processing circuitry 120 can be distributed across multiple packages, such as multiple co-integrated circuit chips. The processing circuitry 120 can implement multiple processor threads and / or multiple processor cores. The cache 121 is memory located in the processor chip package(s) that is typically used for data or code that threads or cores running on the processor complex 110 should have fast access to. Cache memory is typically divided into multiple levels according to relative proximity to the processing circuitry. Alternatively, some or all of the cache of the processor complex can be located “off-chip.” In some computing environments, the processor complex 110 can be designed to work with qubits and perform quantum computations.

[0069] The computer-readable program instructions are typically loaded onto the computer 101 to cause the processor complex 110 of the computer 101 to execute a series of operational steps to implement the computer-implemented method, so that the instructions so executed will instantiate the methods specified in the flowcharts and / or narrative descriptions of the computer-implemented method contained in this document (collectively, “the methods of the invention”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as the cache 121 and other storage media discussed below. The processor complex 110 accesses the program instructions and related data to control and direct the execution of the methods of the invention. In the computing environment 100, at least some of the instructions (or logic) for performing the methods of the invention can be stored (or located) in the module 200 in the persistent storage 113.

[0070] ​The communication fabric 111 is a signal-conducting pathway that allows the various components of the computer 101 to communicate with each other. Typically, this fabric is composed of switches and conductive pathways, such as those that make up a bus, a bridge, a physical input / output port, and the like. Other types of signal communication pathways can be used, such as fiber-optic communication pathways and / or wireless communication pathways.

[0071] The volatile memory 112 is any type of volatile memory now known or developed in the future. Examples include dynamic random access memory or static random access memory. Typically, volatile memory is characterized by random access, but this is not required unless explicitly stated. In the computer 101, the volatile memory 112 is located in a single package and is located inside the computer 101, but, alternatively or additionally, the volatile memory can be distributed across multiple packages and / or located outside with respect to the computer 101.

[0072] The persistent storage 113 is any form of non-volatile storage for a computer, now known or to be developed in the future. The non-volatility of the storage means that the data stored is maintained regardless of whether power is provided to the computer 101 and / or directly to the persistent storage 113. The persistent storage 113 can be read-only memory (ROM), but typically at least a portion of the persistent storage allows data to be written, deleted, and rewritten. Some common forms of persistent storage include magnetic disks and solid-state storage devices. The operating system 122 can take a variety of forms, such as various known proprietary operating systems or an open-source portable operating system interface type of operating system that employs a kernel. The code contained in the module 200 typically includes at least some computer code involved in performing the methods of the present invention.

[0073] The peripheral device group 114 includes the peripheral devices of the computer 101. The data communication connections among the peripheral devices and other components of the computer 101 can be implemented using a variety of well-known means, for example, Bluetooth connections, near-field communication (NFC) connections, cable connections (such as universal serial bus (USB) type cables), plug-in connections (such as secure digital (SD) cards), connections through local area networks, or even connections through wide area networks (such as the Internet). In various embodiments, the UI device group 123 can include components such as display screens, speakers, microphones, wearable devices (such as goggles and smart watches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. The storage device 124 is an external storage device, such as an external hard drive, or a pluggable storage device, such as an SD card. The storage device 124 can be persistent and / or volatile. In some embodiments, the storage device 124 can take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where the computer 101 is required to have a large amount of storage space (for example, in cases where the computer 101 stores and manages a large database locally), this storage space can be provided by peripheral storage devices designed for storing large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The Internet of Things sensor group 125 consists of sensors that can be used for Internet of Things applications. For example, one sensor can be a thermometer, and another sensor can be a motion detector.

[0074] The network module 115 is a collection of computer software, hardware, and firmware that allows the computer 101 to communicate with other computers through the wide area network 102. The network module 115 can include hardware such as a modem or Wi-Fi signal transceiver, software for packaging and / or unpackaging data for transmission over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control functions and network forwarding functions of the network module 115 are performed on the same physical hardware device. In other embodiments (for example, embodiments that utilize software-defined networking (SDN)), the control functions and forwarding functions of the network module 115 are performed on physically separate devices, such that the control functions manage multiple different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can generally be downloaded to a computer 101 from an external computer or external storage device through the network module 115, which contains a network adapter card or network interface.

[0075] The wide area network 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances through any technology now known or later developed for transmitting computer data. In some embodiments, the wide area network can be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in the local area network (e.g., a Wi-Fi network). Wide area networks and / or local area networks typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0076] The end user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the business operating the computer 101), and can take any form discussed above in connection with the computer 101. The EUD 103 typically receives useful data from the operation of the computer 101. For example, in the hypothetical case where the computer 101 is designed to provide recommendations to end users, the recommendations would typically be transmitted from the network module 115 of the computer 101 to the EUD 103 through the wide area network 102. In this manner, the EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, the EUD 103 can be a client device such as a thin client, a fat client, a mainframe computer, a desktop computer, etc.

[0077] The remote server 104 is any computer system that provides at least some data and / or functionality to the computer 101. The remote server 104 can be controlled and used by the same entity operating the computer 101. The remote server 104 represents a machine that collects and stores useful data for use by other computers (e.g., the computer 101). For example, in the hypothetical case where the computer 101 is designed and programmed to provide recommendations based on historical data, the historical data can be provided to the computer 101 from a remote database 130 of the remote server 104.

[0078] The public cloud 105 is any computer system usable by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, especially data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing often utilizes resource sharing to achieve consistency and economies of scale. Direct and active management of the computing resources of the public cloud 105 is performed by computer hardware and / or software of the cloud coordination module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers that make up the host physical machine group 142, which is the world of physical computers in and / or available to the public cloud 105. The virtual computing environments (VCEs) typically take the form of virtual machines from the virtual machine group 143 and / or containers from the container group 144. It can be appreciated that these virtual circuits can be stored as images and can be transferred as images or between the various physical machine hosts after instantiation of the VCE. The gateway 140 is a collection of computer software, hardware, and firmware that allows the public cloud 105 to communicate over the wide area network 102.

[0079] Virtualized computing environments (VCEs) will now be further explained. VCEs can be stored as “images.” New active instances of VCEs can be instantiated from images. Virtual machines and containers are two common types of virtual circuits. Containers are VCEs that use operating system-level virtualization. This refers to operating system functionality that allows multiple independent user space instances, called containers, to exist. From the perspective of a running program, these independent user space instances often appear as real computers. Computer programs running on a normal operating system can utilize all of the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container, a feature known as containerization.

[0080] In addition to computing resources being usable by only a single enterprise, the private cloud 106 is similar to the public cloud 105. Although the private cloud 106 is depicted as being in communication with the wide area network 102, in other embodiments, the private cloud can be completely disconnected from the internet and only accessible through a local / private network. A hybrid cloud is composed of multiple different types of clouds (e.g., private clouds, community clouds, or public clouds), often implemented separately by different vendors. Each of the multiple clouds is an independent and discrete entity, but the larger hybrid cloud architecture is brought together through standardization or proprietary technology, enabling coordination, management, and / or data / application portability between the multiple constituent clouds. In this embodiment, the public cloud 105 and the private cloud 106 are both part of a larger hybrid cloud.

[0081] The computing environment described above is but one example of a computing environment that incorporates, performs, and / or uses one or more aspects of the present disclosure. Other examples are possible as well. Moreover, in one or more embodiments, Figure 1 one or more components / modules need not be included within the computing environment and / or used in connection with one or more embodiments of the present disclosure. Additionally, in one or more embodiments, additional and / or other components / modules can be used. Other variations are possible as well.

[0082] By way of example, reference is first made to Figures 2A-3B One or more embodiments of an adaptive noise margin module and process are described. Figures 2A-2C One or more embodiments of an adaptive noise margin module 200 that includes code or instructions that perform an adaptive noise margin process in accordance with one or more embodiments of the present disclosure are depicted, and Figure 3A - Figure 3C depicts one embodiment of an adaptive noise margin process.

[0083] Reference is made to Figures 1-2C In one example, the adaptive noise margin module 200 includes various sub-modules for performing the process in accordance with one or more embodiments of the present disclosure. The sub-modules are, for example, computer readable program code (e.g., instructions) and computer readable media (e.g., persistent storage (e.g., persistent storage 113, such as a disk) and / or cache (e.g., cache 121). The computer readable media can be part of a computer program product and can be executed by and / or using one or more computers (e.g., computer 101); one or more processor groups 110 Figure 1 ); a processor, such as one or more processors of processor group 110; and / or a processing circuit, such as a processing circuit of processor group 110, etc.

[0084] As described above, Figures 2A-2C One or more embodiments of the adaptive noise margin module 200 are described, which in one or more embodiments, include or facilitate an adaptive noise margin process. In Figures 2A-2CIn embodiments, the adaptive noise margin module 200 includes, as an example sub-module, a noise margin dataset sub-module 202 to facilitate obtaining a plurality of noise margin data curves (i.e., noise immunity curves) for different potential capacitive loads on a logic cell of a circuit design. Additionally, in one or more embodiments, the adaptive noise margin module 200 includes a noise impact on functional test sub-module 204 to perform a noise impact on a functional test of a logic cell instance of a circuit design. In one or more embodiments, the noise impact on functional test sub-module 204 includes a noise margin data curve selection sub-module 206 to select a noise margin data curve of the plurality of noise margin data curves based on a capacitive load of the logic cell instance of the circuit design. Additionally, in one or more embodiments, the noise impact on functional test sub-module 204 includes a noise pulse versus selected data curve comparison sub-module 208 to determine whether the logic cell instance fails the noise impact on the functional test based on comparing a noise pulse at the logic cell instance during the noise impact on the functional test to the selected noise margin data curve. Note that "noise impact on functional test" as used herein refers to a circuit design analysis to determine, for example, whether a size of a noise pulse in a selected line (created when one or more adjacent lines switch) is above a certain margin threshold (i.e., the selected noise margin data curve (or noise immunity curve)). If the threshold is exceeded, it is possible that the correct logic state of the line will be disturbed or corrupted, resulting in a computational error, sometimes referred to as "noise disturbance." The threshold can be defined and measured at the input of a logic gate, and thus the intelligent selection of noise margin data curves or noise immunity curves on logic gates is discussed herein. In one or more embodiments, the adaptive noise margin module 200 further includes a noise impact on functional test action sub-module 210 to initiate or generate one or more actions based on the logic cell instance of the circuit design that fails the noise impact on the functional test to facilitate resolving the failed physical design behavior during the noise impact on the functional test. In one or more embodiments, the one or more actions can include one or more automated processes to facilitate resolving or correcting the physical design that failed the noise impact on the functional test. For example, in one or more embodiments, one or more characteristics of the logic cell instance, or a routing of a circuit or logic gate as a driver, or another embodiment of the circuit design can be adjusted based on the noise violation, and the process repeated to perform the noise impact on the functional test of the adjusted logic cell instance / circuit design.

[0085] Figure 2BOne embodiment of the noise margin dataset submodule 202 is described, which in one or more embodiments can include a noise margin data curve reference submodule 212 to reference a pre-characterized noise margin dataset or table for a logic cell of a circuit design, where the noise margin dataset includes a plurality of noise margin data curves, including noise margin data curves for different potential capacitance loads on the logic cell, as described herein.

[0086] In Figure 2C Another embodiment of the noise margin dataset submodule 202 is shown in Figure 2C The noise margin dataset submodule 202 of the embodiment includes a noise margin data curve storage submodule 218 to store the determined noise margin data curves for the different identified potential capacitance loads of the logic cell. In one or more embodiments, the noise margin dataset can be stored in a cell library file for the logic cell, such as a cell library file for the input pins of the logic cell, for reference during functional testing of noise-affected logic cell instances, as described herein.

[0087] Note that although various submodules are described herein, the adaptive noise margin module process (e.g., as disclosed) can use or include additional, fewer, and / or different submodules. A specified submodule can include additional code, including code for other submodules, or less code. Also, more and / or less submodules can be used. Many variations are possible.

[0088] Advantageously, in one or more embodiments, an improved circuit design process within a computing environment is provided. In one or more embodiments, circuit design verification is facilitated by adjusting the noise margin of logic cell instances based on their load capacitance to address the noise impact on functional verification testing. In one or more embodiments, multiple load-based noise margin data curves (i.e., noise suppression curves) are used to reduce pessimism during noise analysis without impacting runtime by generating appropriately pre-characterized data curves based on potential output capacitive loads (e.g., capacitive loads on the gate outputs of logic cells). In real macros, significant time is saved in terms of reducing the noise impact on function violations when using adaptive noise margin processing as described herein, and typically, the noise relaxation distribution shifts to the right, providing more positive relaxation.

[0089] In one or more embodiments, according to one or more embodiments of the present disclosure, the adaptive noise tolerance module is used to perform adaptive noise tolerance processing. Figures 3A-3B An example of adaptive noise tolerance processing 300 is depicted, such as that disclosed herein. In one or more embodiments, this processing is performed by a computer (e.g., computer 101). Figure 1 )) and / or one or more processor groups (e.g., Figure 1 The processing is executed by the processor or processing circuitry of processor group 110. In one example, the code or instructions implementing the processing are part of a module (e.g., adaptive noise tolerance module 200). In other examples, the code may be contained in one or more other modules and / or one or more other submodules of one or more other modules. There are several options.

[0090] like Figure 3A As shown, in one example, on one or more computers (e.g. Figure 1 Adaptive noise tolerance processing 300 executed on a computer 101, one or more processor groups (e.g., Figure 1 The processor group 110 (e.g., the processor of the processor group's processing circuitry) obtains a noise tolerance dataset 302 of the logic cells of the circuit design. In one or more embodiments, obtaining the noise tolerance dataset can include referencing, or in association with, a pre-characterized noise tolerance dataset contained in a cell library file of the logic cells during or in connection with functional testing of the logic cell instance to select a noise tolerance data curve from a plurality of noise tolerance data curves in the dataset. Figure 3BAnother embodiment is shown in which obtaining a noise margin dataset 302 can include characterizing a plurality of noise margin data curves 312 by, for example, identifying sample capacitance loads 314 for the logic cell and determining a respective noise margin data curve 316 for each identified capacitance load. In one or more embodiments, the different capacitance loads on the logic cell can include a plurality of fixed sink capacitance loads on the logic cell. In one or more other embodiments, the different potential capacitance loads on the logic cell can be based on historical capacitance loads on instances of the logic cell, such as one or more other circuit designs or instances of the same circuit design. In one or more other embodiments, the different potential capacitance loads on the logic cell can be selected to achieve a spaced apart noise margin data curve between a noise data curve for a selected or specified minimum capacitance load condition on the logic cell and a noise margin data curve for a selected or specified maximum capacitance load condition on the logic cell of the circuit design. In one or more embodiments, Figure 3B The obtaining a noise margin dataset process of

[0091] As shown in Figure 3A one or more embodiments, the noise adaptive margin process 300 also includes performing a noise impact 304 on a functional test of an instance of a logic cell of the circuit design. In embodiments, performing a noise impact on the functional test includes selecting a noise margin data curve 306 from the plurality of noise margin data curves of the noise margin dataset of the logic cell and comparing a noise pulse at the instance of the logic cell to the selected noise margin data curve 308 to determine whether the instance of the logic cell fails or passes the noise impact on the functional test based on the comparison. In embodiments, the adaptive noise margin process 300 also includes initiating or generating one or more actions to facilitate resolving a noise violation 310 based on a failure of the instance of the logic cell of the circuit design, such as adjusting one or more characteristics of the instance of the logic cell and / or the circuit design to facilitate the logic cell passing a noise verification process of the circuit design.

[0092] As previously mentioned, electronic design automation (EDA) tools facilitate the development of complex electronic systems, such as integrated circuits, including very large scale integrated circuits, microprocessors, and integrated circuit chips, using computer-aided design. Electronic design automation tools are used for circuit design simulation, design, and verification. These tools allow developers to predict circuit behavior before circuit verification, assemble circuit components, and predict performance of the final circuit design. In one or more embodiments, electronic design automation tools also facilitate analysis and verification of circuit designs or physical designs. Physical verification facilitates ensuring that the final integrated circuit operates correctly and meets specifications.

[0093] In very large-scale integrated circuit (VLSI) designs or chips, standard library cells (such as gates) are building blocks for more complex random logic macros (RLMs) that provide a specific function within the circuit design. The behavior of these cells is characterized using circuit simulation programs, including metrics regarding timing, authority, and noise (also known as signal integrity). Noise characteristics involve simulating the behavior of a cell as noise propagates from each input to its output. A simple and efficient way to describe the noise characteristics of a cell is to generate a noise rejection curve (NRC), also known here as a noise tolerance data curve, for each input of the cell or gate, and to report how much noise is present at each output of the cell. This process also calculates the output impedance (resistance) value so that a reasonable driver model can be used when the cell drives a network to the gates of random logic macros (RLMs) during noise impact on function (NIOF) testing or analysis. An electronic design automation tool file containing noise rejection curves and output noise and output impedance values ​​is called a noise summary (NA). Traditionally, a noise summary is a static noise summary because it assumes that the cell drives a fixed, well-defined load and a fixed, standard average noise pulse propagating from the input to the output.

[0094] The methods described above for determining cell noise summaries are a way to characterize cells (or gates) and generate noise summaries for custom macros. However, a drawback of this method is the use of overly pessimistic output pin load capacitance values, which can affect the noise margin at the cell inputs due to the assumed fixed load. Generally, the minimum acceptable load of a standard cell is used in practice to illustrate the worst-case scenario. In many cases, this overly pessimistic output noise can produce false failures during noise-affected cell functionality testing. This paper discloses computer-implemented methods, computer program products, and computer systems for addressing this problem by providing more realistic noise summaries for cells (e.g., standard library cells in circuit design).

[0095] Regarding the noise impact on functional testing or verification, a component of the noise rule is the Noise Rejection Ratio (NRC), which represents the amount of noise the input can tolerate for a given pulse width before the output causes a noise violation. Figure 4 An example of this situation is described in the text, where the characterized cell 400 (e.g., an inverter) has an effective capacitance C partially based on the output line length. eff And in one example, the load is in Figure 4 In the example, the inverter-loaded gate 410 is used, and the noise evaluation point 411 is located at the output of the inverter-loaded gate 410. As mentioned above, traditionally, standard library cells or gates are characterized by a constant minimum capacitive load, such as a minimum effective capacitance C of 1 fF. effHowever, in actual circuit design, most cells (or gates) drive much higher loads, making the noise rejection curve (NRC) 401 relatively (and in some cases overly) pessimistic of the noise impact on today's functional tests, resulting in excessive noise disturbance during testing.

[0096] A computer-implemented method, computer program product, and computer system are disclosed that overcome the above-mentioned shortcomings of conventional noise compendium of standard library cells characterized by constant minimum capacitive load by providing load adaptive noise margin testing of circuit designs. In one or more embodiments, a load adaptive noise rule is generated by generating a noise margin data curve (or noise rejection curve) that more completely covers the range of possible capacitive loads that a given cell of a circuit design can drive. In a gate level shutdown (GLSO) process of noise on function (NIOF) testing, in one approach, linear interpolation can be performed to predict or select the required noise margin data curve for the actual capacitive load encountered by a cell in a circuit design. In one or more embodiments, the load adaptive noise margin testing disclosed herein transforms the conventional static noise margin testing approach into a quasi-dynamic approach and demonstrates its superiority over the default pessimistic noise rules currently used. The load adaptive noise margin testing disclosed herein not only reduces or minimizes false noise violations, but also saves a significant amount of resources by minimizing the effort to repair noise violations that belong to false violations. Overall, it improves the productivity of the circuit design flow.

[0097] Most industries use Complementary Current Source Model (CCS-Model) based rules as standard cell libraries of point library specifications. Although these CCS rules provide a better driver model, they do not specify a mechanism for noise rejection curve or noise margin. Traditionally, the circuit design industry relies on CCS dot-lib rules to determine the noise on function testing, thus adopting the most pessimistic capacitive load analysis approach. A method of adjusting the noise margin data curve (or noise rejection curve) to adapt or select the curve for the specified driving capacitive load is disclosed herein. By doing so, some of the typical pessimism inherent in conventional noise on function testing is avoided, thus reducing the number of false noise violation indications during testing.

[0098] In one or more embodiments, a noise margin data set for a logic cell used in a circuit design is obtained by characterizing the logic cell, for example, at two or more different capacitive loads and storing the resulting noise margin data curve as part of one or more noise compendium of the standard library cell. As Figure 4 and Figure 5As shown, the noise summary at the input of the logic cell can have multiple noise margin data curves 401 (i.e., noise rejection curves), each curve characterizing different capacitive load conditions on the cell. Figure 4 An expanded example of the chart is shown in Figure 5 shown in which the noise margin of the voltage is plotted against the noise pulse width in picoseconds for different effective capacitive loads (e.g., ylfF... y4fF) at the output of the cell. For example, the multiple noise rejection curves or noise margin data curves include multiple curves for different effective capacitive loads from low load to high load, the effective capacitance being y4fF. In this case, the noise margin or amount of noise slack obtained by considering noise margin data curves other than the minimum noise margin data curve is about 0.2 volts in the graph, from 0.4 volts to 0.6 volts, depending on the effective capacitive load. As is known, the noise margin refers to the amount of noise that the logic cell can tolerate before a noise violation occurs. The greater the noise pulse width, the lower the noise margin. In this way, the digital logic cell (or gate) is characterized to have different noise margin levels depending on the capacitive load of the output pin of the gate, where the capacitive load for each output gate is determined independently to more effectively cover the expected range of actual circuit loads using, for example, a minimum number of noise margin data curves. In this way, load adaptive noise margin testing is facilitated to improve the accuracy of functional noise analysis while reducing pessimism in the tool to improve circuit design and speed up design closure and acceptance.

[0099] Figure 6One embodiment of a process to characterize a noise margin dataset for a logic cell of a circuit design is shown in accordance with one or more embodiments of the present disclosure. As shown, for each logic cell (or gate) 600 in a standard cell library, several output capacitance loads are identified for the logic cell 602. A variety of methods can be used to identify representative capacitance loads for a logic cell. As an example embodiment, the process can include determining a noise margin data curve with the smallest effective capacitance load (e.g., save 100 ps amplitude (i.e., amplitude of 100 ps pulse width)), and determining a noise margin data curve at the maximum capacitance load condition (e.g., save 100 ps amplitude). By way of example, the process identifies a number of desired data curves, and identifies (in one embodiment) an ideal amplitude for each data curve at the 100 ps point. For example, in one or more embodiments, x number of noise margin data curves (or noise suppression curves) can be selected whose 100 ps amplitude measurements average divide the range between the observed minimum and maximum amplitudes. For example, in one embodiment, x can be a relatively low number, such as 2-5 in one embodiment. For each desired data curve amplitude, the process can include increasing the effective capacitance load from the previous data curve load (e.g., minimum data curve load) until the 100 ps amplitude of the new data curve approaches the desired amplitude.

[0100] As Figure 6 shown, for each output capacitance load 604, a noise margin data curve 606 is determined for each input on the logic cell, and the resulting noise margin data curves (i.e., noise suppression curves) and associated load assumptions are stored on the input pins of the noise summary for use in noise impact 608 on functional testing.

[0101] Those skilled in the art will note that there are a number of ways in which the Figure 6processing, to identify, for example, the best minimum and / or maximum effective capacitance load of a scan, the number of curves stored, etc. For example, in one approach, the processing can include finding instances of logic cells in a large sample of random logic macros of a circuit design and drawing a histogram of the load distribution for each cell type. Using the histogram, the first and third quartiles can be selected as two load points in addition to the minimum load driven by the core. Thus, for example, three capacitance load samples are obtained, namely the minimum effective load, the Ql load, and the Q3 load. Then, a noise margin data curve can be generated for each of these three load conditions. In a gate level signature (GLSO) processing of noise on function (NIOF) tests, the processing can determine the actual load being driven by a given instance of a logic cell and then select from the plurality of noise margin data curves the noise margin data curve corresponding to the maximum characterized capacitance load that is lower than the actual capacitance load of the logic cell instance. In this way, the pessimism in the noise margin analysis is reduced compared to the approach using the worst case capacitance load, and the test results are closer to the actual noise immunity of the circuit. In one example, the capacitance load for a given node can also be identified adaptively based on the random logic macro (RLM) routing of the previous node, since the load distribution does not change significantly from one processing to another.

[0102] In another example embodiment, the theoretically maximum and minimum capacitance loads that a logic cell can drive are determined, as well as the noise margin data curves for the best and worst case scenarios based on these loads. Noise margin data curves are identified for the maximum and minimum capacitance loads, and then x (e.g., x is between 2 and 5) additional data curves are generated between the minimum and maximum curves, in one example, the curves are generated equidistantly. The processing can search for a capacitance load using a binary search method corresponding to these curves. In this way, closely spaced noise margin data curves can be provided with a desired accuracy. Based on the analysis, for example, at a 5 nanometer node, it has been found that 5 such curves provide sufficient accuracy to significantly reduce false noise violations. The advantage of this flow is that it is fully adaptive and does not rely on previously generated load data, thus allowing the entire flow to be automated.

[0103] Figure 7One embodiment of a process for partial noise impact processing of functional testing of logic cell instances of a circuit design using noise margin data sets is shown in accordance with one or more embodiments of the present disclosure. The process includes identifying a logic cell (e.g., network) for analysis 700, and determining the load capacitance on the output pin of the cell 702, e.g., determining or calculating the load capacitance of the output pin of the sink. The process includes determining or calculating the noise pulse received or impinging on an input pin (or sink pin) of the logic cell 704, and selecting the appropriate noise margin data curve stored for that input pin based on the determined load capacitance 706. Selecting the appropriate noise margin data curve or noise suppression curve can be accomplished in a number of ways. For example, the best noise margin data curve (i.e., the highest associated load capacitance below the actual logic cell load capacitance) can be selected. In another approach, the noise margin data curves above and below the observed or determined logic cell load can be selected, and an interpolated noise margin data curve constructed for the observed load on the logic cell instance.

[0104] Other variations are possible. For example, the different potential capacitance loads on the logic cell can include a plurality of fixed sink capacitance loads of the logic cell. In another embodiment, the different potential capacitance loads on the logic cell can be based on historical capacitance loads on logic cell instances in one or more circuit designs (e.g., one or more other circuit designs). In another embodiment, the different potential capacitance loads on the logic cell can be selected to achieve a spaced apart noise margin data curve between a noise margin data curve for a selected or determined minimum capacitance load condition on the logic cell and a noise margin data curve for a selected or determined maximum capacitance load condition on the logic cell of the circuit design. In another embodiment, at least one of the plurality of noise margin data curves for the logic cell of the circuit design can be for a given capacitance load on the logic cell, and the data curves can be interpolated between the pre-characterized noise margin data curves having specified load capacitances on the logic cell, where the given capacitance load is between the specified capacitance loads.

[0105] In one or more embodiments, another step includes fabricating a physical integrated circuit from the circuit design, as described herein. One non-limiting specific example of implementing this is described herein in connection with Figures 8-10 For example, the circuit design or circuit design structure is provided to a manufacturing device, such as a semiconductor fabrication facility, to facilitate fabrication of a physical integrated circuit from the design structure.

[0106] In one or more embodiments, the layout is prepared based on the analysis. In one or more embodiments, the layout is instantiated as a design structure. In one or more embodiments, a physical integrated circuit is fabricated from the design structure.

[0107] As described above, in one or more embodiments, the layout is instantiated as a design structure. The physical integrated circuit is then manufactured from the design structure. The design process will also be discussed with reference to Figures 8-10 . Figure 8 is a flow diagram of a design process used in semiconductor design, manufacture, and / or test. Once physical design data is obtained, in some embodiments, the integrated circuits are fabricated, in accordance with the design process described herein, using the design data. The design process is described with reference to Figure 8 known processes described with reference to Figures 8-10 In block 810, the process includes manufacturing masks for photolithography based on the finalized physical layout. In block 820, the process of manufacturing the wafer includes photolithography and etching using the masks. Once the wafer is diced, in 830, each chip is tested and sorted to filter out any defective chips. Further, with reference to

[0108] Figure 9An example of a high-level electronic design automation (EDA) tool flow is described that is responsible for creating an optimized microprocessor (or other IC) design to be manufactured. A designer can start with a high-level logical description of a circuit 901 (e.g., VHDL or Verilog). A logic synthesis tool 903 compiles the logic and optimizes the logic without any feeling for its physical representation and with estimated timing information. A placement tool 905 takes the logical description and places each component to minimize congestion in each region of the design. A clock synthesis tool 907 optimizes the clock tree network by cloning / balancing / caching latches or registers. A timing closure step 909 performs a number of optimizations on the design, including buffers, wire adjustments, and circuit repowering; its goal is to produce a routable design that does not violate timing specifications and does not consume excessive real estate. A routing stage 911 takes the placed / optimized design and determines how to create the wiring that connects the components without causing manufacturing violations. A post-route timing closure 913 performs another set of optimizations to resolve any violations that remain after routing. A design wrap-up 915 then adds additional metal shapes to the netlist to comply with manufacturing requirements. A check step 917 analyzes whether the design violates any requirements, such as manufacturing, timing, real estate, electromigration, or noise. When the design is clean, the final step 919 is to generate a layout of the design, representing all the shapes 921 to be manufactured in the design to be manufactured.

[0109] One or more embodiments incorporate the timing analysis techniques herein with semiconductor integrated circuit design simulation, testing, layout, and / or manufacturing. In this regard, Figure 10 A block diagram illustrates an example design flow 1000, such as for a semiconductor IC logic design, simulation, testing, layout, and manufacturing. The design flow 1000 includes processes, machines and / or mechanisms for processing design structures or devices to generate design structures representing a logic or functional equivalent of a hardware component, electrical circuit, device or system. The design structures processed and / or generated by the design flow 1000 can be encoded on machine-readable media to include data and / or instructions that when executed or otherwise processed on a data processing system generate a functional description of hardware behavior or a structural design, circuit design, device design, or system design. Machines include, but are not limited to, any machine used in the design, simulation, testing, fabrication, or manufacturing of a circuit, component, device, or system, such as design or simulation tools, e.g., design tools 1030-1050, and / or any machines for reading the designs specified or generated by the design flow 1000, including machines for reading the artwork, masks, or reticles used in fabricating or testing a circuit, component, device, or system. For example, a machine might include a machine for generating masks or reticles, e.g., an e-beam writer, a machine for reading the design that is recorded on media, e.g., a disc, or a machine for programming a programmable gate array with the functional description of the hardware design.

[0110] The design process 1000 can vary depending on the type of representation being made. For example, a design process 1000 for building an application specific integrated circuit (ASIC) can differ from a design process 1000 for designing a standard component or from a design process 1000 for

[0111] Figure 10 A number of such design structures 1020 are shown in Fig. 10, which are generated by the design process 1010. Design structure 1020 can be a logical simulation design structure generated and processed by design process 1010 to produce a functional representation of a hardware device. Design structure 1020 can also or alternatively comprise data and / or program instructions capable of being generated and processed by the design process 1010 to generate a functional representation of the hardware device. Whether representing functional and / or structural design representation, design structure 1020 can be generated using electronic computer-aided design (ECAD) such as implemented by a core developer / designer. When encoded on a machine-readable data structure, design structure 1020 can be accessed and processed by one or more hardware and / or software modules within design process 1010 to simulate or otherwise functionally represent hardware component, circuit, electronic or logic module, apparatus, device, or system. As such, design structure 1020 can comprise files or other data structures including human and / or machine-readable source code, compiled structures, and computer- executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures can include hardware-description language (HDL) design entities or other data structures conforming to and / or compatible with lower-level HDL design languages such as Verilog and VHDL, and / or higher level design languages such as C or C++.

[0112] Design process 1010 preferably employs and incorporates hardware and / or software modules for synthesizing, translating, or otherwise processing a design / simulation functional equivalent of the components, circuits, devices, or logic structures shown in design structure 1020. Design structure 1020 can be synthesized using a variety of technologies to generate a netlist 1080 which can include design structures such as design structure 1020. Netlist 1080 can include a compiled or otherwise processed data structure representing a list of wires, discrete components, logic gates, control circuits, I / O devices, models, etc. that are to be used to fabricate or otherwise implement a design of an integrated circuit as represented by design structure 1020. Netlist 1080 can be generated from design structure 1020 (i.e., actual design implementation) or otherwise, starting with a pre- processed design structure containing a description of the design as set forth by a designer or design

[0113] The design process 1010 can include hardware and software modules for processing various input data structure types, including a netlist 1080. Such data structure types can reside, for example, within library elements 1030 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (for example, different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure type(s) can further include design specifications 1040, characterization data 1050, verification data 1060, design rules 1070, and test data files 1085 which can include input test patterns, expected output results, and other testing information. Design process 1010 can further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and

[0114] Design process 1010 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 1020 along with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 1090. Design structure 1090 resides on storage medium or programmable gate array in a data format used for the exchange of data of storage media (for example, information stored in IGES, DXF, Paridex, XT, JT, DRG, or any other format utilized by the manufacturing company). Similar to design structure 1020, design structure 1090 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on storage media and that, when executed by an ECAD system, generate a logically or otherwise functionally equivalent form of the components, modules, instaictions for an implementation of a hardware device. In one embodiment, the design structure 1090 can comprise a compiled, executable HDL simulation model that functionally simulates the devices being

[0115] Design structure 1090 can also employ a data format used for the exchange of layout data of integrated circuits and / or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 1090 can comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, shapes, polygons, test data, etc. Design structure 1090 can also comprise any other suitable data in any other suitable format that facilitates instructing manufacturing devices to manufacture a structure as described herein. Design structure 1090 can then proceed to a stage 1095 where, for example, design structure 1090: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

[0116] The computing environment described herein is merely an example of a computing environment that can be used. One or more embodiments of the present disclosure can be used in a variety of types of environments. The computing environment provided herein is merely an example. Each computing environment can be configured to include one or more aspects of the present disclosure.

[0117] Other aspects, variations and / or embodiments are also possible.

[0118] In accordance with the foregoing, one or more embodiments can be provided, offered, deployed, managed, serviced, etc. A service provider provides management of a customer's environment. For example, a service provider can create, maintain, support, etc. Computer code and / or computer infrastructure for one or more embodiments are executed for one or more customers. In return, the service provider can receive payment from the customer, for example, under a subscription and / or fee agreement. Additionally or alternatively, the service provider can receive payment from the sale of advertising content to one or more third parties.

[0119] In one embodiment, an application can be deployed for executing one or more embodiments. As one example, deployment of an application includes providing computer infrastructure operable when executing and / or configuring to execute one or more embodiments.

[0120] As a further embodiment, a computing infrastructure can be deployed comprising integrating computer readable code on a computer infrastructure for executing the code. A specific

[0121] In yet a further embodiment, a process can be provided for integrating a computing infrastructure, including integrating computer readable code on a computer infrastructure for executing the code. The computer infrastructure can comprise, among other things, a computer readable medium storing the computer readable code. The code in combination with the computer system can cause performing one or more embodiments.

[0122] While various embodiments have been described above, these are only examples. For example, other memory access instructions can be used. Also, other predictors can be used, including but not limited to other examples of counter tables and / or global counters. Many variations are possible.

[0123] Various aspects and embodiments are described herein. Moreover, many changes can be made to the disclosure without departing from the spirit thereof. It is to be noted that, unless otherwise indicated herein, each of the aspects and features described herein, and / or the variants thereof, are combinable with any other aspect or feature, or combination of aspects or features.

[0124] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" (and any

[0125] All means or steps plus any claim elements for performing the functions recited by that means or step are intended to be encompassed by the corresponding structural, material, acts, or equivalents (if any) for performing the functions recited by that means or step. The description of one or more embodiments is presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others skilled in the art to understand various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A computer-implemented method for facilitating circuit design processes within a computing environment, the computer-implemented method comprising: Obtain multiple noise margin data curves for different potential capacitive loads on logic units in the circuit design; The noise impact of performing functional tests on instances of the logic units within the circuit design, the performance including: The noise margin data curve is selected from the plurality of noise margin data curves based on the capacitive load on the logic unit instance of the circuit design; and Whether a logic cell instance fails the noise impact test is determined by comparing the noise pulse at the logic cell instance during the noise impact test with a selected noise tolerance data curve; and The logic unit instance based on the circuit design fails to initiate one or more actions due to the noise impact on the functional test, in order to resolve the failure of the logic unit instance during the noise impact on the functional test.

2. The computer-implemented method of claim 1, wherein the different potential capacitive loads for the logic unit include a plurality of fixed capacitive loads for the logic unit.

3. The computer-implemented method of claim 1, wherein the different potential capacitive loads for the logic unit are based on historical capacitive loads on one or more instances of the logic unit within one or more other circuit designs.

4. The computer-implemented method of claim 1, wherein the different potential capacitive loads for the logic unit are selected to achieve spaced noise margin data curves between the noise margin data curve for the selected minimum capacitive load condition for the logic unit and the noise margin data curve for the selected maximum capacitive load condition for the logic unit for the circuit design.

5. The computer-implemented method of claim 1, wherein at least one of the plurality of noise tolerance data curves is used for a given capacitive load on the logic unit, and is an interpolated data curve between noise tolerance data curves representing a specified capacitive load on the logic unit, the given capacitive load being located between the specified capacitive loads.

6. The computer-implemented method of claim 1, wherein the execution further includes determining the capacitive load on the logic unit instance as a sink load capacitor on the output pin of the logic unit instance.

7. The computer-implemented method of claim 6, wherein selecting the noise margin data curve from the plurality of noise margin data curves based on the capacitive load on the logic unit comprises: The noise tolerance data curve is selected based on the assumed capacitive load on the output pin of the logic unit instance that is closest to and lower than the determined sink load capacitance.

8. The computer-implemented method of claim 6, wherein the selection includes generating a noise tolerance data curve for the capacitive load on the logic unit instance, the generation including referencing one or more noise tolerance data curves for one or more capacitive loads closest to the capacitive load among the plurality of noise tolerance data curves, and generating another noise tolerance data curve for the capacitive load on the logic unit instance by interpolation, wherein the other noise tolerance data curve is the selected noise tolerance data curve for determining whether the logic unit instance of the circuit design has passed the noise impact of functional testing.

9. The computer-implemented method of claim 1, wherein the acquisition includes referencing a cell library file for the logic unit during the noise impact of a functional test of the logic unit instance to select the noise tolerance data curve from the plurality of noise tolerance data curves.

10. A computer program product for facilitating circuit design processes within a computing environment, the computer program product comprising: A group or more computer-readable storage media; as well as Program instructions, which are collectively stored in the one or more computer-readable storage media, are used to cause at least one processor group to perform computer operations, the computer operations including: Obtain multiple noise margin data curves for different potential capacitive loads on logic units in the circuit design; The noise impact of performing functional tests on instances of the logic units within the circuit design, the performance including: The noise margin data curve is selected from the plurality of noise margin data curves based on the capacitive load on the logic unit instance of the circuit design; and Whether a logic cell instance fails the noise impact test is determined by comparing the noise pulse at the logic cell instance during the noise impact test with a selected noise tolerance data curve; and The logic unit instance based on the circuit design fails to initiate one or more actions due to the noise impact on the functional test, in order to resolve the failure of the logic unit instance during the noise impact on the functional test.

11. The computer program product of claim 10, wherein the different potential capacitive loads for the logic unit include a plurality of fixed capacitive loads for the logic unit.

12. The computer program product of claim 10, wherein the different potential capacitive loads for the logic unit are based on historical capacitive loads on one or more instances of the logic unit within one or more other circuit designs.

13. The computer program product of claim 10, wherein the different potential capacitive loads for the logic unit are selected to achieve spaced noise margin data curves between the noise margin data curve for the selected minimum capacitive load condition for the logic unit and the noise margin data curve for the selected maximum capacitive load condition for the logic unit for the circuit design.

14. The computer program product of claim 10, wherein at least one of the plurality of noise tolerance data curves is used for a given capacitive load on the logic unit, and is an interpolation data curve between noise tolerance data curves representing a specified capacitive load on the logic unit, the given capacitive load being located between the specified capacitive loads.

15. The computer program product of claim 10, wherein the execution further comprises determining the capacitive load on the logic unit instance as a sink capacitance on an output pin of the logic unit instance, and selecting the noise margin curve among the plurality of noise margin curves for the capacitive load on the logic unit includes: The noise tolerance data curve is selected based on the assumed capacitive load on the output pin of the logic unit instance that is closest to and lower than the determined sink load capacitance.

16. The computer program product of claim 10, wherein the execution further comprises determining the capacitive load on the logic unit instance as a sink capacitance on an output pin of the logic unit instance, and wherein the selection comprises generating a noise tolerance data curve for the capacitive load on the logic unit instance, the generation comprising generating another noise tolerance data curve for the capacitive load on the logic unit instance by interpolation, referencing one or more noise tolerance data curves for one or more capacitive loads closest to the capacitive load among the plurality of noise tolerance data curves, wherein the other noise tolerance data curve is the selected noise tolerance data curve for determining whether the logic unit instance of the circuit design has passed the noise impact of functional testing.

17. A computer system for facilitating circuit design processes within a computing environment, the computer system comprising: At least one processor group; A group or more computer-readable storage media; as well as Program instructions, which are collectively stored in the one or more computer-readable storage media, are used to cause the at least one processor group to perform computer operations, the computer operations including: Obtain multiple noise margin data curves for different potential capacitive loads on logic units in the circuit design; The noise impact of performing functional tests on instances of the logic units within the circuit design, the performance including: The noise margin data curve is selected from the plurality of noise margin data curves based on the capacitive load on the logic unit instance of the circuit design; and Whether a logic cell instance fails the noise impact test is determined by comparing the noise pulse at the logic cell instance during the noise impact test with a selected noise tolerance data curve; and The logic unit instance based on the circuit design fails to initiate one or more actions due to the noise impact on the functional test, in order to resolve the failure of the logic unit instance during the noise impact on the functional test.

18. The computer system of claim 17, wherein the execution further includes determining the capacitive load on the logic unit instance as a sink load capacitor on an output pin of the logic unit instance.

19. The computer system of claim 18, wherein selecting the noise margin data curve from the plurality of noise margin data curves based on the capacitive load on the logic unit comprises: The noise tolerance data curve is selected based on the assumed capacitive load on the output pin of the logic unit instance that is closest to and lower than the determined sink load capacitance.

20. The computer system of claim 18, wherein the selection includes generating a noise tolerance data curve for the capacitive load on the logic unit instance, the generation including referencing one or more noise tolerance data curves for one or more capacitive loads closest to the capacitive load among the plurality of noise tolerance data curves, and generating another noise tolerance data curve for the capacitive load on the logic unit instance by interpolation, wherein the other noise tolerance data curve is the selected noise tolerance data curve for determining whether the logic unit instance of the circuit design has passed the noise impact of functional testing.

Images