Switching technique for supply-side harmonic tuning in voltage controlled oscillators (VCOs)

Abstract

Certain aspects of the present disclosure relate to techniques and apparatus for oscillating signal generation. An example apparatus generally includes a VCO and a first filter coupled to the VCO, where the first filter includes: a first inductive element including a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; a first capacitor bank coupled between the second terminal of the first inductive element and a reference potential node; and a bypass capacitive element coupled between the first terminal of the first inductive element and the reference potential node.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 591,195, filed February 29, 2024, which is incorporated herein by reference. Technical Field

[0002] Certain aspects of this disclosure relate generally to electronic circuits, and more specifically, to techniques for harmonic tuning of voltage-controlled oscillators (VCOs). Background Technology

[0003] Wireless communication devices are widely deployed to provide a variety of communication services, such as telephone, video, data, messaging, broadcasting, and so on. These wireless communication devices can transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), LTE, CDMA, TDMA, WCDMA, GSM, GSM, Bluetooth, Bluetooth Low Energy (BLE), ZigBee, WLAN RATs (e.g., WiFi), etc.

[0004] A wireless communication network may include multiple base stations capable of supporting communication with multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via downlink and uplink. A downlink (or forward link) is the communication link from the base station to the mobile station, while an uplink (or reverse link) is the communication link from the mobile station to the base station. The base station may transmit data and control information to the mobile station on the downlink and / or receive data and control information from the mobile station on the uplink. The base station and / or mobile station may include one or more frequency synthesizers implemented using a voltage-controlled oscillator (VCO). Summary of the Invention

[0005] The systems, methods, and apparatus of this disclosure each have several aspects, none of which is solely responsible for their desired properties. Without limiting the scope of this disclosure as set forth in the following claims, some features will now be briefly discussed. Upon consideration of this discussion, and especially after reading the section entitled “Detailed Description,” it will be understood how the features of this disclosure provide the advantage of an increased filter quality factor, including a voltage-controlled oscillator (VCO).

[0006] Some aspects of this disclosure relate to an apparatus for generating an oscillation signal. The apparatus generally includes a voltage control unit (VCO) and a first filter coupled to the VCO, wherein the first filter includes: a first inductor element having a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; a first capacitor bank coupled between the second terminal of the first inductor element and a reference potential node; and a bypass capacitor element coupled between the first terminal of the first inductor element and the reference potential node.

[0007] Certain aspects of this disclosure relate to a method for generating an oscillating signal. The method generally includes: configuring a first capacitor bank of a first filter based on the oscillation frequency of a VCO, wherein at least a portion of the first filter is coupled between a voltage rail and the VCO, the first filter comprising: a first inductor element including a first terminal coupled to the voltage rail and a second terminal coupled to the VCO, wherein the first capacitor bank is coupled between the second terminal of the first inductor element and a reference potential node; and a bypass capacitor element coupled between the first terminal of the first inductor element and the reference potential node. The method may further include generating an oscillating signal having an oscillation frequency via the VCO.

[0008] Certain aspects of this disclosure relate to a wireless device. The wireless device generally includes: one or more antennas; a transmitter or receiver coupled to the one or more antennas and including a frequency synthesizer, wherein the frequency synthesizer includes a VCO; and a filter coupled to the VCO, wherein the filter includes: an inductor including a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; a capacitor bank coupled between the second terminal and a reference potential node; and a bypass capacitor element coupled between the first terminal of the inductor and the reference potential node.

[0009] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate some exemplary features of one or more aspects in detail. However, these features indicate only some of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, which has been briefly summarized above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not to be construed as limiting its scope, as other equally valid aspects may be acknowledged in this description.

[0011] Figure 1 This is a diagram illustrating an example wireless communication network in which various aspects of the present disclosure can be practiced.

[0012] Figure 2 It is a block diagram conceptually illustrating the design of an example base station (BS) and user equipment (UE) in which various aspects of this disclosure can be practiced.

[0013] Figure 3 This is a block diagram of an example radio frequency (RF) transceiver in which various aspects of this disclosure can be practiced.

[0014] Figure 4 An example oscillating circuit including a voltage-controlled oscillator (VCO) is illustrated according to certain aspects of this disclosure.

[0015] Figure 5 Example embodiments of filters for VCOs according to certain aspects of this disclosure are illustrated.

[0016] Figure 6 This is a flowchart illustrating example operations for generating oscillating signals according to certain aspects of this disclosure.

[0017] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the figures. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0018] Some aspects of this disclosure relate to a filter for a voltage-controlled oscillator (VCO). The filter may include a capacitor bank comprising capacitive elements selectively coupled in parallel using appropriate switches. The filter may be a supply-side filter for the VCO and is configured to use one or more n-type metal-oxide-semiconductor (NMOS) transistors to implement the switching for the capacitor bank. Using NMOS transistors increases the quality factor (Q) of the filter compared to implementations using p-type metal-oxide-semiconductor (PMOS) transistors for the supply-side filter.

[0019] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of protection of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of this disclosure is intended to cover any aspect of the disclosure herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functions, or structures and functions other than or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of this disclosure herein may be embodied by one or more elements of these claims.

[0020] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0021] As used in this article, the term "connected with" in various tenses of the verb "connect" can refer to an element. A Directly connected to the component B Or other components can be connected to the component. A With components B Between (i.e., elements) A With components B Indirect connection). In the context of electronic components, the term "connected to..." may also be used herein to refer to leads, traces, or other conductive materials used to connect components. A and components B Electrical connections (and any components that are electrically connected between them).

[0022] Example wireless system Figure 1Example wireless communication network 100 is illustrated in which various aspects of this disclosure can be practiced. For example, wireless communication network 100 may be a new radio (NR) system (e.g., a fifth-generation (5G) NR network), an evolved universal terrestrial radio access (E-UTRA) system (e.g., a fourth-generation (4G) network), a universal mobile telecommunications system (UMTS) (e.g., a second-generation / third-generation (2G / 3G) network), or a code division multiple access (CDMA) system (e.g., a 2G / 3G network), or may be configured to communicate according to IEEE standards such as one or more standards in the 802.11 standard.

[0023] like Figure 1 As illustrated, the wireless communication network 100 may include multiple base stations (BS) 110a to 110z (each individually referred to herein as BS 110 or collectively as BS 110) and other network entities. BS may also be referred to as access point (AP), evolved Node B (eNodeB or eNB), next-generation Node B (gNodeB or gNB), or some other terminology.

[0024] BS 110 can provide communication coverage for a specific geographic area (sometimes referred to as a "cell"), which can be stationary or mobile depending on the location of the mobile BS. In some examples, BS 110 can use any suitable transport network, interconnected with each other through various types of backhaul interfaces (e.g., direct physical connection, wireless connection, virtual network, etc.) and / or connected to one or more other BSs or network nodes (not shown) in the wireless communication network 100. Figure 1 In the example shown, BS 110a, 110b, and 110c can be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x can be a pico BS for pico cell 102x. BS 110y and 110z can be femto BSs for femto cells 102y and 102z, respectively. A BS can support one or more cells.

[0025] In the wireless communication network 100, BS 110 communicates with one or more user equipment (UEs) 120a to 120y (each of which may also be individually referred to as "UE 120" or collectively as "UE 120" herein). UEs may be fixed or mobile, and may also be referred to as user terminals (UTs), mobile stations (MSs), access terminals, stations (STAs), clients, wireless devices, mobile devices, or other terms. User terminals may be wireless devices such as cellular phones, smartphones, personal digital assistants (PDAs), handheld devices, wearable devices, wireless modems, laptop computers, tablet computers, personal computers, etc.

[0026] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a “transmitting entity” is a separately operating apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is a separately operating apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “…” dn " indicates the downlink, subscript " up "Indicates uplink. You can select..." N up Each UE is used for simultaneous transmission on the uplink, and can be selected. N dn Each UE is used for simultaneous transmission on the downlink. N up It can be equal to or not equal to N dn ,and N up and N dn It can be a static value or it can be changed for each scheduling interval. Beam control or some other spatial processing techniques can be used at BS 110 and UE 120.

[0027] UEs 120 (e.g., 120x, 120y, etc.) may be distributed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include relay stations (e.g., relay station 110r) (also referred to as repeaters, etc.) that receive data transmissions and / or other information transmissions from upstream stations (e.g., BS 110a or UE 120r) and transmit the data transmissions and / or other information transmissions to downstream stations (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between devices.

[0028] BS 110 can communicate with one or more UE 120s on both the downlink and uplink at any given time. The downlink (i.e., the forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., the reverse link) is the communication link from UE 120 to BS 110. UE 120 can also communicate peer-to-peer with another UE 120.

[0029] Wireless communication network 100 can use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. BS 110 can be equipped with several ( N ap(Number) antennas to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A set of ( N u Each UE 120 can receive downlink transmissions and send uplink transmissions. Each UE 120 can send user-specific data to and / or receive user-specific data from the BS 110. Typically, each UE 120 may be equipped with one or more antennas. N u Each UE 120 can have the same or different number of antennas.

[0030] The wireless communication network 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each UE 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional cost can be supported).

[0031] Network controller 130 (sometimes referred to as a "system controller") can communicate with a group of BSs 110 and (e.g., via backhaul) provide coordination and control for these BSs 110. In some cases (e.g., in a 5G NR system), network controller 130 may include centralized units (CUs) and / or distributed units (DUs). In some aspects, network controller 130 can communicate with core network 132 (e.g., a 5G core network (5GC)) that provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network openness functions, network repository functions, network slice selection functions, etc.

[0032] In certain aspects of this disclosure, BS 110 and / or UE 120 may include a frequency synthesizer implemented using a power supply side filter of at least one n-type metal-oxide-semiconductor (NMOS) transistor with a voltage-controlled oscillator (VCO).

[0033] Figure 2 Examples of BS 110a and UE 120a in which aspects of this disclosure may be implemented (e.g., from...) Figure 1 Example components of a wireless communication network 100.

[0034] On the downlink, at BS 110a, the transmitting processor 220 can receive data from data source 212, control information from controller / processor 240, and / or other data (e.g., from scheduler 244). Various types of data can be transmitted on different transport channels. For example, control information can be designated for the Physical Broadcast Channel (PBCH), Physical Control Format Indicator Channel (PCFICH), Physical Hybrid Automatic Repeat Request (HARQ) Indicator Channel (PHICH), Physical Downlink Control Channel (PDCCH), Group Common PDCCH (GC PDCCH), etc. Data can be designated for the Physical Downlink Shared Channel (PDSCH), etc. The Media Access Control (MAC)-Control Element (MAC-CE) is a MAC layer communication structure that can be used for exchanging control commands between wireless nodes. The MAC-CE can be carried in shared channels such as PDSCH, Physical Uplink Shared Channel (PUSCH), or Physical Sidelink Shared Channel (PSSCH).

[0035] Processor 220 can process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. Transmitter processor 220 can also generate reference symbols such as those for primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0036] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 can perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and can provide the output symbol stream to the modulators (MODs) in transceivers 232a to 232t. Each modulator in transceivers 232a to 232t can process its own output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each transceiver in transceivers 232a to 232t can further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signal from transceivers 232a to 232t can be transmitted via antennas 234a to 234t, respectively.

[0037] At UE 120a, antennas 252a to 252r can receive downlink signals from BS 110a and can provide the received signals to transceivers 254a to 254r respectively. Transceivers 254a to 254r can adjust (e.g., filter, amplify, down-convert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a to 232t can further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 can obtain the received symbols from all demodulators in transceivers 254a to 254r, perform MIMO detection on the received symbols where applicable, and provide the detected symbols. Receiver processor 258 can process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide the decoded data for UE 120a to data sink 260, and provide the decoded control information to controller / processor 280.

[0038] On the uplink, at UE 120a, the transmit processor 264 can receive and process data from data source 262 (e.g., for the Physical Uplink Shared Channel (PUSCH)) and control information from controller / processor 280 (e.g., for the Physical Uplink Control Channel (PUCCH)). The transmit processor 264 can also generate reference symbols for reference signals (e.g., for the Sounding Reference Signal (SRS)). Symbols from the transmit processor 264 can be pre-decoded by the TX MIMO processor 266 where applicable, further processed by modulators (MODs) in transceivers 254a to 254r (e.g., for Single Carrier Frequency Division Multiplexing (SC-FDM), etc.), and transmitted to BS 110a. At BS 110a, the uplink signal from UE 120a can be received by antenna 234, processed by demodulators in transceivers 232a to 232t, detected by MIMO detector 236 where applicable, and further processed by receiver processor 238 to obtain decoded data and control information transmitted by UE 120a. Receiver processor 238 can provide the decoded data to data sink 239 and the decoded control information to controller / processor 240.

[0039] Memory 242 and 282 can store data and program code for BS 110a and UE 120a, respectively. Memory 242 and 282 can also interface with controller / processor 240 and 280, respectively. Scheduler 244 can schedule UEs for data transmission on the downlink and / or uplink.

[0040] In some aspects of this disclosure, transceiver 232 and / or transceiver 254 may include a frequency synthesizer that uses at least one NMOS transistor to implement a power supply side filter of the VCO.

[0041] NR can use Orthogonal Frequency Division Multiplexing (OFDM) with a cyclic prefix (CP) on both the uplink and downlink. NR can use Time Division Duplex (TDD) to support half-duplex operation. OFDM and Single-Carrier Frequency Division Multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are often referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, a subband can cover multiple resource blocks (RBs).

[0042] Example RF transceiver Figure 3 This is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of this disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via antenna 306. When the TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via an interface 308, which may include any of a variety of suitable RF devices, such as switches, duplexers, double-ended converters, multiplexers, etc.

[0043] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, mixer 314, DA 316, and PA 318 may be included in a radio frequency integrated circuit (RFIC). In some respects, the PA 318 may be external to the RFIC.

[0044] BBF 312 filters the baseband signal received from DAC 310, and mixer 314 mixes the filtered baseband signal with the transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). This frequency conversion process produces a sum and difference frequency between the LO frequency and the frequency of the baseband signal of interest. This sum and difference frequency is referred to as the "beat frequency". The beat frequency is typically in the RF range, such that the signal output from mixer 314 is typically an RF signal, which can be amplified by DA 316 and / or PA 318 before being transmitted by antenna 306. When one mixer 314 is exemplified, several mixers can be used to up-convert the filtered baseband signal to one or more intermediate frequencies and subsequently up-convert the intermediate frequency (IF) signal to the frequency used for transmission.

[0045] The RX path 304 may include a low-noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC including the TX path components, or may not be the same RFIC as the RFIC including the TX path components. The RF signal received via antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-conversion). The baseband signal output from the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0046] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Therefore, the transmit LO can be generated by the TX frequency synthesizer 320, which can be buffered or amplified by amplifier 322 before being mixed with the baseband signal in mixer 314. Similarly, the receive LO can be generated by the RX frequency synthesizer 332, which can be buffered or amplified by amplifier 334 before being mixed with the RF signal in mixer 326. In some aspects, a single frequency synthesizer may be used for both TX path 302 and RX path 304. In some aspects, frequency synthesizer 320 or frequency synthesizer 332 may be implemented using at least one NMOS transistor with a power supply-side filter of the VCO.

[0047] Controller 336 (e.g., Figure 2The controller / processor 280 in the controller can direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. The controller 336 can be a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the memory can store data and / or program code used to operate the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0048] although Figures 1 to 3 Wireless communication is provided as an example application in which certain aspects of this disclosure can be implemented to facilitate understanding; however, certain aspects described herein can be used in any of a variety of other suitable systems. For example, the techniques described herein for generating oscillating signals can be applied to any suitable communication system, such as a wired communication system.

[0049] Figure 4 An example oscillator circuit 400 including a VCO 401 is illustrated according to certain aspects of this disclosure. The VCO 401 can be used to implement... Figure 3 Synthesizer 320 or synthesizer 332 is described. As shown, VCO 401 may include cross-coupled p-type metal-oxide-semiconductor (PMOS) transistors 408, 410 (e.g., transconductance (gm) transistors). The sources of transistors 408, 410 are coupled to a voltage rail (Vdd). In some cases, a filter 450 may be coupled between the sources of transistors 408, 410 and Vdd for harmonic signal attenuation. For example, filter 450 may be a notch filter configured to attenuate a frequency twice the oscillation frequency of VCO 401, thereby reducing the second harmonic signal of the VCO. In some aspects, switch 454 may be coupled between Vdd and filter 450. Switch 454 may be controlled to enable or disable VCO 401 (e.g., to energize or de-energize the VCO). In some embodiments, a current source may be used instead of switch 454.

[0050] The gate of transistor 408 can be coupled to output node 416 of the VCO, and the gate of transistor 410 can be coupled to output node 414, as shown. A resonant circuit 412 (e.g., an inductor-capacitor (LC) resonant circuit) can be coupled between output nodes 414 and 416. A tuning voltage (Vtune) can be provided to the resonant circuit 412 to adjust the oscillation frequency of the VCO.

[0051] As shown in the figure, VCO 401 also includes cross-coupled n-type metal-oxide-semiconductor (NMOS) transistors 418 and 420 (e.g., transconductance (gm) transistors). The sources of transistors 418 and 420 are coupled to a reference potential node (e.g., electrically grounded). In some aspects, a filter 452 may be coupled between the sources of transistors 418 and 420 and the reference potential node for harmonic signal attenuation. For example, filter 452 may be a notch filter configured to attenuate a frequency twice the oscillation frequency of VCO 401, thereby reducing the second harmonic signal of the VCO.

[0052] Example techniques for harmonic tuning For the same dimensions, a P-type metal-oxide-semiconductor (PMOS) transistor has a higher on-resistance (R0) than an n-type metal-oxide-semiconductor (NMOS) transistor. ON In some implementations, PMOS transistors can be used to adjust the power supply side filter (e.g., regarding...). Figure 4 The capacitor bank of the filter (450) described. The higher R of the PMOS transistor. ON This may lead to a deterioration in the reduction of second harmonic noise (e.g., due to a lower quality factor (Q) of the filter). In some implementations, the voltage rail (Vdd) of the VCO can be reduced to increase reliability and / or reduce power consumption, and if the transistors are implemented as thick oxide devices, the Rd of both the PMOS and NMOS transistors used to implement the corresponding filters 450 and 452 can be further increased. ON As a result, the VCO's quality factor specifications may not be met. Certain aspects of this disclosure relate to implementations of a power-side filter (e.g., filter 450) with an NMOS transistor having a lower Ri than a PMOS transistor. ON Furthermore, the NMOS transistors used to implement filter 450 (e.g., filter 452 in some aspects) can be implemented as thin oxide devices, thereby further reducing the RL of the filter. ON And the obtained Q.

[0053] Figure 5 An example embodiment of a filter for VCO 401 according to certain aspects of this disclosure is illustrated. As shown, for the oscillation circuit 550, the filter 450 can be implemented using an inductor 506 coupled in parallel with a capacitor bank. As shown in Figure 590, the capacitor bank may include capacitor elements C1-C n (For example, n is any positive integer), each capacitive element is connected via a corresponding switch S1-S nSelectively coupled between the terminals of the capacitor bank. As used herein, a capacitor circuit may refer to one or more capacitive elements, such as capacitor elements C1 to C2. n Furthermore, a switching circuit can refer to one or more switches, such as switches S1 to S2. n The filter 450 may include an inductor 506 connected in parallel with a capacitor bank, wherein the capacitor bank includes a capacitor circuit 508 coupled to a switching circuit 504, as described.

[0054] As shown in the figure, filter 450 creates a current loop 554, which includes a capacitor bank and an inductor to achieve the frequency response of notch filter 450. Similarly, filter 452 can be implemented using an inductor 512 coupled in parallel with a capacitor bank, which includes a capacitor circuit 510 coupled to a switching circuit 514. As shown in the figure, filter 452 creates a current loop 556, which includes a capacitor bank and an inductor to achieve the frequency response of notch filter 452.

[0055] In some respects, bypass capacitor element 502 can be coupled between the voltage rail Vdd and the reference potential node, as shown in the figure. Bypass capacitor element 502 serves as a noise filter for VCO 401 by providing a low-impedance path to high-frequency noise from Vdd to the reference potential node (e.g., electrically grounded).

[0056] As described in this article, a PMOS transistor can be used to implement the switching of the switching circuit 504 of the filter 450 on the power supply side, and the R of the PMOS transistor... ON This can lead to a deterioration in the filter's quality factor. Therefore, in order to use a filter with a lower R-value compared to a PMOS transistor... ON The power supply side filter 450 can be implemented using NMOS transistors to improve the filter Q, and an oscillator circuit 552 can be used. For the oscillator circuit 552, the switching circuit 514 of the filter 452 can be implemented using a thin oxide NMOS transistor, which provides a reduced R² value compared to using a thick oxide NMOS transistor. ON This leads to an increase in Q.

[0057] In some aspects, the power supply side filter can be implemented using an inductor 506 and a capacitor bank 519, which includes a capacitor circuit 516 coupled to a switching circuit 518. The capacitor bank 519 can be coupled between the inductor 506 and a reference potential node, as shown in the figure.

[0058] Using the power supply side filter of the oscillation circuit 552, an NMOS transistor can be used to implement the switch of the switching circuit 518 for the capacitor bank. This NMOS transistor has a lower Ro than the PMOS transistor used to implement the filter 450 of the oscillation circuit 550.ON This provides a higher Q for the power supply side filter. The current loop 560 for the power supply side filter may include a bypass capacitor element 502. Furthermore, the switching of the switching circuit 518 can be implemented using a thin oxide NMOS transistor, further increasing the Q of the filter.

[0059] Because of the increased wiring distance associated with current loop 560 (e.g., compared to current loop 554 of filter 450) and the fact that bypass capacitor element 502 is part of loop 560, using oscillator circuit 552 may degrade the quality of the inductor element of the power supply side filter. However, compared to oscillator circuit 550, using thin oxide NMOS transistors increases the overall Q of the power supply side filter of oscillator circuit 552.

[0060] Figure 6 This is a flowchart illustrating an example operation 600 for generating an oscillating signal according to certain aspects of this disclosure. Operation 600 can be performed, for example, by an oscillating circuit (such as oscillating circuit 552).

[0061] At block 602, the oscillation circuit configures the first capacitor bank (e.g., capacitor bank 519) of the first filter based on the oscillation frequency of the VCO. In some aspects, the first filter may include a notch filter. At least a portion of the first filter may be coupled to a voltage rail and the VCO (e.g., Figure 5 The first filter may include a first inductor (e.g., inductor 506) having a first terminal coupled to a voltage rail and a second terminal coupled to the VCO. A first capacitor bank may be coupled between the second terminal of the first inductor and a reference potential node. The first filter may include a bypass capacitor (e.g., capacitor 502) coupled between the first terminal of the first inductor and the reference potential node. At block 604, the oscillation circuit may generate an oscillation signal having an oscillation frequency via the VCO.

[0062] In some aspects, the first capacitor bank may include one or more switches (e.g., included as part of switch circuit 518 and corresponding to switches S1 to S2). n The first capacitor bank may also include one or more capacitor elements (e.g., included as part of capacitor circuit 516 and corresponding to switches C1 to C). n Each of the one or more capacitor elements is selectively coupled between the terminals of the capacitor bank via a corresponding switch of one or more switches. In some aspects, the one or more switches include one or more NMOS transistors. The one or more NMOS transistors may include thin oxide NMOS transistors.

[0063] In some respects, the oscillation circuit can be configured with a second filter coupled between the VCO and the reference potential node based on the oscillation frequency of the VCO (e.g., Figure 5 The second capacitor bank (e.g., including capacitor circuit 510 and switching circuit 514) of the filter 452. The second filter may include a second inductor element (e.g., inductor element 512) coupled in parallel with the second capacitor bank.

[0064] In some aspects, the second capacitor bank may include one or more switches (e.g., included as part of switch circuit 514 and corresponding to switches S1 to S2). n The second capacitor bank may also include one or more capacitor elements (e.g., included as part of capacitor circuit 510 and corresponding to switches C1 to C). n Each of the one or more capacitor elements is selectively coupled between the terminals of the second capacitor bank via a corresponding switch of the one or more switches. In some aspects, the one or more switches include one or more NMOS transistors. The one or more NMOS transistors may include thin oxide NMOS transistors.

[0065] Example In addition to the various aspects described above, specific combinations of these aspects are also within the scope of this disclosure, some of which are detailed below: Aspect 1: An apparatus for generating an oscillation signal, the apparatus comprising: a voltage-controlled oscillator (VCO); and a first filter coupled to the VCO, wherein the first filter comprises: a first inductor including a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; a first capacitor bank coupled between the second terminal of the first inductor and a reference potential node; and a bypass capacitor coupled between the first terminal of the first inductor and the reference potential node.

[0066] Aspect 2: The apparatus according to aspect 1 further includes a switch or current source coupled between the voltage rail and the first terminal of the first inductive element.

[0067] Aspect 3: The apparatus according to aspect 1 or 2, wherein the first capacitor bank comprises: one or more switches; and one or more capacitor elements, each of the one or more capacitor elements being selectively coupled between terminals of the first capacitor bank via a respective switch of the one or more switches.

[0068] Aspect 4: The apparatus according to aspect 3, wherein the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

[0069] Aspect 5: The apparatus according to aspect 4, wherein the one or more NMOS transistors comprise thin oxide NMOS transistors.

[0070] Aspect 6: The apparatus according to any one of Aspects 1 to 5, wherein the first filter comprises a notch filter.

[0071] Aspect 7: The apparatus according to any one of Aspects 1 to 6, the apparatus further comprising a second filter coupled between the VCO and the reference potential node.

[0072] Aspect 8: The apparatus according to aspect 7, wherein the second filter includes a second inductor element coupled in parallel with the second capacitor bank.

[0073] Aspect 9: The apparatus according to aspect 8, wherein the second capacitor bank comprises: one or more switches; and one or more capacitor elements, each of the one or more capacitor elements being selectively coupled between terminals of the second capacitor bank via a respective switch of the one or more switches.

[0074] Aspect 10: The apparatus according to aspect 9, wherein the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

[0075] Aspect 11: The apparatus according to aspect 10, wherein the one or more NMOS transistors comprise thin oxide NMOS transistors.

[0076] Aspect 12: The apparatus according to any one of Aspects 7 to 11, wherein the second filter comprises a notch filter.

[0077] Aspect 13: The apparatus according to any one of Aspects 7 to 12, wherein the second filter is configured to attenuate a signal with a frequency twice the oscillation frequency of the VCO.

[0078] Aspect 14: The apparatus according to any one of Aspects 1 to 13, wherein the first filter is configured to attenuate a signal with a frequency twice the oscillation frequency of the VCO.

[0079] Aspect 15: A method for generating an oscillating signal, the method comprising: configuring a first capacitor bank of a first filter based on the oscillation frequency of a voltage-controlled oscillator (VCO), wherein at least a portion of the first filter is coupled between a voltage rail and the VCO, the first filter comprising: a first inductor element including a first terminal coupled to the voltage rail and a second terminal coupled to the VCO, wherein the first capacitor bank is coupled between the second terminal of the first inductor element and a reference potential node; and a bypass capacitor element coupled between the first terminal of the first inductor element and the reference potential node; and generating an oscillating signal having the oscillation frequency via the VCO.

[0080] Aspect 16: According to the method of aspect 15, the first capacitor bank includes: one or more switches; and one or more capacitor elements, each of the one or more capacitor elements being selectively coupled between terminals of the first capacitor bank via a corresponding switch of the one or more switches.

[0081] Aspect 17: According to the method of aspect 16, the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

[0082] Aspect 18: According to the method of aspect 17, the one or more NMOS transistors include thin oxide NMOS transistors.

[0083] Aspect 19: The method according to any one of Aspects 15 to 18, wherein the first filter comprises a notch filter.

[0084] Aspect 20: The method according to any one of aspects 15 to 19, the method further comprising configuring a second capacitor bank of a second filter coupled between the VCO and the reference potential node based on the oscillation frequency of the VCO.

[0085] Aspect 21: According to the method of aspect 20, the second filter includes a second inductor element coupled in parallel with the second capacitor bank.

[0086] Aspect 22: The method according to aspect 20 or 21, wherein the second capacitor bank comprises: one or more switches; and one or more capacitor elements, each of the one or more capacitor elements being selectively coupled between terminals of the second capacitor bank via a respective switch of the one or more switches.

[0087] Aspect 23: According to the method of aspect 22, the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

[0088] Aspect 24: According to the method of aspect 23, the one or more NMOS transistors include thin oxide NMOS transistors.

[0089] Aspect 25: The method according to any one of aspects 20 to 24, wherein the second filter comprises a notch filter.

[0090] Aspect 26: A wireless device comprising: one or more antennas; a transmitter or receiver coupled to the one or more antennas and including a frequency synthesizer, wherein the frequency synthesizer includes a voltage-controlled oscillator (VCO); and a filter coupled to the VCO, wherein the filter includes: an inductor including a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; a capacitor bank coupled between the second terminal and a reference potential node; and a bypass capacitor coupled between the first terminal of the inductor and the reference potential node.

[0091] The above description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be omitted, substituted, or added as appropriate in various examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Moreover, the scope of this disclosure is intended to cover such apparatus or methods practiced using structures, functionalities, or structures and functionalities other than or different from the various aspects of this disclosure set forth herein. It should be understood that any aspect of this disclosure may be embodied by one or more elements of these claims.

[0092] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the accompanying drawings, these operations can have corresponding components plus functional elements.

[0093] As used in this article, the phrase "at least one of" in a list of items refers to any combination of these items, including a single member. For example, " a , b or c "At least one of" is intended to cover: a , b , c , ab , ac , bc and abc and any combination having multiple identical elements (e.g., a - a , a - a - a , a - a - b , a - a - c , a - b - b , a - c - c , b - b , b - b - b , b - b - c , c - c and c - c - c or a , b and c (any other sorting).

[0094] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0095] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An apparatus for generating an oscillation signal, the apparatus comprising: Voltage-controlled oscillator (VCO); and A first filter, coupled to the VCO, wherein the first filter comprises: A first inductor element, the first inductor element including a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; A first capacitor bank, coupled between the second terminal of the first inductor and a reference potential node; and A bypass capacitor element is coupled between the first terminal of the first inductor element and the reference potential node.

2. The apparatus of claim 1, further comprising a switch or current source coupled between the voltage rail and the first terminal of the first inductive element.

3. The apparatus of claim 1, wherein the first capacitor bank comprises: One or more switches; and One or more capacitor elements, each of the one or more capacitor elements being selectively coupled between the terminals of the first capacitor bank via a corresponding switch of the one or more switches.

4. The apparatus of claim 3, wherein the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

5. The apparatus of claim 4, wherein the one or more NMOS transistors comprise thin oxide NMOS transistors.

6. The apparatus of claim 1, wherein the first filter comprises a notch filter.

7. The apparatus of claim 1, further comprising a second filter coupled between the VCO and the reference potential node.

8. The apparatus of claim 7, wherein the second filter includes a second inductor element coupled in parallel with the second capacitor bank.

9. The apparatus of claim 8, wherein the second capacitor bank comprises: One or more switches; and One or more capacitor elements, each of the one or more capacitor elements being selectively coupled between the terminals of the second capacitor bank via a corresponding switch of the one or more switches.

10. The apparatus of claim 9, wherein the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

11. The apparatus of claim 10, wherein the one or more NMOS transistors comprise thin oxide NMOS transistors.

12. The apparatus of claim 7, wherein the second filter comprises a notch filter.

13. The apparatus of claim 7, wherein the second filter is configured to attenuate a signal with a frequency twice the oscillation frequency of the VCO.

14. The apparatus of claim 1, wherein the first filter is configured to attenuate a signal with a frequency twice that of the oscillation frequency of the VCO.

15. A method for generating an oscillating signal, the method comprising: A first capacitor bank of a first filter is configured based on the oscillation frequency of a voltage-controlled oscillator (VCO), wherein at least a portion of the first filter is coupled between a voltage rail and the VCO, and the first filter comprises: A first inductor element, the first inductor element including a first terminal coupled to the voltage rail and a second terminal coupled to the VCO, wherein a first capacitor bank is coupled between the second terminal of the first inductor element and a reference potential node; and A bypass capacitor element, the bypass capacitor element being coupled between the first terminal of the first inductor element and the reference potential node; and An oscillation signal with the oscillation frequency is generated via the VCO.

16. The method of claim 15, wherein the first capacitor bank comprises: One or more switches; and One or more capacitor elements, each of the one or more capacitor elements being selectively coupled between the terminals of the first capacitor bank via a corresponding switch of the one or more switches.

17. The method of claim 16, wherein the one or more switches comprise one or more n-type metal-oxide-semiconductor (NMOS) transistors.

18. The method of claim 17, wherein the one or more NMOS transistors comprise thin oxide NMOS transistors.

19. The method of claim 15, wherein the first filter comprises a notch filter.

20. A wireless device, the wireless device comprising: One or more antennas; A transmitter or receiver coupled to the one or more antennas and including a frequency synthesizer, wherein the frequency synthesizer includes a voltage-controlled oscillator (VCO). and A filter, coupled to the VCO, wherein the filter comprises: An inductor, the inductor comprising a first terminal coupled to a voltage rail and a second terminal coupled to the VCO; A capacitor bank, coupled between the second terminal and the reference potential node; and A bypass capacitor element is coupled between the first terminal of the inductor element and the reference potential node.

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