Silicon carbide VDMOS with source shielding structure

Abstract

The utility model provides a silicon carbide VDMOS with a source electrode shielding structure. The silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; a groove is formed in the drift layer; the insulating dielectric layer is arranged on the groove, a source electrode shielding layer is arranged in the insulating dielectric layer, a groove is formed in the insulating dielectric layer, and the groove is located above the source electrode shielding layer; the lower side surface of the well region is connected to the upper side surface of the drift layer, a source region is arranged in the well region, one side surface of the source region and one side surface of the well region are connected to one side surface of the insulating dielectric layer, and the upper side surface of the source shielding layer is higher than the lower side surface of the well region; the source electrode metal layer is connected to the well region and the source region, and the source electrode metal layer is electrically connected to the source electrode shielding layer; the gate metal layer is arranged in the groove; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the source shielding layer reduces the capacitance effect from the gate metal layer to the drift layer, so that the gate-drain Miller capacitance is effectively reduced, the gate charge of the device is reduced, the switching speed of the device is improved, and the driving loss of the device is reduced.

Description

Technical Field

[0001] The utility model relates to a silicon carbide VDMOS with a source shielding structure. Background Art

[0002] As a representative device among silicon carbide power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. Among them, trench gate silicon carbide VDMOS has attracted much attention for its advantages such as low on-resistance and low drive charge, but it has gate reliability problems caused by electric field concentration at the gate corner, and the capacitance effect between the gate and the drift layer is large, resulting in large Maitreya capacitance in the device during high-voltage turn-on and turn-off, which in turn affects the switching speed and switching loss of the device, resulting in a reduction in switching speed and an increase in switching loss. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS with a source shielding structure, in which the source shielding layer of the device reduces the capacitance effect from the gate metal layer to the drift layer, thereby effectively reducing the gate-drain Maitreya capacitance and reducing the gate charge of the device, thereby increasing the switching speed of the device and reducing the driving loss of the device.

[0004] The utility model is implemented as follows: a silicon carbide VDMOS with a source shielding structure, comprising:

[0005] Silicon carbide substrate;

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; and a groove is provided on the drift layer;

[0007] an insulating dielectric layer, the insulating dielectric layer being disposed on the groove, a source shielding layer being disposed in the insulating dielectric layer, a groove being disposed on the insulating dielectric layer, and the groove being located above the source shielding layer;

[0008] A well region, wherein the lower side of the well region is connected to the upper side of the drift layer, a source region is provided in the well region, one side of the source region and one side of the well region are both connected to one side of the insulating dielectric layer, and the upper side of the source shielding layer is higher than the lower side of the well region by a distance of;

[0009] A source metal layer, the source metal layer is connected to the well region and the source region, and the source metal layer is electrically connected to the source shielding layer;

[0010] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0011] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0012] Furthermore, the distance that the upper side surface of the source shielding layer is higher than the lower side surface of the well region is 100 nm.

[0013] Furthermore, the distance from the upper side of the source shielding layer to the lower side of the gate metal layer is 100-200 nm.

[0014] Furthermore, the distance between the lower side surface of the source shielding layer and the bottom surface of the groove is 100-500 nm.

[0015] Furthermore, the silicon carbide substrate, drift layer, and source region are all N-type; and the well region is P-type.

[0016] The advantages of the utility model are:

[0017] 1. The distance between the bottom of the source shielding structure and the top of the drift layer is 100-500nm, of which 100nm is to achieve effective shielding of the electric field of the gate metal layer and the drift layer by the source shielding structure, and the range of 100-500nm is to adapt to the situation where the etching depth is difficult to grasp under deep etching conditions. The source shielding layer of the device reduces the capacitance effect from the gate metal layer to the drift layer, thereby effectively reducing the gate-drain Maitreya capacitance and the gate charge of the device, thereby increasing the switching speed of the device and reducing the driving loss of the device;

[0018] 2. The source of the device is electrically interconnected with the source shielding structure to ensure the electric field characteristics of the source shielding structure;

[0019] 3. The device adopts a trench gate structure, the on-resistance of the device is small, and the corner from the gate metal layer to the insulating dielectric layer of the device is in the well region, which effectively suppresses the gate reliability problem caused by the electric field concentration at the gate corner;

[0020] 4. The device constructs a source shielding structure, the top of which is 100nm above the bottom of the well region and 100nm-200nm away from the bottom of the gate metal layer to ensure good insulation from the gate metal layer to the source shielding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0022] Figure 1 The utility model is a schematic diagram of a silicon carbide VDMOS with a source shielding structure.

[0023] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide VDMOS with a source shielding structure.

[0024] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 1 .

[0025] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 2 .

[0026] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 3 .

[0027] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 4 .

[0028] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 5 .

[0029] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 6 .

[0030] Fig. 9 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 7 .

[0031] Fig.10 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 8 .

[0032] Fig.11 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 9 .

[0033] Fig.12 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 10 .

[0034] Fig.13 This is a cross-sectional view of the process of a silicon carbide VDMOS with a source shielding structure of the utility model. Figure 10 one. DETAILED DESCRIPTION

[0035] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0039] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide VDMOS with a source shielding structure, including:

[0041] Silicon carbide substrate 1;

[0042] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a groove 21 is provided on the drift layer 2;

[0043] An insulating dielectric layer 3, wherein the insulating dielectric layer 3 is disposed on the groove 21, a source shielding layer 31 is disposed in the insulating dielectric layer 3, a groove 32 is disposed on the insulating dielectric layer 3, and the groove 32 is located above the source shielding layer 31;

[0044] A well region 4, wherein the lower side of the well region 4 is connected to the upper side of the drift layer 2, a source region 41 is provided in the well region 4, one side of the source region 41 and one side of the well region 4 are both connected to one side of the insulating dielectric layer 3, and the upper side of the source shielding layer 31 is higher than the lower side of the well region 4;

[0045] A source metal layer 5, the source metal layer 5 is connected to the well region 4 and the source region 41, and the source metal layer 5 is electrically connected to the source shielding layer 31;

[0046] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 32;

[0047] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0048] The distance L1 between the upper side of the source shielding layer 31 and the lower side of the well region 4 is 100nm, the distance L2 between the upper side of the source shielding layer 31 and the lower side of the gate metal layer 6 is 100-200nm, and the distance L3 between the lower side of the source shielding layer 31 and the bottom of the groove 21 is 100-500nm. The silicon carbide substrate 1, the drift layer 2, and the source region 41 are all N-type; the well region 4 is P-type.

[0049] like Figures 1 to 13 As shown, the method for preparing the above silicon carbide VDMOS comprises the following steps:

[0050] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7, and depositing and growing a drift layer 2 on the upper side of the silicon carbide substrate 1;

[0051] Step 2, ion implantation is performed on the drift layer 2 to form a well region 7, the ion implantation energy is 10-200kev, and the thickness of the well region 7 is 600nm;

[0052] Step 3, forming a barrier layer a, etching to form a through hole, and performing ion implantation on the through hole to form a source region 41, the implantation energy is 10-100kev, and the thickness of the source region 4 is 300nm;

[0053] Step 4, removing the original barrier layer a, re-forming the barrier layer a, etching to form a metal deposition area, depositing metal, and forming a source metal layer 5;

[0054] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, the well region 4 and the drift layer 2 to form a through hole and a groove 21, the etching depth L4 is 1000nm, and dry oxygen oxidation is performed after etching to form a first insulating dielectric region 33;

[0055] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a and the first insulating dielectric region 33 to form a through hole, and the etching depth L5 is 800 nm;

[0056] Step 7: depositing metal to form a source shielding layer 31, wherein the source shielding layer 31 is electrically connected to the source metal layer 5;

[0057] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, the first insulating dielectric region 33 and the source shielding layer 31 to form a through hole, and the etching depth L6 is 500 nm;

[0058] Step 9: Dry oxygen oxidation is performed after etching to form a second insulating dielectric region 34. The insulating dielectric layer 3 includes a first insulating dielectric region 33 and a second insulating dielectric region 34;

[0059] Step 10, remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a and the second insulating dielectric region 34 to form a through hole and a groove 32, deposit metal on the groove 32 to form a gate metal layer 6, remove the barrier layer a, and complete the manufacturing.

[0060] The distance L1 between the upper side of the source shielding layer 31 and the lower side of the well region 4 is 100nm, the distance L2 between the upper side of the source shielding layer 31 and the lower side of the gate metal layer 6 is 100-200nm, and the distance L3 between the lower side of the source shielding layer 31 and the bottom of the groove 21 is 100-500nm. The silicon carbide substrate 1, the drift layer 2, and the source region 41 are all N-type; the well region 4 is P-type.

[0061] The doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 6e17cm -3 The doping concentration of the source region 41 is 2e18cm -3 The doping concentration of the well region 4 is 3e17 cm-3 The doping concentration of the silicon carbide substrate 1 is to form an ohmic contact with the drain metal layer 7 and reduce the drain contact resistance; the doping concentration of the drift layer 2 is to reduce the on-resistance of the device and ensure the compromise of withstand voltage; the doping concentration of the well region 4 is to achieve effective shutdown of the device; the doping concentration of the source region 41 is to form an ohmic contact with the source metal layer 5 and reduce the on-resistance of the device.

[0062] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide VDMOS with a source shielding structure, characterized in that: include: Silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; and a groove is provided on the drift layer; an insulating dielectric layer, the insulating dielectric layer being disposed on the groove, a source shielding layer being disposed in the insulating dielectric layer, a groove being disposed on the insulating dielectric layer, and the groove being located above the source shielding layer; A well region, wherein the lower side of the well region is connected to the upper side of the drift layer, a source region is provided in the well region, one side of the source region and one side of the well region are both connected to one side of the insulating dielectric layer, and the upper side of the source shielding layer is higher than the lower side of the well region; A source metal layer, the source metal layer is connected to the well region and the source region, and the source metal layer is electrically connected to the source shielding layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. The silicon carbide VDMOS with source shielding structure according to claim 1, characterized in that: The distance between the upper side surface of the source shielding layer and the lower side surface of the well region is 100 nm.

3. The silicon carbide VDMOS with source shielding structure according to claim 1, characterized in that: The distance from the upper side of the source shielding layer to the lower side of the gate metal layer is 100-200 nm.

4. The silicon carbide VDMOS with source shielding structure according to claim 1, characterized in that: The distance between the lower side surface of the source shielding layer and the bottom surface of the groove is 100-500 nm.

5. The silicon carbide VDMOS with source shielding structure according to claim 1, characterized in that: The silicon carbide substrate, drift layer and source region are all N-type; the well region is P-type.

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