Package structure
By using cushion parts and metal pads in the package structure, the co-planarity problem caused by inconsistent RDL line width and height is solved, the electrical properties and structural reliability of the package structure are improved, and the photoresist deformation during yellow light exposure is solved and the The problem of inaccurate line width.
Patent Information
- Application Number
- CN202420853064.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-23
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-04-23
AI Technical Summary
In the chip package on fanout substrate, due to the inconsistent width and height of the RDL line, the height of the upper surface of the dielectric layer is inconsistent, which affects the line coplanarity, which may lead to the problem of photoresist deformation and inaccurate line width during yellow light exposure.
The encapsulation structure including the first dielectric layer, a cushion piece, a metal liner and a second dielectric layer is adopted. The cushion piece fills the height difference of the metal liner and ensures the coplanarity of the upper surface of the second dielectric layer. Improve the electrical properties and structural reliability of the packaging structure.
By improving the coplanarity of the package structure, the problems of photoresist deformation and inaccurate line width are reduced, and the reliability and stability of the package structure are enhanced.
Smart Images
Figure CN222146220U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging structure. Background Art
[0002] The packaging technology currently used, FOCoS (Fan Out Chip on Substrate), integrates small chips (chips) with RDL (Redistribution Layer) circuits on a fan-out substrate. Due to the growing demand for I / O (Input / Output) interfaces and the continuous miniaturization of RDL circuits, the width of the circuit affects the height of the electroplating circuit. Figure 2A In the example, the width of the first circuit structure 01 is different from the width of the second circuit structure 02, resulting in a different height of the first circuit structure 01 and the second circuit structure 02, which in turn results in an inconsistent height of the upper surface of the dielectric layer 03, resulting in a height difference. Figure 1 In the process, since RDL is made by stacking layers, the height difference of the lower layer may continue to accumulate to the upper layer line, resulting in a decrease in the coplanarity of the line, that is, there will be a height difference G, which may cause the openings exposed to yellow light to be prone to photoresist deformation problems, which will subsequently lead to the line width of the produced line not being as expected, or the lines that should not be connected are connected to each other. In addition, if the height difference is reduced by thickening the dielectric layer 03, on the one hand, the height growth has a limit, which is not conducive to miniaturization, and on the other hand, if Figure 2B As shown, the larger aspect ratio makes it more difficult to make the opening, and photoresist residue 031 is easily generated in the yellow light process. Utility Model Content
[0003] The present application provides a packaging structure, including:
[0004] a first dielectric layer;
[0005] A spacer, disposed on the first dielectric layer;
[0006] A metal liner is disposed on the first dielectric layer and is spaced apart from the spacer;
[0007] A second dielectric layer is disposed on the first dielectric layer and covers the spacer and the metal pad;
[0008] The external circuit is arranged on the second dielectric layer.
[0009] A packaging structure provided in an embodiment of the present application includes a first dielectric layer, a spacer, a metal liner, a second dielectric layer and an external circuit. The spacer is arranged on the first dielectric layer. Due to the presence of the spacer, the height difference with the metal liner is compensated, that is, a spacer structure is made using the spacer. When the second dielectric layer covers the spacer and the metal liner, the coplanarity of the upper surface of the second dielectric layer is improved, that is, there is no obvious height difference on the upper surface of the second dielectric layer at the positions corresponding to the spacer and the metal liner, thereby improving the electrical and structural reliability of the packaging structure in the embodiment of the present application.
[0010] In some optional embodiments, the packaging structure further includes an internal circuit and a first seed layer, the internal circuit is disposed on the pad, and the first seed layer is disposed between the internal circuit and the pad.
[0011] In some optional embodiments, the top end of the internal circuit is flush with the upper surface of the metal pad.
[0012] In some optional embodiments, the packaging structure further includes a second seed layer disposed between the metal liner and the first dielectric layer.
[0013] In some optional embodiments, a height of the second seed layer is lower than a height of the first seed layer.
[0014] In some optional embodiments, the upper surface of the second dielectric layer has a recess, and the orthographic projection of the recess on the first dielectric layer does not overlap with the orthographic projection of the raising member on the first dielectric layer, and the orthographic projection of the recess on the first dielectric layer does not overlap with the orthographic projection of the metal pad on the first dielectric layer.
[0015] In some optional embodiments, the turning point of the cushioning member is a rounded corner.
[0016] In some optional embodiments, the side surface of the raising member is a curved surface.
[0017] In some optional implementations, an orthographic projection of the internal circuit on the first dielectric layer is located within an orthographic projection of the spacer on the first dielectric layer.
[0018] In some optional embodiments, the raising member includes a first sub-raising block and a second sub-raising block that are spaced apart from each other, and lower surfaces of the first sub-raising block and the second sub-raising block are flush.
[0019] In some optional embodiments, the thickness of the first sub-raising block is not equal to the thickness of the second sub-raising block;
[0020] The internal circuit includes at least two connecting wires, and the upper surfaces of the first sub-raising block and the second sub-raising block are both provided with the connecting wires, and the top of the connecting wire on the first sub-raising block is flush with the top of the connecting wire on the second sub-raising block.
[0021] In some optional implementations, the number of connection lines on the first sub-raising block is the same as the number of connection lines on the second sub-raising block.
[0022] In some optional implementations, the number of connection lines on the first sub-raising block is different from the number of connection lines on the second sub-raising block.
[0023] In some optional embodiments, the raising member further includes a third sub-raising block, and the first sub-raising block, the second sub-raising block and the third sub-raising block are arranged in sequence and spaced apart along a preset direction; the lower surfaces of the first sub-raising block, the second sub-raising block and the third sub-raising block are all flush.
[0024] In some optional embodiments, the thickness of the first sub-raising block, the thickness of the second sub-raising block, and the thickness of the third sub-raising block are all equal; the internal circuit includes at least three connecting wires, and the upper surface of the first sub-raising block, the upper surface of the second sub-raising block, and the upper surface of the third sub-raising block are all provided with the connecting wires, and the top of the connecting wire on the first sub-raising block, the top of the connecting wire on the second sub-raising block, and the top of the connecting wire on the second sub-raising block are all flush.
[0025] In some optional implementations, the number of connection lines on the first sub-raising block, the number of connection lines on the second sub-raising block, and the number of connection lines on the third sub-raising block are all the same.
[0026] In some optional embodiments, there is a first spacing distance between the first sub-raising block and the second sub-raising block, and there is a second spacing distance between the second sub-raising block and the third sub-raising block, and the first spacing distance is equal to the second spacing distance.
[0027] In some optional embodiments, a cross-section of at least one of the first sub-raising block, the second sub-raising block and the third sub-raising block is in a trapezoidal shape.
[0028] In some optional embodiments, the top surface of the raising member is smaller than the bottom surface.
[0029] In some optional embodiments, the orthographic projection of the metal liner in the horizontal direction overlaps with the orthographic projection of the raising member in the horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0031] Figure 1 It is a schematic diagram of the longitudinal cross-sectional structure of a current packaging structure;
[0032] Figure 2A It is a schematic diagram of a partial longitudinal cross-sectional structure of a current packaging structure;
[0033] Figure 2B It is a schematic diagram of a local longitudinal cross-sectional structure of a current packaging structure with residues present;
[0034] Figure 3 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 3a of a packaging structure according to the present application;
[0035] Figure 4 yes Figure 3 A partial structural diagram of
[0036] Figure 5 It corresponds to Figure 3 A local enlarged schematic diagram of the middle A;
[0037] Figure 6A-6G is a schematic diagram of manufacturing steps of an embodiment of a semiconductor packaging device of the present application;
[0038] Figure 7 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 7a of a packaging structure according to the present application;
[0039] Figure 8 is a schematic diagram of a light path when photolithography is performed using photoresist in an embodiment of a packaging structure according to the present application;
[0040] Fig. 9 is a structural schematic diagram corresponding to the structural dimension identification in an embodiment of the packaging structure of the present application;
[0041] Fig.10 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 10a of a packaging structure according to the present application;
[0042] Fig.11 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 11a of a packaging structure according to the present application;
[0043] Fig.12 It corresponds to Fig.11 A local enlarged schematic diagram in FIG.
[0044] Fig.13 It is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 13a of the packaging structure according to the present application.
[0045] Description of reference numerals / symbols:
[0046] G-height difference; 01-first circuit structure; 02-second circuit structure; 03-dielectric layer; 031-residue;
[0047] 10-first dielectric layer; 20-pad; 21-first sub-pad block; 22-second sub-pad block; 23-third sub-pad block; 30-metal pad; 40-second dielectric layer; 41-recess; 50-external circuit; 60-internal circuit; 61-connecting line; 70-first seed layer; 80-second seed layer; 90-substrate; 100-third dielectric layer; 110-top pad; 120-top metal pad; 130-top internal circuit; 140-photoresist; 150-mask; 160-insulating layer; 170-seed layer; 180-electroplating layer. DETAILED DESCRIPTION
[0048] The specific implementation methods of the present application are described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the inventions. In addition, for ease of description, only the parts related to the relevant inventions are shown in the accompanying drawings.
[0049] It should be readily understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also means “on something” including the presence of intermediate components or layers therebetween.
[0050] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
[0051] The term "layer" as used herein refers to a material portion including an area with a certain thickness. A layer may extend over the entire underlying or superstructure, or may have a degree less than the extent of the underlying or superstructure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.
[0052] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed in the present application. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of the present application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present application without substantially changing the technical content.
[0053] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.
[0054] In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0055] refer to Figure 3 As shown, Figure 3 It is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 3a of a packaging structure according to the present application; a packaging structure provided by an embodiment of the present application includes: a first dielectric layer 10 arranged on a substrate 90; wherein a spacer 20 is arranged on a side of the first dielectric layer 10 away from the substrate 90, and a metal pad 30 is also arranged on a side of the first dielectric layer 10 away from the substrate 90, and the metal pad 30 is spaced apart from the spacer 20; a second dielectric layer 40 is arranged on the first dielectric layer 10, and covers the spacer 20 and the metal pad 30, at this time, the coplanarity of the upper surface of the second dielectric layer 40 is improved, so that it is convenient to set an external circuit 50 on the upper surface of the second dielectric layer 40.
[0056] It should be noted that a packaging structure provided in an embodiment of the present application includes a first dielectric layer 10, a spacer 20, a metal pad 30, a second dielectric layer 40 and an external circuit 50. The spacer 20 is arranged on the first dielectric layer 10. Due to the presence of the spacer 20, the height difference with the metal pad 30 is compensated, that is, a spacer structure is made using the spacer 20. Therefore, when the second dielectric layer 40 covers the spacer 20 and the metal pad 30, the coplanarity of the upper surface of the second dielectric layer 40 is improved, that is, the upper surface of the second dielectric layer 40 has no obvious height difference at the positions corresponding to the spacer 20 and the metal pad 30, thereby improving the electrical and structural reliability of the packaging structure in the embodiment of the present application.
[0057] Continue to refer Figure 3 , and refer to Figure 4 The packaging structure further includes an internal circuit 60 and a first seed layer 70. The internal circuit 60 is arranged on the pad 20. The side of the internal circuit 60 away from the pad 20 is substantially flush with the upper surface of the metal pad 30. In this way, when the second dielectric layer 40 is coated on the internal circuit 60, the pad 20 and the metal pad 30, there is no obvious height difference on the upper surface of the second dielectric layer 40, so that it is convenient to set the external circuit 50 on the upper surface of the second dielectric layer 40. Specifically, the first seed layer 70 is arranged between the internal circuit 60 and the pad 20. For example, the material of the first seed layer 70 can be titanium (Ti), tungsten (W), nickel (Ni). The first seed layer 70 can be attached to the pad 20 to facilitate the production of the internal circuit 60 thereon, and can enhance the adhesion between the internal circuit 60 and the pad 20, thereby improving the stability and reliability of the overall structure. In addition, the conductive performance of the first seed layer 70 is crucial to forming an effective circuit connection. The first seed layer 70 can be used as a part of the circuit to transmit current or signals. Specifically, the orthographic projection of the metal liner 30 in the horizontal direction overlaps with the orthographic projection of the spacer 20 in the horizontal direction.
[0058] Continue to refer Figure 4, the packaging structure also includes a second seed layer 80, which is disposed between the metal pad 30 and the first dielectric layer 10. The second seed layer 80 can be attached to the first dielectric layer 10 to facilitate the manufacture of the metal pad 30 thereon, and can further improve the connection stability between the first dielectric layer 10 and the metal pad 30. In addition, the height of the second seed layer 80 is lower than the height of the first seed layer 70, and the first seed layer 70 and the second seed layer 80 correspond to different positions. The first seed layer 70 is disposed on the upper surface of the pad 20 as needed, and the second seed layer 80 is disposed on the upper surface of the first dielectric layer 10. The height of the second seed layer 80 is lower than the height of the first seed layer 70, and the thickness of the second seed layer 80 is less than the thickness of the pad 20, so as to achieve more precise control of the deposition process by adjusting the height or distribution of the first seed layer 70 and the second seed layer 80, and ensure that each area obtains the required material layer thickness.
[0059] In some specific embodiments, the turning point of the padding member 20 is rounded, and the side surface of the padding member 20 is a curved surface. The design of the turning point of the padding member 20 being rounded can reduce the sharp corner effect of the padding member 20 and avoid stress concentration in these areas, because stress concentration may cause material fatigue, crack formation and expansion, and ultimately may cause device failure. By using rounded corners, stress can be dispersed and the mechanical stability of the structure can be improved.
[0060] Continue to refer Figure 4 The orthographic projection of the internal circuit 60 on the first dielectric layer 10 is located within the orthographic projection of the pad 20 on the first dielectric layer 10, and the internal circuit 60 is located within the range where the pad 20 is located. This can ensure the structural integrity of the internal circuit 60 and avoid affecting the electrical connection of the internal circuit 60 due to the provision of the pad 20.
[0061] refer to Figure 5 , Figure 5 Corresponding Figure 3 A partial enlarged schematic diagram of the area A in the middle; the upper surface of the second dielectric layer 40 has a recess 41, the orthographic projection of the recess 41 on the first dielectric layer 10 does not overlap with the orthographic projection of the spacer 20 on the first dielectric layer 10, and the orthographic projection of the recess 41 on the first dielectric layer 10 does not overlap with the orthographic projection of the metal liner 30 on the first dielectric layer 10. The position of the orthographic projection of the recess 41 on the first dielectric layer 10 corresponds to the gap between the spacer 20 and the metal liner 30. Since the height at the gap is relatively low, during the process of forming the second dielectric layer 40, the second dielectric layer 40 will be recessed into the gap to form the recess 41.
[0062] For easier understanding, please refer to Figure 6A-6G The following is a detailed description of the manufacturing process of the packaging device provided in the embodiment of the present application:
[0063] exist Fig. 6A In the embodiment, a substrate 90 is provided, the substrate 90 includes but is not limited to a glass carrier, and a first dielectric layer 10 is formed on one side surface of the substrate 90; Figure 6B , an insulating layer 160 is formed on the side of the first dielectric layer 10 away from the substrate 90, and the insulating layer 160 includes but is not limited to a photosensitive dielectric material, such as PI (polyimide), PBO (polybenzoxazole), BCB (benzocyclobutene), etc.; Figure 6C In the embodiment, the insulating layer 160 is photolithographically exposed and developed using a mask plate 150, so that the insulating layer 160 forms a spacer 20; Fig.6D In the embodiment, a seed layer 170 is formed by a PVD (Physical Vapor Deposition) process, and the seed layer 170 covers the first dielectric layer 10 and the spacer 20; Fig. 6E , a photoresist 140 is disposed on the upper surface of the seed layer 170, that is, on the side of the seed layer 170 away from the substrate 90, and a photoresist 140 having a pattern is formed by photolithography (exposure) and development steps; continue to refer to Fig. 6F , forming an electroplating layer 180 within the pattern formed by the photoresist 140; Figure 6G , remove the photoresist 140 to form the electroplating layer 180 into the internal circuit 60 and the metal pad 30; continue to refer to Figure 3 The second dielectric layer 40 is disposed on the first dielectric layer 10 and covers the spacer 20, the internal circuit 60, and the metal liner 30, and finally forms Figure 3 The package structure shown.
[0064] In some specific embodiments, reference Figure 7 , Figure 7 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 7a of a packaging structure according to the present application; Figure 7 Compared to Figure 3 Specifically, the external circuit 50 arranged on the upper surface of the second dielectric layer 40 may include a top metal pad 120, and a top raising member 110 may also be arranged on the upper surface of the second dielectric layer 40, and a top internal circuit 130 is arranged on the upper surface of the top raising member 110. Similarly, the top raising member 110 is used to ensure that the upper surface of the top metal pad 120 is basically flush with the top of the top internal circuit 130, and then after the third dielectric layer 100 covers the top metal pad 120 and the top internal circuit 130, there is no obvious height difference on the upper surface of the third dielectric layer 100.
[0065] refer to Figure 8 , Figure 8This is a schematic diagram of the light path when using photoresist 140 for photolithography in an embodiment of the packaging structure of the present application; due to the use of a spacer 20 set between the internal circuit 60 structure and the first dielectric layer 10, it is ensured that there is no obvious height difference between the upper surface of the second dielectric layer 40 covering the internal circuit 60 structure and the metal liner 30, thereby improving the problem of photoresist deformation caused by poor coplanarity during the exposure process of the photoresist 140.
[0066] For easier understanding, refer to Fig. 9 , Fig. 9 It is a structural schematic diagram corresponding to the structural dimension identification in an embodiment of the packaging structure of the present application; the width of the pad 20 is DL, the thickness of the pad 20 is D1, the internal circuit 60 structure includes at least two connecting wires 61, the width of each connecting wire 61 is L1, the height of the connecting wire 61 is L2, the thickness of the metal pad 30 is L3, and the above dimensions need to satisfy the following formula: D1+L2=L3±20%, wherein D1=0.5μm-1.5μm, for example, D1 can be 0.5μm, 1μm or 1.5μm; L2=4.5μm-4.7μm, for example, L2 is 4.6μm, 4.7μm or 4.8μm; L3=5.5μm-5.7μm, for example, L3 can be 5.5μm, 5.6μm or 5.7μm. The structures of the spacer 20 and the internal line 60 have the following corresponding relationship: DL≧L1, that is, the internal line 60 is located within the spacer 20.
[0067] In some specific implementations, the top surface of the spacer is smaller than the bottom surface, so that the shape of the spacer is conducive to the entry, flow and cleaning of etching solution.
[0068] In some specific embodiments, reference Fig.10 , Figure 7 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 10a of a packaging structure according to the present application; Fig.10 As shown, Fig.10 Compared to Figure 4 In particular, the padding member 20 includes a first sub-padding block 21 and a second sub-padding block 22 which are spaced apart. The lower surfaces of the first sub-padding block 21 and the second sub-padding block 22 are flush with each other. The thickness of the first sub-padding block 21 is not equal to the thickness of the second sub-padding block 22, that is, the upper surfaces of the first sub-padding block 21 and the second sub-padding block 22 are not coplanar. The internal circuit 60 includes at least two connecting wires 61. The upper surfaces of the first sub-padding block 21 and the second sub-padding block 22 are both provided with connecting wires 61. The top of the connecting wire 61 on the first sub-padding block 21 is flush with the top of the connecting wire 61 on the second sub-padding block 22. Of course, in Fig.10The number of connecting lines 61 located on the first sub-padded block 21 is different from the number of connecting lines 61 located on the second sub-padded block 22. Specifically, the number of connecting lines 61 located on the first sub-padded block 21 is greater than the number of connecting lines 61 located on the second sub-padded block 22, or the number of connecting lines 61 located on the first sub-padded block 21 may be less than the number of connecting lines 61 located on the second sub-padded block 22; for example, the number of connecting lines 61 located on the first sub-padded block 21 is 4, and the number of connecting lines 61 located on the second sub-padded block 22 is 2; of course, the number of connecting lines 61 located on the first sub-padded block 21 is the same as the number of connecting lines 61 located on the second sub-padded block 22 (not shown in the figure). The width and height of each of the multiple connecting lines 61 located on the first sub-raising block 21 are the same, and the width and height of each of the multiple connecting lines 61 located on the second sub-raising block 22 are the same; of course, the width of each of the multiple connecting lines 61 located on the first sub-raising block 21 is different from the width of each of the multiple connecting lines 61 located on the second sub-raising block 22, and similarly, the height of each of the multiple connecting lines 61 located on the first sub-raising block 21 is different from the height of each of the multiple connecting lines 61 located on the second sub-raising block 22.
[0069] In some specific embodiments, the raising member 20 includes a first sub-raising block 21 and a second sub-raising block 22 that are spaced apart, the lower surfaces of the first sub-raising block 21 and the second sub-raising block 22 are flush, the thickness of the first sub-raising block 21 is equal to the thickness of the second sub-raising block 22, that is, the upper surfaces of the first sub-raising block 21 and the second sub-raising block 22 are coplanar.
[0070] like Fig.11 As shown, Fig.11 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 11a of a packaging structure according to the present application; Fig.11 As shown, a single connection line 61 can be matched with a single padding member 20 below, or in other words, a single connection line 61 can be supported above a single padding member 20. For example, Fig.11 Compared to Fig.10In particular, the padding member 20 further includes a third sub-padding block 23, and the first sub-padding block 21, the second sub-padding block 22 and the third sub-padding block 23 are sequentially arranged in a predetermined direction; the lower surfaces of the first sub-padding block 21, the second sub-padding block 22 and the third sub-padding block 23 are all flush. The thickness of the first sub-padding block 21, the thickness of the second sub-padding block 22 and the thickness of the third sub-padding block 23 are all equal; of course, the thickness of the first sub-padding block 21, the thickness of the second sub-padding block 22 and the thickness of the third sub-padding block 23 may not be completely equal, for example, the thickness of the first sub-padding block 21 is the same as the thickness of the second sub-padding block 22, and the thickness of the third sub-padding block 23 is not the same as the thickness of the other two sub-padding blocks; for example, the thickness of the first sub-padding block 21 is the same as the thickness of the third sub-padding block 23, and the thickness of the second sub-padding block 22 is not the same as the thickness of the other two sub-padding blocks. The internal circuit 60 includes at least three connecting wires 61. The upper surface of the first sub-raising block 21, the upper surface of the second sub-raising block 22 and the upper surface of the third sub-raising block 23 are all provided with connecting wires 61. The top of the connecting wire 61 located on the first sub-raising block 21, the top of the connecting wire 61 located on the second sub-raising block 22 and the top of the connecting wire 61 located on the second sub-raising block 22 are all flush.
[0071] As described above, a single first sub-raising block 21, a second sub-raising block 22 or a third sub-raising block 23 may be provided below the single connection line 61. Optionally, at least one of the first sub-raising block 21, the second sub-raising block 22 and the third sub-raising block 23 or any one of the sub-raising blocks may have a structure in which the top surface is larger than the bottom surface, and such a structure is conducive to the flow of etching solution and can increase the maximum allowable etching range of wet etching.
[0072] In some specific embodiments, a single padding member 20 may also carry multiple connection lines 61. Exemplarily, the number of connection lines 61 on the first sub-padding block 21, the number of connection lines 61 on the second sub-padding block 22, and the number of connection lines 61 on the third sub-padding block 23 are all the same; of course, the number of connection lines 61 on the first sub-padding block 21, the number of connection lines 61 on the second sub-padding block 22, and the number of connection lines 61 on the third sub-padding block 23 may not be exactly the same.
[0073] For ease of understanding, Fig.12As shown, the first spacing distance CD1 is between the first sub-padded block 21 and the second sub-padded block 22, and the second spacing distance CD3 is between the second sub-padded block 22 and the third sub-padded block 23, and the first spacing distance CD1 is equal to the second spacing distance CD3. The distance between the connecting line 61 located on the first sub-padded block 21 and the connecting line 61 located on the second sub-padded block 22 is CD2, wherein CD1 is smaller than CD2. The cross-section of at least one of the first sub-padded block 21, the second sub-padded block 22 and the third sub-padded block 23 is in the shape of a trapezoid, and the length of the upper side of the trapezoid is smaller than the length of the lower side; of course, the trapezoidal shape of the first sub-padded block, the second sub-padded block and the third sub-padded block is conducive to the entry and cleaning of etching solution.
[0074] like Fig.13 As shown, Fig.13 It is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 13a of the packaging structure according to the present application. Fig.13 Compared to Fig.10 In the present invention, dummy chips (dummy dies) of different heights are first buried as a padding layer, and then the second dielectric layer 40 is made. The dummy chip can be understood as a fake chip with chip size but no electrical performance.
[0075] It is understandable that the materials of the first dielectric layer 10, the second dielectric layer 40 and the second dielectric layer 40 can be organic materials, such as PI, PA (polyamide), PBO, BCB, etc., or can be inorganic materials, such as SiOx, SiNx, SiCN or Si, etc.
[0076] Although the present application has been described and illustrated with reference to the specific embodiments of the present application, these descriptions and illustrations do not limit the present application. It is clearly understood by those skilled in the art that various changes can be made, and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present application and the actual implementation. There may be other embodiments of the present application that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the goals, spirits and scopes of the present application. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present application.
Claims
1. A packaging structure, It is characterized in that include: a first dielectric layer; A spacer, disposed on the first dielectric layer; A metal liner is disposed on the first dielectric layer and is spaced apart from the spacer; A second dielectric layer is disposed on the first dielectric layer and covers the spacer and the metal pad; The external circuit is arranged on the second dielectric layer.
2. The packaging structure according to claim 1, It is characterized in that The packaging structure further includes an internal circuit and a first seed layer. The internal circuit is disposed on the padding component, and the first seed layer is disposed between the internal circuit and the padding component.
3. The packaging structure according to claim 2, It is characterized in that The top end of the internal circuit is flush with the upper surface of the metal pad.
4. The packaging structure according to claim 2, It is characterized in that The package structure further includes a second seed layer disposed between the metal liner and the first dielectric layer.
5. The packaging structure according to claim 4, It is characterized in that The second seed layer has a height lower than that of the first seed layer.
6. The packaging structure according to claim 1, It is characterized in that The upper surface of the second dielectric layer has a recess, the orthographic projection of the recess on the first dielectric layer does not overlap with the orthographic projection of the spacer on the first dielectric layer, and the orthographic projection of the recess on the first dielectric layer does not overlap with the orthographic projection of the metal pad on the first dielectric layer.
7. The packaging structure according to claim 1, It is characterized in that The turning point of the padding member is a rounded corner.
8. The packaging structure according to claim 7, It is characterized in that The side surface of the raising member is a curved surface.
9. The packaging structure according to claim 1, It is characterized in that The padding member comprises a first sub-padding block and a second sub-padding block which are spaced apart from each other. The lower surfaces of the first sub-padding block and the second sub-padding block are flush and have unequal thicknesses.
10. The packaging structure according to claim 1, It is characterized in that The top surface of the raising member is smaller than the bottom surface.