Semiconductor module for charger, charger and electric vehicle

Abstract

The utility model discloses a semiconductor module for a charger, the charger and an electric automobile. The semiconductor module comprises a first substrate area, a second substrate area and a third substrate area which extend along the same plane, the second substrate area and the third substrate area are located on the same side of the first substrate area, the first substrate area comprises a first area and a second area, and the second substrate area comprises a third area and a fourth area. The third region is located between the second region and the fourth region; a switching circuit of the power factor correction circuit formed on the first substrate region; a switching circuit of a resonant conversion circuit including a switching circuit of a resonant conversion primary side circuit formed on the second region and a switching circuit of a resonant conversion secondary side circuit formed on the third region; and the switching circuit of the DC / DC conversion circuit comprises a switching circuit of a DC / DC conversion main side circuit formed on the fourth region and a switching circuit of a DC / DC conversion secondary side circuit formed on the third substrate region.

Description

Technical Field

[0001] The utility model relates to the field of chargers, in particular to a semiconductor module for a charger, a charger and an electric vehicle. Background Art

[0002] Electric vehicles are charged with the help of charging piles, which conforms to the concept of green environmental protection. Therefore, electric vehicles have gradually been favored by more and more people in recent years. In the related art, the electronic control device in the electric vehicle, such as the charger, is composed of several modules. The charger is usually located in the front cabin of the electric vehicle and can be connected to the charging pile through the charging harness. The component modules of the charger are usually arranged in an upper, middle and lower structure in the front cabin of the electric vehicle, and these modules are connected by wiring harnesses. However, this layout of the charger requires the management of the wiring harness of the charger, and the wiring harness management is more complicated due to the large number of wiring harnesses.

[0003] In addition, the layout of the modules of the existing chargers in the upper, middle and lower positions requires a large space, which affects the aesthetics of the interior layout of the front cabin to a certain extent. Moreover, considering that a component of the charger may be damaged and need to be repaired, a special space position needs to be set up in the front cabin of the electric vehicle to provide a suitable repair space, which will reduce the freedom of choice of the installation position of the charger. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to propose a semiconductor module for a charger, in which each circuit module of the semiconductor module is integrated into one module, which not only avoids complex wiring harness connection and complex wiring harness management, but also takes up less space in the electric vehicle, provides a larger space for the maintenance of the charger and provides a larger space selection freedom for the installation of the charger, compared with the prior art charger semiconductor module in which each circuit module is divided into an upper, middle and lower structure and connected by a wiring harness.

[0005] Another object of the present invention is to provide a charger comprising the semiconductor module.

[0006] Another object of the present invention is to provide an electric vehicle comprising the charger.

[0007] A semiconductor module for a charger according to an embodiment of the first aspect of the utility model comprises: a first substrate area, a second substrate area and a third substrate area, wherein the first substrate area, the second substrate area and the third substrate area extend along the same plane, the second substrate area and the third substrate area are located on the same side of the first substrate area, the first substrate area comprises a first region and a second region, the second substrate area comprises a third region and a fourth region, the third region is located between the second region and the fourth region; a switch circuit of a power factor correction circuit, wherein the switch circuit of the power factor correction circuit is formed on the first region of the first substrate area; a switch circuit of a resonant conversion circuit The switching circuit of the resonant conversion circuit includes a switching circuit of a resonant conversion primary circuit and a switching circuit of a resonant conversion secondary circuit, the switching circuit of the resonant conversion primary circuit is formed on the second area, and the switching circuit of the resonant conversion secondary circuit is formed on the third area; the switching circuit of the DC / DC conversion circuit, the switching circuit of the DC / DC conversion circuit includes a switching circuit of a DC / DC conversion primary circuit and a switching circuit of a DC / DC conversion secondary circuit, the switching circuit of the DC / DC conversion primary circuit is formed on the fourth area, and the switching circuit of the DC / DC conversion secondary circuit is formed on the third substrate area.

[0008] According to some embodiments of the present invention, the first region and the second region are arranged sequentially along a first direction, the second region, the third region and the fourth region are arranged sequentially along a second direction perpendicular to the first direction, and the third substrate region and the second substrate region are arranged sequentially along the first direction.

[0009] According to some embodiments of the utility model, the first region includes a first sub-region and a second sub-region arranged in sequence along the first direction, and the second sub-region is located between the first sub-region and the second region, wherein the switching circuit of the power factor correction circuit includes multiple pairs of first semiconductor chips, and the multiple pairs of first semiconductor chips are located in the first sub-region and arranged in sequence along the second direction, and the two first semiconductor chips in each pair of first semiconductor chips are spaced apart along the second direction and connected in series to each other.

[0010] According to some embodiments of the utility model, the sources of the multiple pairs of first semiconductor chips are electrically connected to the respective first source signal detection terminals one by one through electrical connection lines, and the gates of the multiple pairs of first semiconductor chips are electrically connected to the respective first gate signal detection terminals one by one through electrical connection lines, and the respective first source signal detection terminals are arranged at intervals along the second direction on the first sub-region, and the respective first gate signal detection terminals are arranged at intervals along the second direction on the first sub-region and are spaced apart from the respective first source signal detection terminals in the first direction.

[0011] According to some embodiments of the utility model, the semiconductor module also includes a first power signal AC end and multiple first power signal negative DC transmission ends for each pair of first semiconductor chips located in the first sub-area, wherein, in each pair of first semiconductor chips, the source of one first semiconductor chip is connected to the drain of another first semiconductor chip through an electrical connection line, the drain of the one first semiconductor chip is electrically connected to one of the multiple first power signal positive DC transmission ends, the source of the other first semiconductor chip is electrically connected to another of the multiple first power signal negative DC transmission ends, and the first power signal AC end is connected between the source of the one first semiconductor chip and the drain of the other first semiconductor chip.

[0012] According to some embodiments of the utility model, the switching circuit of the power factor correction circuit also includes multiple pairs of second semiconductor chips located in the second sub-area, the two second semiconductor chips in the same pair of second semiconductor chips are connected in parallel, and the second semiconductor chips in different pairs are connected in series in sequence.

[0013] According to some embodiments of the present invention, the source of one second semiconductor chip in each pair of second semiconductor chips is electrically connected to a second source signal detection terminal located in the second sub-region through an electrical connection line, and the gate of one second semiconductor chip in each pair of second semiconductor chips is electrically connected to a second gate signal detection terminal located in the second sub-region through an electrical connection line.

[0014] According to some embodiments of the present invention, the semiconductor module also includes a second power signal AC terminal and a plurality of second power signal negative DC transmission terminals for the multiple pairs of second semiconductor chips located in the first area, one of the multiple second power signal positive DC transmission terminals in the first area is electrically connected to the drain of the first pair of second semiconductor chips among the multiple pairs of second semiconductor chips connected in series in sequence, another of the multiple second power signal negative DC transmission terminals is electrically connected to the source of the last pair of second semiconductor chips among the multiple pairs of second semiconductor chips connected in series in sequence, and the second power signal AC terminal is connected between two adjacent pairs of second semiconductor chips among the multiple pairs of second semiconductor chips connected in series in sequence.

[0015] According to some embodiments of the present invention, the first semiconductor chip is a MOS chip, the second semiconductor chip is an IGBT chip or an FRD chip, the multiple pairs of first semiconductor chips are 3 pairs of first semiconductor chips, and the multiple pairs of second semiconductor chips are 2 pairs of second semiconductor chips.

[0016] According to some embodiments of the present invention, the switching circuit of the resonant conversion primary side circuit includes multiple pairs of third semiconductor chips, and the two third semiconductor chips in each pair of third semiconductor chips are connected in series with each other; the switching circuit of the resonant conversion secondary side circuit includes multiple pairs of fourth semiconductor chips, and the two fourth semiconductor chips in each pair of fourth semiconductor chips are connected in series with each other.

[0017] According to some embodiments of the present invention, the sources of the multiple pairs of third semiconductor chips are electrically connected to the respective third source signal detection terminals located in the second area through electrical connection lines, and the gates of the multiple pairs of third semiconductor chips are electrically connected to the respective third gate signal detection terminals located in the second area through electrical connection lines; and the sources of the multiple pairs of fourth semiconductor chips are electrically connected to the respective fourth source signal detection terminals located in the third area through electrical connection lines, and the gates of the multiple pairs of fourth semiconductor chips are electrically connected to the respective fourth gate signal detection terminals located in the third area through electrical connection lines.

[0018] According to some embodiments of the utility model, the semiconductor module further includes a third power signal AC terminal and a plurality of third power signal negative DC output terminals for each pair of third semiconductor chips located in the second region, wherein, in each pair of the third semiconductor chips, the source of one of the first semiconductor chips is connected to the drain of another third semiconductor chip through an electrical connection line, the drain of the one third semiconductor chip is electrically connected to one of the plurality of third power signal positive DC transmission terminals, the source of the other third semiconductor chip is electrically connected to another of the plurality of third power signal negative DC transmission terminals, and the third power signal AC terminal is connected between the source of the one third semiconductor chip and the drain of the other third semiconductor chip. The semiconductor module further comprises a fourth power signal AC terminal and a plurality of fourth power signal negative DC transmission terminals for each pair of fourth semiconductor chips located in the third region, wherein, in each pair of the fourth semiconductor chips, the source of one fourth semiconductor chip is connected to the drain of another fourth semiconductor chip through an electrical connection line, the drain of the one fourth semiconductor chip is electrically connected to one of the plurality of fourth power signal positive DC transmission terminals, the source of the other fourth semiconductor chip is electrically connected to another of the plurality of fourth power signal negative DC transmission terminals, and the fourth power signal AC terminal is connected between the source of the one fourth semiconductor chip and the drain of the other fourth semiconductor chip.

[0019] According to some embodiments of the present invention, the multiple pairs of third semiconductor chips are 2 pairs of third semiconductor chips, the multiple pairs of fourth semiconductor chips are 2 pairs of fourth semiconductor chips, and the third semiconductor chips and the fourth semiconductor chips are MOS chips.

[0020] According to some embodiments of the present invention, the switching circuit of the DC / DC conversion main side circuit includes multiple pairs of fifth semiconductor chips, and two fifth semiconductor chips in each pair of fifth semiconductor chips are connected in series with each other, wherein the source of one of the two fifth semiconductor chips is connected to the drain of the other fifth semiconductor chip.

[0021] According to some embodiments of the present invention, the sources in the multiple pairs of fifth semiconductor chips are electrically connected one-to-one to the fourth source signal detection terminals located in the fourth region through electrical connection lines, and the gates in the multiple pairs of fifth semiconductor chips are electrically connected one-to-one to the fourth gate signal detection terminals located in the fourth region through electrical connection lines.

[0022] According to some embodiments of the utility model, the switch circuit of the secondary circuit of the DC / DC conversion includes a first group of gate resistors, a first group of sixth semiconductor chips, a second group of gate resistors, and a second group of sixth semiconductor chips arranged in sequence along the first direction, and the number of sixth semiconductor chips in each group of sixth semiconductor chips is equal to the number of gate resistors in each group of gate resistors. The sixth semiconductor chips in the first group of sixth semiconductor chips are arranged at intervals along the second direction, and the gate resistors in the first group of gate resistors are arranged at intervals along the second direction, each sixth semiconductor chip in the first group of sixth semiconductor chips is connected in series with a corresponding gate resistor in the first group of gate resistors to form a first chip-gate resistor pair, and each of the first chip-gate resistor pairs is connected in parallel with each other. The sixth semiconductor chips in the second group of sixth semiconductor chips are arranged at intervals along the second direction, and the gate resistors in the second group of gate resistors are arranged at intervals along the second direction, each sixth semiconductor chip in the second group of sixth semiconductor chips is connected in series with a corresponding gate resistor in the second group of gate resistors to form a second chip-gate resistor pair, and each of the second chip-gate resistor pairs is connected in parallel with each other.

[0023] According to some embodiments of the present invention, the fifth semiconductor chip is a MOS chip, the sixth semiconductor chip is a MOS chip, the first group of sixth semiconductor chips and the second group of sixth semiconductor chips each include four sixth semiconductor chips, and the multiple pairs of fifth semiconductor chips are 2 pairs of fifth semiconductor chips.

[0024] According to some embodiments of the present utility model, the semiconductor module includes a fifth power signal AC terminal and a plurality of fifth power signal negative DC transmission terminals for each pair of fifth semiconductor chips, one of the plurality of fifth power signal positive DC transmission terminals is connected to the drain of one of the fifth semiconductor chips, another of the plurality of fifth power signal negative DC transmission terminals is connected to the source of the other fifth semiconductor chip, and the fifth power signal AC terminal is connected between the drain of one of the fifth semiconductors and the source of the other fifth semiconductor chip.

[0025] According to some embodiments of the utility model, the switching circuit of the DC / DC conversion circuit includes a first DC electrode output terminal, a second DC electrode output terminal and a second DC electrode output terminal, the first DC electrode output terminal, the second DC electrode output terminal and the second DC electrode output terminal are located on the third substrate area and are spaced apart along the first direction, the first DC electrode output terminal is electrically connected to the drain of the sixth semiconductor chip in the first group of sixth semiconductor chips, the second DC electrode output terminal is electrically connected to the source of the sixth semiconductor chip in the first group of sixth semiconductor chips and the second group of sixth semiconductor chips, and the third DC electrode output terminal is electrically connected to the drain of the sixth semiconductor chip in the second group of sixth semiconductor chips, wherein the second DC electrode output terminal is used to be connected to a transformer outside the semiconductor module.

[0026] According to some embodiments of the present invention, the semiconductor module also includes thermistors respectively arranged on the first substrate area, the second substrate area and the third substrate area, and at least two thermistor terminals are respectively provided on the first substrate area, the second substrate area and the third substrate area, and the two thermistor terminals in the first substrate area, the second substrate area and the third substrate area are respectively connected to the two ends of the corresponding thermistor.

[0027] According to some embodiments of the present invention, the thermistor in the first substrate area is arranged on a side of the first region close to the second substrate area and the third substrate area, the thermistor in the second substrate area is arranged on a side of the second substrate area close to the third substrate area, and the thermistor in the third substrate area is arranged on a side of the third substrate area close to the second substrate area.

[0028] A charger according to an embodiment of the second aspect of the utility model includes: a semiconductor module according to any embodiment of the first aspect of the utility model; a first capacitor, the first capacitor is included in the power factor correction circuit, and the two ends of the first capacitor are connected in parallel with the switching circuit of the resonant conversion main circuit; a first transformer, the first transformer is connected between the switching circuit of the resonant conversion main circuit and the switching circuit of the resonant conversion secondary circuit; and a second transformer, the second transformer is connected between the switching circuit of the DC / DC conversion main circuit and the switching circuit of the DC / DC conversion secondary circuit.

[0029] According to some embodiments of the utility model, the multiple pairs of third semiconductor chips are 2 pairs of third semiconductor chips, and the multiple pairs of fourth semiconductor chips are 2 pairs of fourth semiconductor chips, wherein the charger further includes: a first inductor, a first end of the first inductor is connected between two third semiconductor chips in a pair of third semiconductor chips in the 2 pairs of third semiconductor chips, and a second end of the first inductor is connected to a first end of a primary coil of the first transformer; a second capacitor, a first end of the second capacitor is connected between two third semiconductor chips in another pair of third semiconductor chips in the 2 pairs of third semiconductor chips, and a second end of the second capacitor is connected to a second end of the primary coil of the first transformer; a second inductor, a first end of the second inductor is connected between two fourth semiconductor chips in a pair of fourth semiconductor chips in the 2 pairs of fourth semiconductor chips, and a second end of the second inductor is connected to a first end of a secondary coil of the first transformer; and a third capacitor, a first end of the third capacitor is connected between two fourth semiconductor chips in another pair of fourth semiconductor chips in the 2 pairs of fourth semiconductor chips, and a second end of the third capacitor is connected to a second end of the secondary coil of the first transformer.

[0030] According to some embodiments of the present utility model, the charger further includes: a fourth capacitor, wherein the fourth capacitor is connected in parallel with the switch circuit of the resonant conversion secondary circuit.

[0031] According to some embodiments of the present invention, the charger further includes: a third inductor, a first end of the third inductor being connected to the secondary coil of the second transformer, and a second end of the third inductor being connected between the first group of sixth semiconductor chips and the second group of sixth semiconductor chips.

[0032] According to some embodiments of the utility model, the multiple pairs of first semiconductor chips include a first pair of first semiconductor chips, a second pair of first semiconductor chips and a third pair of first semiconductor chips, wherein the charger also includes: a fourth inductor, a first end of the fourth inductor is connected to an external power grid, and the other end of the fourth inductor is connected between the two first semiconductor chips of the first pair of first semiconductor chips; a fifth inductor, a first end of the fifth inductor is connected to the external power grid, and the other end of the fifth inductor is connected between the two first semiconductor chips of the second pair of first semiconductor chips; and a sixth inductor, a first end of the sixth inductor is connected to the external power grid, and the other end of the sixth inductor is connected between the two first semiconductor chips of the third pair of first semiconductor chips.

[0033] An electric vehicle according to an embodiment of the third aspect of the utility model comprises a charger according to any one of the embodiments of the second aspect of the utility model.

[0034] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0036] Figure 1 It is a schematic structural diagram of a semiconductor module for a charger according to an embodiment of the utility model.

[0037] Figure 2 yes Figure 1 1. A top view of a semiconductor module shown in FIG.

[0038] Figure 3 yes Figure 1 A top view of a first substrate region of a semiconductor module and a circuit structure arranged on the first substrate region is shown in FIG.

[0039] Figure 4 yes Figure 1 FIG. 1 is a top view of a second substrate region of a semiconductor module and a circuit structure arranged on the second substrate region.

[0040] Figure 5 yes Figure 1 FIG. 1 is a top view of a third substrate region of a semiconductor module and a circuit structure arranged on the third substrate region.

[0041] Figure 6 yes Figure 1 Schematic diagram of the structure of the first semiconductor chip and the third semiconductor chip shown in .

[0042] Figure 7 yes Figure 1 Schematic diagram of the structure of the second semiconductor chip serving as an FRD shown in FIG.

[0043] Figure 8 yes Figure 1 Schematic diagram of the structure of the second semiconductor chip serving as an IGBT is shown in FIG.

[0044] Fig. 9 yes Figure 1 Schematic diagram of the structure of the fourth semiconductor chip and the fifth semiconductor chip shown in FIG.

[0045] Fig.10 yes Figure 1 Schematic diagram of the structure of the sixth semiconductor chip shown in .

[0046] Fig.11 yes Figure 1 Schematic diagram of the structure of the gate resistor shown in.

[0047] Fig.12 yes Figure 1 Schematic diagram of the thermistor structure shown in .

[0048] Fig.13 This is a schematic diagram of electrical connection lines when the first semiconductor chip or the third semiconductor chip is a SiC MOS chip.

[0049] Fig.14 This is a schematic diagram of electrical connection lines when the second semiconductor chip is an IGBT chip.

[0050] Fig.15 FIG. 4 is a schematic diagram of electrical connection lines when the fourth semiconductor chip is a Si MOS chip.

[0051] Fig.16 FIG. 4 is a schematic diagram of electrical connection lines when the fifth semiconductor chip is a Si MOS chip.

[0052] Fig.17 4 is a schematic diagram of electrical connection lines when the sixth semiconductor chip is a Si MOS chip.

[0053] Fig.18 It is a schematic diagram of the electrical connection wires of the thermistor.

[0054] Fig.19 This is a schematic diagram of the electrical connection lines of the gate resistor.

[0055] Fig. 20 It is a schematic topological structure diagram of a charger according to an embodiment of the utility model.

[0056] Fig.21 It is a schematic block diagram of an electric vehicle according to an embodiment of the utility model.

[0057] Reference numerals:

[0058] Semiconductor module 1000; first substrate region 1; second substrate region 2; third substrate region 3;

[0059] A first semiconductor chip 41; a second semiconductor chip 42; a third semiconductor chip 511; a fourth semiconductor chip 521;

[0060] a fifth semiconductor chip 611; a first group of gate resistors 621; a first group of sixth semiconductor chips 622; a second group of gate resistors 623; a second group of sixth semiconductor chips 624; a sixth semiconductor chip 6221; a first chip-gate resistor pair 625; a second chip-gate resistor pair 626; a first direction AA; a second direction BB;

[0061] Electrical connection line 7; first source signal detection terminal 1a; first gate signal detection terminal 1b; first power signal positive DC transmission terminals 1c, 1e; first power signal AC terminal 1d;

[0062] A second source signal detection terminal 2a; a second gate signal detection terminal 2b; second power signal positive DC transmission terminals 2c, 2e; a second power signal AC terminal 2d;

[0063] A third source signal detection terminal 3a; a third gate signal detection terminal 3b; a third power signal positive DC transmission terminal 3c, 3e; a third power signal AC terminal 3d;

[0064] A fourth source signal detection terminal 4a; a fourth gate signal detection terminal 4b; fourth power signal positive DC transmission terminals 4c, 4e, and a fourth power signal AC terminal 4d;

[0065] A fifth source signal detection terminal 5a; a fifth gate signal detection terminal 5b; a fifth power signal positive DC transmission terminal 5c, 5e; a fifth power signal AC terminal 5d;

[0066] A first DC electrode output terminal 6a, a second DC electrode output terminal 6b; a third DC electrode output terminal 6c;

[0067] Thermistor 8; thermistor terminal 9; a first DC signal detection terminal 10a; a second DC signal detection terminal 10b; a third DC signal detection terminal 10c;

[0068] The first capacitor C1; the first transformer T1; the primary coil T11 of the first transformer; the secondary coil T12 of the first transformer; the second transformer T2; the primary coil T21 of the second transformer; the secondary coil T22 of the second transformer; the first inductor L1; the second capacitor C2; the second inductor L2; the third capacitor C3; the fourth capacitor C4; the third inductor L3; the fourth inductor L4; the fifth inductor L5; the sixth inductor L6; the charger 2000; the electric car 3000. DETAILED DESCRIPTION

[0069] Embodiments of the present invention are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary.

[0070] Combine the following Figures 1 to 19 The semiconductor module 1000 for a charger according to an embodiment of the utility model is described. The semiconductor module 1000 can be, for example, a semiconductor module of a vehicle-mounted integrated charger. The semiconductor module 1000 can be installed on a charger of an electric vehicle and connected to a charging pile of the electric vehicle through a charging cable, thereby charging the electric vehicle and providing energy power for the driving of the electric vehicle.

[0071] refer to Figure 1-Figure 5 According to the first embodiment of the utility model, the semiconductor module 1000 for a charger includes a first substrate area 1, a second substrate area 2 and a third substrate area 3. The first substrate area 1, the second substrate area 2 and the third substrate area 3 extend along the same plane. In other words, the first substrate area 1, the second substrate area 2 and the third substrate area 3 are located in the same layer. Optionally, the first substrate area 1, the second substrate area 2 and the third substrate area 3 may be different areas of the same substrate; or optionally, the first substrate area 1, the second substrate area 2 and the third substrate area 3 may be defined on different substrates. For example, in either of these two optional cases, the substrate may be a ceramic copper-clad substrate, but is not limited thereto.

[0072] like Figure 1-Figure 5 As shown, the second substrate area 2 and the third substrate area 3 are located on the same side of the first substrate area 1, the first substrate area 1 includes a first area 11 and a second area 12, the second substrate area 2 includes a third area 21 and a fourth area 22, and the third area 21 is located between the second area 12 and the fourth area 22. For example, Figure 1 As shown, the first substrate region 1 is located on the left side of the semiconductor module 1000 , and the second substrate region 2 and the third substrate region 3 are located on the right side of the semiconductor module 1000 . The third region 21 is located on the right side of the second region 12 , and the fourth region 22 is located on the right side of the third region 21 .

[0073] like Figure 1-Figure 5As shown, the semiconductor module 1000 also includes a switching circuit of a power factor correction (PFC) circuit, a switching circuit of a resonant conversion circuit (LLC), and a switching circuit of a DC / DC conversion circuit. Specifically, the switching circuit of the power factor correction circuit is formed on the first area 11 of the first substrate area 1. The switching circuit of the resonant conversion circuit includes a switching circuit of a resonant conversion primary circuit and a switching circuit of a resonant conversion secondary circuit, the switching circuit of the resonant conversion primary circuit is formed on the second area 12, and the switching circuit of the resonant conversion secondary circuit is formed on the third area 21. The switching circuit of the DC / DC conversion circuit includes a switching circuit of a DC / DC conversion primary circuit and a switching circuit of a DC / DC conversion secondary circuit, the switching circuit of the DC / DC conversion primary circuit is formed on the fourth area 22, and the switching circuit of the DC / DC conversion secondary circuit is formed on the third substrate area 3. It can be seen that the switching circuit of the power factor correction circuit, the switching circuit of the resonant conversion circuit and the switching circuit of the DC / DC conversion circuit are all integrated on the substrate area located on the same layer. Compared with the prior art in which each circuit is arranged on a different module, these modules are arranged in order from top to bottom, and these modules are connected together through wiring harnesses to form a semiconductor module, the layout method of the semiconductor module 1000 of the utility model realizes a highly integrated design, which can avoid complex wiring harness connections and complex wiring harness management, and can work in a high power range.

[0074] Moreover, the second substrate area 2 and the third substrate area 3 are located on the same side of the first substrate area 1 in the semiconductor module 1000, the switching circuit of the power factor correction circuit is formed on the first area 11 of the first substrate area 1, the switching circuit of the resonant conversion main side circuit of the switching circuit of the resonant conversion circuit is formed on the second area 12 of the first substrate, the switching circuit of the resonant conversion secondary side circuit of the switching circuit of the resonant conversion circuit is formed on the third area 21 adjacent to the second area 12, the switching circuit of the DC / DC conversion main side circuit of the switching circuit of the DC / DC conversion circuit is formed on the fourth area 22 adjacent to the third area 21, and the switching circuit of the DC / DC conversion secondary side circuit is formed on the third substrate area 3. The layout of the various circuits in these substrate areas realizes efficient utilization of the various areas in the first substrate area 1, the second substrate area 2 and the third substrate area 3, and realizes the miniaturization of the semiconductor module 1000, which can reduce the occupied space of the entire semiconductor module 1000 and thereby reduce the occupied space of the entire charger. Furthermore, when the semiconductor module 1000 is used in a charger such as a charger for an electric vehicle, for example, the charger is installed in the front cabin of the electric vehicle, it can provide greater freedom of choice for the specific installation location of the charger including the semiconductor module 1000, and when a component in the charger is damaged, more space can be left in the front cabin to facilitate maintenance personnel to inspect the charger.

[0075] Therefore, according to the semiconductor module 1000 for a charger according to the embodiment of the utility model, through the above-mentioned layout of its various circuits, it is possible to avoid complicated wiring harness connection and wiring harness management, and the entire charger can be miniaturized, occupying a small space, and having a high degree of freedom in choosing its installation position. Moreover, when installed on, for example, an electric vehicle, when the charger needs maintenance, a larger maintenance space can be left for maintenance personnel, thereby facilitating the maintenance personnel's operation.

[0076] According to some further embodiments of the present invention, the first region 11 and the second region 12 are sequentially arranged along a first direction, the second region 12, the third region 21 and the fourth region 22 are sequentially arranged along a second direction perpendicular to the first direction, and the third substrate region 3 and the second substrate region 2 are sequentially arranged along the first direction. Figure 1-Figure 5 As shown in the figure, for example, along the first direction AA, in the first substrate area 1, the first area 11 and the second area 12 are sequentially arranged; the third substrate area 3 and the second substrate area 2 are arranged on the right side of the first substrate area 1, and the third substrate area 3 and the second substrate area 2 are sequentially arranged along the first direction AA; the second area 12 of the first substrate area 1, the third area 21 of the second substrate area 2 and the fourth area 22 of the second substrate area 2 are sequentially arranged along the second direction BB perpendicular to the first direction AA. In other words, in the figure, Figure 1 On the page of , the first area 11 is located above the second area 12, the third substrate area 3 and the second substrate area 2 are located on the right side of the first area 11 and the second area 12 and the third substrate area 3 is located above the second substrate area 2, and the third area 21 of the second substrate area 2 is located on the right side of the second area 12 and on the left side of the fourth area 22. With this arrangement, when the total area of ​​the first substrate area 1, the second substrate area 2 and the third substrate area 3 is the same, the size of the semiconductor module 1000 in any direction is avoided to be too large, which not only facilitates the layout of each circuit, but also makes it easier to flexibly select the installation position of the semiconductor module 1000 and the charger including the semiconductor module 1000 in the front cabin of the electric vehicle, for example.

[0077] Alternatively, if Figure 1-Figure 5 As shown, the first substrate region 1 , the second substrate region 2 and the third substrate region 3 all have a substantially rectangular shape.

[0078] Further optionally, in the case where the first substrate region 1 , the second substrate region 2 and the third substrate region 3 are formed on the same substrate, the substrate also substantially has a rectangular shape.

[0079] According to some optional embodiments of the present invention, reference Figure 1-Figure 5, the first region 11 includes a first sub-region 111 and a second sub-region 112 arranged in sequence along the first direction, and the second sub-region 112 is located between the first sub-region 111 and the second region 12. Figure 1-Figure 3 In the figure, along the first direction AA, the first sub-region 111, the second sub-region 112 and the second region 12 are arranged in sequence. The switch circuit of the power factor correction circuit includes a plurality of pairs of first semiconductor chips 41, which are located in the first sub-region 111 and arranged in sequence along the second direction BB, and the two first semiconductor chips 41 in each pair of first semiconductor chips 41 are arranged at intervals along the second direction BB and connected in series with each other. In this way, the plurality of pairs of first semiconductor chips 41 in the first sub-region 111 realize the PFC fast tube function, and the overall layout of each semiconductor chip of the switch circuit of the power factor correction circuit is regular.

[0080] Furthermore, if Figure 1-Figure 3 As shown, the sources of the multiple pairs of first semiconductor chips 41 are electrically connected to the respective first source signal detection terminals 1a (e.g., detection pins) one by one through electrical connection lines 7 (e.g., bonding wires), and the first source signal detection terminals 1a are used to detect the signals of the sources of the first semiconductor chips 41. In addition, the gates of the multiple pairs of first semiconductor chips 41 are electrically connected to the respective first gate signal detection terminals 1b one by one through electrical connection lines 7, and the first gate signal detection terminals 1b are used to detect the signals of the gates of the first semiconductor chips 41. The respective first source signal detection terminals 1a are arranged at intervals along the second direction BB on the first sub-region 111, and the respective first gate signal detection terminals 1b are arranged at intervals along the second direction BB on the first sub-region 111 and are spaced apart from the respective first source signal detection terminals 1a in the first direction AA. For example, as Figure 1-Figure 3 As shown, each first source signal detection terminal 1a is arranged in a row along the second direction BB, each first gate signal detection terminal 1b is arranged in a row along the second direction BB, and each first source signal detection terminal 1a is arranged on the side of each first gate signal detection terminal 1b away from the second area 12. Therefore, the arrangement of the first source signal detection terminal 1a and the first gate signal detection terminal 1b is relatively regular, which is convenient for the installation of these detection terminals, and can ensure that the connection between the first source signal detection terminal 1a and the source of the first semiconductor chip 41 and the connection between the first gate signal detection terminal 1b and the gate of the first semiconductor chip 41 are relatively regular, further ensuring that the layout of the internal structure of the semiconductor module 1000 for the charger is regular, and facilitating the wiring of each circuit structure of the charger.

[0081] According to some embodiments of the present invention, Figure 1-Figure 3As shown, the semiconductor module 1000 for a charger also includes a plurality of first power signal positive DC transmission terminals 1c, 1e, and a first power signal AC terminal 1d for each pair of first semiconductor chips 41 located in the first sub-area 111, wherein, in each pair of first semiconductor chips 41, the source of one first semiconductor chip 41 is connected to the drain of another first semiconductor chip 41 through an electrical connection line 7, the drain of the one first semiconductor chip 41 is electrically connected to one first power signal positive DC transmission terminal 1c among the plurality of first power signal positive DC transmission terminals, the source of the other first semiconductor chip 41 is electrically connected to the first power signal negative DC transmission terminal 1e among the plurality of first power signal positive DC transmission terminals, and the first power signal AC terminal 1d is connected between the source of the one first semiconductor chip 41 and the drain of the other first semiconductor chip 41. With such an arrangement, it is possible to provide an AC signal to each pair of first semiconductor chips 41 through the first power signal AC terminal 1d, provide a DC input to the pair of first semiconductor chips 41 through the first power signal positive DC transmission terminal 1c and the first power signal negative DC transmission terminal 1e, and obtain a DC output of the pair of first semiconductor chips 41, thereby realizing the circuit function.

[0082] According to some embodiments of the present invention, reference Figure 1-Figure 12 , the switch circuit of the power factor correction circuit also includes multiple pairs of second semiconductor chips 42 located in the second sub-area 112, two second semiconductor chips 42 in the same pair of second semiconductor chips 42 are connected in parallel, one of the two second semiconductor chips 42 is an IGBT chip, and the other of the two second semiconductor chips 42 is an FRD chip, and different pairs of second semiconductor chips 42 are connected in series in sequence. For example, the drain of the IGBT chip is connected to the positive electrode of the FRD chip, and the source of the IGBT is connected to the negative electrode of the FRD. In this way, the multiple pairs of second semiconductor chips 42 in the second sub-area 112 realize the PFC slow tube function, and the multiple pairs of second semiconductor chips 42 in the second sub-area 112 realize the PFC slow tube function.

[0083] According to some embodiments of the present invention, reference Figure 1-Figure 3 The source of the second semiconductor chip 42 in each pair of second semiconductor chips 42 is electrically connected to a second source signal detection terminal 2a located in the second sub-region 112 through the electrical connection line 7, and the gate of the second semiconductor chip 42 in each pair of second semiconductor chips 42 is electrically connected to a second gate signal detection terminal 2b located in the second sub-region 112 through the electrical connection line 7. Specifically, Figure 1In the example, the source of the IGBT chip is connected to a second source signal detection terminal 2a located in the second sub-region 112, and the second source signal detection terminal 2a is used to detect the signal of the source of the IGBT chip, and can also detect the signal of the negative electrode of the FRD connected in parallel with the IGBT; the gate of the IGBT chip is connected to a second gate signal detection terminal 2b located in the second sub-region 112, and the second gate signal detection terminal 2b is used to detect the signal of the gate of the IGBT chip.

[0084] like Figure 1-Figure 3 As shown, the semiconductor module 1000 for the charger also includes a second power signal AC terminal 2d and a plurality of second power signal negative DC transmission terminals 2c, 2e for the multiple pairs of second semiconductor chips 42 located in the first area 11, one of the second power signal positive DC transmission terminals 2c among the multiple second power signal negative DC transmission terminals in the first area 11 is electrically connected to the drain of the second semiconductor chip 42 in the first pair of second semiconductor chips 42 among the multiple pairs of second semiconductor chips 42 connected in series in sequence, one of the second power signal negative DC transmission terminals 2e is electrically connected to the source of the second semiconductor chip 42 in the last pair of second semiconductor chips 42 among the multiple pairs of second semiconductor chips 42 connected in series in sequence, and the second power signal AC terminal 2d is connected between two adjacent pairs of second semiconductor chips 42 among the multiple pairs of second semiconductor chips 42 connected in series in sequence.

[0085] According to some embodiments of the present invention, Figure 1-Figure 12 As shown, the first semiconductor chip 41 is a MOS chip, the multiple pairs of first semiconductor chips 41 are 3 pairs of first semiconductor chips 41, and the multiple pairs of second semiconductor chips 42 are 2 pairs of second semiconductor chips 42. It can be understood that the number of the multiple pairs of first semiconductor chips 41 is not limited to 3 pairs, and the number of the multiple pairs of second semiconductor chips 42 is not limited to 2 pairs. For the purpose of simplicity, the utility model does not give examples one by one.

[0086] Furthermore, the first semiconductor chip 41 is a SiC MOS chip.

[0087] According to some embodiments of the present invention, reference Figure 1-Figure 4 The switch circuit of the resonant conversion primary circuit includes a plurality of pairs of third semiconductor chips 511, and the two third semiconductor chips 511 in each pair of third semiconductor chips 511 are connected in series with each other. The switch circuit of the resonant conversion secondary circuit includes a plurality of pairs of fourth semiconductor chips 521, and the two fourth semiconductor chips 521 in each pair of fourth semiconductor chips 521 are connected in series with each other. The switch circuit of the resonant conversion primary circuit and the switch circuit of the resonant conversion secondary circuit together constitute the switch circuit of the resonant conversion circuit.

[0088] According to some embodiments of the present invention, reference Figure 1-Figure 4 The sources of the plurality of pairs of third semiconductor chips 511 are electrically connected to the third source signal detection terminals 3a located in the second region 12 through the electrical connection wires 7 in a one-to-one correspondence, and the third source signal detection terminals 3a are used to detect the signal of the source of the third semiconductor chip 511. The gates of the plurality of pairs of third semiconductor chips 511 are electrically connected to the third gate signal detection terminals 3b located in the second region 12 in a one-to-one correspondence through the electrical connection wires 7, and the third gate signal detection terminals 3b are used to detect the signal of the gate of the third semiconductor chip 511. The sources of the plurality of pairs of fourth semiconductor chips 521 are electrically connected to the fourth source signal detection terminals 4a located in the third region 21 in a one-to-one correspondence through the electrical connection wires 7, and the fourth source signal detection terminals 4a are used to detect the signal of the source of the fourth semiconductor chip 521. The gates of the plurality of pairs of fourth semiconductor chips 521 are electrically connected to the fourth gate signal detection terminals 4b located in the third region 21 in a one-to-one correspondence through the electrical connection wires 7, and the fourth gate signal detection terminals 4b are used to detect the signal of the gate of the fourth semiconductor chip 521.

[0089] According to some embodiments of the present invention, Figure 1-Figure 4 As shown, the semiconductor module 1000 for the charger further includes a third power signal AC terminal 3d and a plurality of third power signal negative DC transmission terminals 3c, 3e for each pair of third semiconductor chips 511 located in the second area 12. Among them, in each pair of third semiconductor chips 511, the source of one third semiconductor chip 511 is connected to the drain of another third semiconductor chip 511 through an electrical connection line 7, the drain of the one third semiconductor chip 511 is electrically connected to a third power signal positive DC transmission terminal 3c among the plurality of third power signal negative DC transmission terminals, the source of the other third semiconductor chip 511 is electrically connected to a third power signal negative DC transmission terminal 3e among the plurality of third power signal negative DC transmission terminals, and the third power signal AC terminal 3d is connected between the source of the one third semiconductor chip 511 and the drain of the other third semiconductor chip 511. With such an arrangement, it is possible to provide an AC signal to each pair of third semiconductor chips 511 through the third power signal AC terminal 3d, provide a DC input to the pair of third semiconductor chips 511 through the third power signal positive DC transmission terminal 3c and the third power signal negative DC transmission terminal 3e, and obtain a DC output for the pair of third semiconductor chips 511.

[0090] According to some embodiments of the present invention, Figure 1-Figure 3As shown, the semiconductor module 1000 for the charger further includes a fourth power signal AC terminal 4d and a plurality of fourth power signal positive DC transmission terminals 4c, 4e for each pair of fourth semiconductor chips 521 located in the third region 21. Among them, in each pair of fourth semiconductor chips 521, the source of one fourth semiconductor chip 521 is connected to the drain of another fourth semiconductor chip 521 through an electrical connection line 7, the drain of the one fourth semiconductor chip 521 is electrically connected to one fourth power signal positive DC transmission terminal 4c of the plurality of fourth power signal positive DC transmission terminals, the source of the other fourth semiconductor chip 521 is electrically connected to one fourth power signal negative DC transmission terminal 4e of the plurality of fourth power signal positive DC transmission terminals, and the fourth power signal AC terminal 4d is connected between the source of the one fourth semiconductor chip 521 and the drain of the other fourth semiconductor chip 521. With such an arrangement, it is possible to provide an AC signal to each pair of fourth semiconductor chips 521 through the fourth power signal AC terminal 4d, provide a DC input to the pair of fourth semiconductor chips 521 through the fourth power signal positive DC transmission terminal 4c and the fourth power signal negative DC transmission terminal 4e, and obtain a DC output for the pair of fourth semiconductor chips 521.

[0091] According to some embodiments of the present invention, Figure 1-Figure 12 As shown, the plurality of pairs of third semiconductor chips 511 are 2 pairs of third semiconductor chips 511, the plurality of pairs of fourth semiconductor chips 521 are 2 pairs of fourth semiconductor chips 521, and the third semiconductor chips 511 and the fourth semiconductor chips 521 are MOS chips. It is understandable that the number of the plurality of pairs of third semiconductor chips 511 is not limited to 2 pairs, and the number of the plurality of pairs of fourth semiconductor chips 521 is not limited to 2 pairs. For the purpose of simplicity, the present utility model does not give examples one by one.

[0092] Furthermore, the third semiconductor chip 511 is a SiC MOS chip, and the fourth semiconductor chip 521 is a Si MOS chip.

[0093] According to some embodiments of the present invention, the switching circuit of the DC / DC conversion main side circuit includes multiple pairs of fifth semiconductor chips 611, and the two fifth semiconductor chips 611 in each pair of fifth semiconductor chips 611 are connected in series with each other, wherein the source of one of the two fifth semiconductor chips 611 is connected to the drain of the other fifth semiconductor chip 611.

[0094] Further, according to some embodiments of the present invention, the sources in the plurality of pairs of fifth semiconductor chips 611 are electrically connected to the fifth source signal detection terminal 5a located in the fourth region 22 through the electrical connection line 7 in a one-to-one correspondence, and the fifth source signal detection terminal 5a is used to detect the signal of the source of the fifth semiconductor chip 611. The gates in the plurality of pairs of fifth semiconductor chips 611 are electrically connected to the fifth gate signal detection terminal 5b located in the fourth region 22 in a one-to-one correspondence through the electrical connection line 7, and the fifth gate signal detection terminal 5b is used to detect the signal of the gate of the fifth semiconductor chip 611.

[0095] According to some embodiments of the present invention, Figure 1-Figure 5 As shown, the switch circuit of the secondary circuit of the DC / DC converter includes a first group of gate resistors 621, a first group of sixth semiconductor chips 622, a second group of gate resistors 623, and a second group of sixth semiconductor chips 624 arranged in sequence along the first direction AA, and the number of sixth semiconductor chips 6221 in each group of sixth semiconductor chips is equal to the number of gate resistors in each group of gate resistors. The sixth semiconductor chips 6221 in the first group of sixth semiconductor chips 622 are arranged at intervals along the second direction BB, and the gate resistors in the first group of gate resistors 621 are arranged at intervals along the second direction BB, and each sixth semiconductor chip 6221 in the first group of sixth semiconductor chips 622 is connected in series with a corresponding gate resistor in the first group of gate resistors 621 to form a first chip-gate resistor pair 625, and each first chip-gate resistor pair 625 is connected in parallel to each other. The sixth semiconductor chips 6221 in the second group of sixth semiconductor chips 624 are arranged at intervals along the second direction BB, and the gate resistors in the second group of gate resistors 623 are arranged at intervals along the second direction BB. Each sixth semiconductor chip 6221 in the second group of sixth semiconductor chips 624 is connected in series with a corresponding gate resistor in the second group of gate resistors 623 to form a second chip-gate resistor pair 626, and each second chip-gate resistor pair 626 is connected in parallel with each other. In this way, the arrangement of each component of the switch circuit of the secondary side circuit of the DC / DC conversion is relatively regular, which is conducive to the wiring of the switch circuit of the secondary side circuit of the DC / DC conversion, thereby facilitating the manufacture of the semiconductor module 1000 used for the charger and the entire charger. In addition, the gate resistor can protect the gate of the sixth semiconductor chip 6221 and realize the current sharing function. During the opening and closing process of the sixth semiconductor chip 6221, the sixth semiconductor chip 6221 can be prevented from generating a large oscillation, thereby ensuring the circuit stability of the charger including the semiconductor module 1000.

[0096] For example, in Figure 1In the embodiment, the first group of gate resistors 621 are arranged in a row along the second direction BB, the first group of sixth semiconductor chips 622 are arranged in a row along the second direction BB, the second group of gate resistors 623 are arranged in a row along the second direction BB, and the second group of sixth semiconductor chips 624 are arranged in a row along the second direction BB. In each first chip-gate resistor pair 625 and each second chip-gate resistor pair 626, one end of the gate resistor is connected to the gate of the sixth semiconductor chip 6221, and the other ends of the gate resistors in different pairs of first chip-gate resistor pairs 625 are electrically connected to each other through the electrical connection line 7, and the other ends of the gate resistors in different pairs of second chip-gate resistor pairs 626 are electrically connected to each other through the electrical connection line 7.

[0097] According to some embodiments of the present invention, the fifth semiconductor chip 611 is a MOS chip, the sixth semiconductor chip 6221 is a MOS chip, the first group of sixth semiconductor chips 622 and the second group of sixth semiconductor chips 624 each include four sixth semiconductor chips 6221, and the multiple pairs of fifth semiconductor chips 611 are 2 pairs of fifth semiconductor chips 611. It can be understood that the number and type of the fifth semiconductor chip and the sixth semiconductor chip 6221 are not limited thereto, and for the purpose of brevity, the present invention does not exemplify them one by one.

[0098] Furthermore, the fifth semiconductor chip 611 is a Si MOS chip, and the sixth semiconductor chip 6221 is a Si MOS chip.

[0099] According to some embodiments of the present invention, reference Figure 1-Figure 5 , the semiconductor module 1000 for the charger includes a fifth power signal AC terminal 5d and a plurality of fifth power signal positive DC transmission terminals 5c and 5e for each pair of fifth semiconductor chips 611. One of the plurality of fifth power signal positive DC transmission terminals 5c is connected to the drain of one of the fifth semiconductor chips 611, one of the plurality of fifth power signal positive DC transmission terminals 5e is connected to the source of another fifth semiconductor chip 611, and the fifth power signal AC terminal 5d is connected between the source of one of the fifth semiconductors and the drain of another fifth semiconductor chip 611. In this way, it is possible to provide an AC signal to the pair of fifth semiconductor chips 611 through the first power signal AC terminal 1d, provide a DC input to the pair of fifth semiconductor chips 611 through the fifth power signal positive DC transmission terminal 5c and the fifth power signal negative DC transmission terminal 5e, and obtain a DC output of the pair of fifth semiconductor chips 611.

[0100] According to some embodiments of the present invention, reference Figure 1-Figure 5The switch circuit of the DC / DC conversion circuit includes a first DC electrode output terminal 6a, a second DC electrode output terminal 6b and a third DC electrode output terminal 6c, which are located on the third substrate area 3 and spaced apart along the first direction, the first DC electrode output terminal 6a is electrically connected to the drain of the sixth semiconductor chip 6221 in the first group of sixth semiconductor chips 622, the second DC electrode output terminal 6b is electrically connected to the source of the sixth semiconductor chip 6221 in the first group of sixth semiconductor chips 622 and the second group of sixth semiconductor chips 624, and the third DC electrode output terminal 6c is electrically connected to the drain of the sixth semiconductor chip 6221 in the second group of sixth semiconductor chips 624, wherein the second DC electrode output terminal 6b is used to be connected to a transformer outside the semiconductor module 1000. After being connected to the transformer, the second DC electrode output terminal 6b outputs its output signal to the power battery.

[0101] Further, refer to Figure 1-Figure 5 A first DC signal detection terminal 10a, a second DC signal detection terminal 10b, and a third DC signal detection terminal 10c are provided in the third substrate area 3. The first DC signal detection terminal 10a, the second DC signal detection terminal 10b, and the third DC signal detection terminal 10c are electrically connected to the first DC electrode output terminal 6a, the second DC electrode output terminal 6b, and the third DC electrode output terminal 6c, respectively, and the DC signals at these output terminals are detected accordingly.

[0102] According to some embodiments of the present invention, reference Figure 1-Figure 5 The semiconductor module 1000 for a charger further includes a thermistor 8 respectively arranged on the first substrate area 1, the second substrate area 2 and the third substrate area 3, and at least two thermistor terminals 9 are respectively arranged on the first substrate area 1, the second substrate area 2 and the third substrate area 3, and the two thermistor terminals 9 in the first substrate area 1, the second substrate area 2 and the third substrate area 3 are respectively connected to the two ends of the corresponding thermistor 8.

[0103] Further, refer to Figure 1-Figure 5 A thermistor 8 is provided in each of the first substrate area 1, the second substrate area 2 and the third substrate area 3, and both ends of each thermistor 8 are respectively connected to corresponding thermistor terminals 9, so as to detect the temperature conditions of the first substrate area 1, the second substrate area 2 and the third substrate area 3.

[0104] For the electrical connection method of each component in the semiconductor module 1000 for the charger, please refer to Figures 13 to 19Specifically, the source S and gate G of the SiC MOS chip are electrically connected, the source S and gate G of the IGBT chip are electrically connected, the source S and gate G of the Si MOS chip are electrically connected, the two ends of the thermistor 8 are electrically connected, and the two ends of the gate resistor are electrically connected.

[0105] According to some embodiments of the present invention, Figure 1 and Figure 2 As shown, the thermistor 8 in the first substrate area 1 is arranged on the side of the first region 11 close to the second substrate area 2 and the third substrate area 3, the thermistor 8 in the second substrate area 2 is arranged on the side of the second substrate area 2 close to the third substrate area 3, and the thermistor 8 in the third substrate area 3 is arranged on the side of the third substrate area 3 close to the second substrate area 2. Compared with the thermistors in the prior art arranged on the housing of the semiconductor module or the housing of the charger, each thermistor 8 of the present application is located on the substrate of the semiconductor, and the measurement result is closer to the junction temperature of the circuit in the semiconductor module, thereby obtaining a more accurate measurement result.

[0106] According to the charger 2000 of the second embodiment of the utility model, refer to Fig. 20 Combined with Figure 1-Figure 19 , comprising: a semiconductor module 1000 and a first capacitor C1 according to any embodiment of the first aspect of the utility model, wherein the first capacitor C1 is included in a power factor correction circuit, and both ends of the first capacitor C1 are connected in parallel with the switch circuit of the resonant conversion primary circuit. The charger 2000 also includes a first transformer T1, and the first transformer T1 is connected between the switch circuit of the resonant conversion primary circuit and the switch circuit of the resonant conversion secondary circuit. The charger 2000 also includes a second transformer T2, and the second transformer T2 is connected between the switch circuit of the DC / DC conversion primary circuit and the switch circuit of the DC / DC conversion secondary circuit.

[0107] Therefore, according to the charger 2000 of the embodiment of the utility model, by including the above-mentioned semiconductor module, complex wiring harness connection and wiring harness management can be avoided, and the miniaturization of the entire charger 2000 can be achieved, occupying a small space, and the freedom of choice of its installation position is relatively high. When installed on, for example, an electric vehicle, when the charger 2000 needs to be repaired, a larger maintenance space can be left for maintenance personnel, thereby facilitating the operation of the maintenance personnel.

[0108] According to some embodiments of the present invention, reference Fig. 20, the plurality of pairs of third semiconductor chips are 2 pairs of third semiconductor chips, and the plurality of pairs of fourth semiconductor chips are 2 pairs of fourth semiconductor chips. The charger 2000 further includes a first inductor L1, a second capacitor C2, a second inductor L2 and a third capacitor C3. The first end of the first inductor L1 is connected between two third semiconductor chips in one pair of the above two pairs of third semiconductor chips, and the second end of the first inductor L1 is connected to the first end of the primary coil T11 of the first transformer T1. The first end of the second capacitor C2 is connected between two third semiconductor chips in another pair of the above two pairs of third semiconductor chips, and the second end of the second capacitor C2 is connected to the second end of the primary coil T11 of the first transformer T1. The first end of the second inductor L2 is connected between two fourth semiconductor chips in one pair of the above two pairs of fourth semiconductor chips, and the second end of the second inductor L2 is connected to the first end of the secondary coil T12 of the first transformer T1. A first end of the third capacitor C3 is connected between two fourth semiconductor chips in another pair of the two pairs of fourth semiconductor chips, and a second end of the third capacitor C3 is connected to a second end of the secondary coil T12 of the first transformer T1.

[0109] Further, refer to Fig. 20 The charger 2000 further includes a fourth capacitor C4, which is connected in parallel with the switch circuit of the resonant conversion secondary circuit.

[0110] According to some embodiments of the present invention, reference Fig. 20 Combined with Figure 1-Figure 2 The charger 2000 further includes: a third inductor L3, a first end of the third inductor L3 is connected to the secondary coil T22 of the second transformer T2, and a second end of the third inductor L3 is connected between the first group of sixth semiconductor chips and the second group of sixth semiconductor chips.

[0111] According to some embodiments of the present invention, reference Fig. 20 Combined with Figure 1-Figure 2 , the plurality of pairs of first semiconductor chips include a first pair of first semiconductor chips, a second pair of first semiconductor chips, and a third pair of first semiconductor chips; the charger 2000 further includes a fourth inductor L4, a fifth inductor L5, and a sixth inductor L6. A first end of the fourth inductor L4 is connected to an external power grid, and the other end of the fourth inductor L4 is connected between two first semiconductor chips of the first pair of first semiconductor chips; a first end of the fifth inductor L5 is connected to an external power grid, and the other end of the fifth inductor L5 is connected between two first semiconductor chips of the second pair of first semiconductor chips; and a first end of the sixth inductor L6 is connected to an external power grid, and the other end of the sixth inductor L6 is connected between two first semiconductor chips of the third pair of first semiconductor chips.

[0112] According to the electric vehicle 3000 of the third embodiment of the utility model, Fig.21 As shown, it includes the charger 2000 described in any implementation of the second aspect of the utility model.

[0113] Therefore, the electric vehicle 3000 according to the embodiment of the utility model can avoid complicated wiring harness connection and wiring harness management by including the charger 2000 according to the first aspect of the utility model, and has a higher freedom of choice of installation position on the electric vehicle 3000. When the charger 1000 needs maintenance, it can leave a larger maintenance space for maintenance personnel, facilitating the operation of maintenance personnel.

[0114] It should be noted that the above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any technical personnel in this field, without departing from the scope of the technical solution of the present invention, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

[0115] In the description of the present invention, it should be understood that the terms "center", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "lateral", "longitudinal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0116] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0117] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor module for a charger, characterized in that: include: a first substrate region, a second substrate region and a third substrate region, wherein the first substrate region, the second substrate region and the third substrate region extend along the same plane, the second substrate region and the third substrate region are located on the same side of the first substrate region, the first substrate region includes a first area and a second area, the second substrate region includes a third area and a fourth area, and the third area is located between the second area and the fourth area; a switch circuit of a power factor correction circuit, wherein the switch circuit of the power factor correction circuit is formed on a first area of ​​the first substrate area; a switching circuit of a resonant conversion circuit, wherein the switching circuit of the resonant conversion circuit comprises a switching circuit of a resonant conversion primary circuit and a switching circuit of a resonant conversion secondary circuit, wherein the switching circuit of the resonant conversion primary circuit is formed on the second region, and the switching circuit of the resonant conversion secondary circuit is formed on the third region; The switching circuit of the DC / DC conversion circuit comprises a switching circuit of a DC / DC conversion primary circuit and a switching circuit of a DC / DC conversion secondary circuit, the switching circuit of the DC / DC conversion primary circuit is formed on the fourth area, and the switching circuit of the DC / DC conversion secondary circuit is formed on the third substrate area.

2. The semiconductor module according to claim 1, characterized in that The first region and the second region are sequentially arranged along a first direction, the second region, the third region and the fourth region are sequentially arranged along a second direction perpendicular to the first direction, and the third substrate region and the second substrate region are sequentially arranged along the first direction.

3. The semiconductor module according to claim 2, characterized in that The first region includes a first sub-region and a second sub-region sequentially arranged along the first direction, and the second sub-region is located between the first sub-region and the second region. Among them, the switching circuit of the power factor correction circuit includes multiple pairs of first semiconductor chips, which are located in the first sub-area and arranged in sequence along the second direction, and the two first semiconductor chips in each pair of first semiconductor chips are arranged at intervals along the second direction and connected in series with each other.

4. The semiconductor module according to claim 3, characterized in that The sources of the multiple pairs of first semiconductor chips are electrically connected to the respective first source signal detection terminals one by one through electrical connection lines, and the gates of the multiple pairs of first semiconductor chips are electrically connected to the respective first gate signal detection terminals one by one through electrical connection lines, and the respective first source signal detection terminals are arranged at intervals along the second direction on the first sub-region, and the respective first gate signal detection terminals are arranged at intervals along the second direction on the first sub-region and are spaced apart from the respective first source signal detection terminals in the first direction.

5. The semiconductor module according to claim 3, characterized in that The semiconductor module further includes a first power signal AC terminal and a plurality of first power signal DC transmission terminals for each pair of first semiconductor chips located in the first sub-region. Among them, in each pair of first semiconductor chips, the source of one first semiconductor chip is connected to the drain of another first semiconductor chip through an electrical connection line, the drain of the one first semiconductor chip is electrically connected to one of the multiple first power signal DC transmission ends, the source of the other first semiconductor chip is electrically connected to another of the multiple first power signal DC transmission ends, and the first power signal AC end is connected between the source of the one first semiconductor chip and the drain of the other first semiconductor chip.

6. The semiconductor module according to claim 3, characterized in that The switching circuit of the power factor correction circuit also includes multiple pairs of second semiconductor chips located in the second sub-area, two second semiconductor chips in the same pair of second semiconductor chips are connected in parallel, one of the two second semiconductor chips is an IGBT chip, and the other of the two second semiconductor chips is an FRD chip, and different pairs of second semiconductor chips are connected in series in sequence.

7. The semiconductor module according to claim 6, characterized in that The source of the one second semiconductor chip in each pair of second semiconductor chips is electrically connected to a second source signal detection terminal located in the second sub-region through an electrical connection line, and the gate of the one second semiconductor chip in each pair of second semiconductor chips is electrically connected to a second gate signal detection terminal located in the second sub-region through an electrical connection line.

8. The semiconductor module according to claim 6, characterized in that The semiconductor module also includes a second power signal AC terminal and a plurality of second power signal DC transmission terminals for the multiple pairs of second semiconductor chips located in the first area, one of the multiple second power signal DC transmission terminals in the first area is electrically connected to the drain of the first pair of second semiconductor chips among the multiple pairs of second semiconductor chips connected in series, another of the multiple second power signal DC transmission terminals is electrically connected to the source of the last pair of second semiconductor chips among the multiple pairs of second semiconductor chips connected in series, and the second power signal AC terminal is connected between two adjacent pairs of second semiconductor chips among the multiple pairs of second semiconductor chips connected in series.

9. The semiconductor module according to claim 8, characterized in that The first semiconductor chip is a MOS chip, the multiple pairs of first semiconductor chips are three pairs of first semiconductor chips, and the multiple pairs of second semiconductor chips are two pairs of second semiconductor chips.

10. The semiconductor module according to claim 6, characterized in that The switch circuit of the resonant conversion main side circuit comprises a plurality of pairs of third semiconductor chips, and two third semiconductor chips in each pair of third semiconductor chips are connected in series with each other; The switch circuit of the resonant conversion secondary circuit includes a plurality of pairs of fourth semiconductor chips, and two fourth semiconductor chips in each pair of fourth semiconductor chips are connected in series.

11. The semiconductor module according to claim 10, characterized in that The sources of the plurality of pairs of third semiconductor chips are electrically connected to the third source signal detection terminals located in the second region one by one through electrical connection lines, and the gates of the plurality of pairs of third semiconductor chips are electrically connected to the third gate signal detection terminals located in the second region one by one through electrical connection lines; as well as The sources of the multiple pairs of fourth semiconductor chips are electrically connected one-to-one to respective fourth source signal detection terminals located in the third area through electrical connection lines, and the gates of the multiple pairs of fourth semiconductor chips are electrically connected one-to-one to respective fourth gate signal detection terminals located in the third area through electrical connection lines.

12. The semiconductor module according to claim 10, characterized in that The semiconductor module further includes a third power signal AC terminal and a plurality of third power signal DC transmission terminals for each pair of third semiconductor chips located in the second region, wherein, in each pair of the third semiconductor chips, a source of one of the first semiconductor chips is connected to a drain of another third semiconductor chip through an electrical connection line, a drain of the one third semiconductor chip is electrically connected to one of the plurality of third power signal DC transmission terminals, a source of the other third semiconductor chip is electrically connected to another of the plurality of third power signal DC transmission terminals, and the third power signal AC terminal is connected between the source of the one third semiconductor chip and the drain of the other third semiconductor chip; The semiconductor module also includes a fourth power signal AC terminal and a plurality of fourth power signal DC transmission terminals for each pair of fourth semiconductor chips located in the third area, wherein, in each pair of the fourth semiconductor chips, the source of one of the fourth semiconductor chips is connected to the drain of another fourth semiconductor chip through an electrical connection line, the drain of the one fourth semiconductor chip is electrically connected to one of the plurality of fourth power signal DC transmission terminals, the source of the other fourth semiconductor chip is electrically connected to another of the plurality of fourth power signal DC transmission terminals, and the fourth power signal AC terminal 4d is connected between the source of the one fourth semiconductor chip and the drain of the other fourth semiconductor chip.

13. The semiconductor module according to claim 12, characterized in that The plurality of pairs of third semiconductor chips are 2 pairs of third semiconductor chips, the plurality of pairs of fourth semiconductor chips are 2 pairs of fourth semiconductor chips, and the third semiconductor chips and the fourth semiconductor chips are MOS chips.

14. The semiconductor module according to claim 10, characterized in that The switching circuit of the DC / DC conversion main side circuit includes multiple pairs of fifth semiconductor chips, and the two fifth semiconductor chips in each pair of fifth semiconductor chips are connected in series with each other, wherein the source of one of the two fifth semiconductor chips is connected to the drain of the other fifth semiconductor chip.

15. The semiconductor module according to claim 14, characterized in that The sources in the multiple pairs of fifth semiconductor chips are electrically connected one-to-one to the fifth source signal detection terminals located in the fourth area through electrical connection lines, and the gates in the multiple pairs of fifth semiconductor chips are electrically connected one-to-one to the fifth gate signal detection terminals located in the fourth area through electrical connection lines.

16. The semiconductor module according to claim 14, characterized in that The switch circuit of the DC / DC conversion secondary circuit comprises a first group of gate resistors, a first group of sixth semiconductor chips, a second group of gate resistors, and a second group of sixth semiconductor chips arranged in sequence along the first direction, wherein the number of sixth semiconductor chips in each group of sixth semiconductor chips is equal to the number of gate resistors in each group of gate resistors. The sixth semiconductor chips in the first group of sixth semiconductor chips are arranged at intervals along the second direction, the gate resistors in the first group of gate resistors are arranged at intervals along the second direction, each sixth semiconductor chip in the first group of sixth semiconductor chips is connected in series with a corresponding gate resistor in the first group of gate resistors to form a first chip-gate resistor pair, and each of the first chip-gate resistor pairs is connected in parallel with each other, and Among them, the sixth semiconductor chips in the second group of sixth semiconductor chips are arranged at intervals along the second direction, the gate resistors in the second group of gate resistors are arranged at intervals along the second direction, each sixth semiconductor chip in the second group of sixth semiconductor chips is connected in series with a corresponding gate resistor in the second group of gate resistors to form a second chip-gate resistor pair, and each of the second chip-gate resistor pairs is connected in parallel to each other.

17. The semiconductor module according to claim 16, characterized in that The fifth semiconductor chip is a MOS chip, the sixth semiconductor chip is a MOS chip, the first group of sixth semiconductor chips and the second group of sixth semiconductor chips each include four sixth semiconductor chips, and the multiple pairs of fifth semiconductor chips are 2 pairs of fifth semiconductor chips.

18. The semiconductor module according to claim 14, characterized in that The semiconductor module includes a fifth power signal AC terminal and a plurality of fifth power signal DC transmission terminals for each pair of fifth semiconductor chips, one of the plurality of fifth power signal DC transmission terminals is connected to the drain of one of the fifth semiconductor chips, another of the plurality of fifth power signal DC transmission terminals is connected to the source of the other fifth semiconductor chip, and the fifth power signal AC terminal is connected between the drain of one of the fifth semiconductors and the source of the other fifth semiconductor chip.

19. The semiconductor module according to claim 18, characterized in that The switching circuit of the DC / DC conversion circuit includes a first DC electrode output terminal, a second DC electrode output terminal and a third DC electrode output terminal, wherein the first DC electrode output terminal, the second DC electrode output terminal and the third DC electrode output terminal are located on the third substrate area and are spaced apart along the first direction, the first DC electrode output terminal is electrically connected to the drain of the sixth semiconductor chip in the first group of sixth semiconductor chips, the second DC electrode output terminal is electrically connected to the source of the sixth semiconductor chip in the first group of sixth semiconductor chips and the second group of sixth semiconductor chips, and the third DC electrode output terminal is electrically connected to the drain of the sixth semiconductor chip in the second group of sixth semiconductor chips, wherein the second DC electrode output terminal is used to be connected to a transformer outside the semiconductor module.

20. The semiconductor module according to any one of claims 1 to 19, characterized in that It also includes thermistors respectively arranged on the first substrate area, the second substrate area and the third substrate area, wherein at least two thermistor terminals are respectively arranged on the first substrate area, the second substrate area and the third substrate area, and the two thermistor terminals in the first substrate area, the second substrate area and the third substrate area are respectively connected to the two ends of the corresponding thermistor.

21. The semiconductor module according to claim 20, characterized in that The thermistor in the first substrate region is arranged on a side of the first region close to the second substrate region and the third substrate region, the thermistor in the second substrate region is arranged on a side of the second substrate region close to the third substrate region, and the thermistor in the third substrate region is arranged on a side of the third substrate region close to the second substrate region.

22. A charger, characterized in that: include: The semiconductor module according to any one of claims 1 to 21; A first capacitor, the first capacitor is included in the power factor correction circuit, and both ends of the first capacitor are connected in parallel with the switch circuit of the resonant conversion main side circuit; a first transformer, wherein the first transformer is connected between a switch circuit of the resonant conversion primary circuit and a switch circuit of the resonant conversion secondary circuit; as well as A second transformer, wherein the second transformer is connected between the switch circuit of the DC / DC conversion primary circuit and the switch circuit of the DC / DC conversion secondary circuit.

23. The charger according to claim 22, characterized in that: The plurality of pairs of third semiconductor chips are 2 pairs of third semiconductor chips, and the plurality of pairs of fourth semiconductor chips are 2 pairs of fourth semiconductor chips, wherein the charger further comprises: a first inductor, wherein a first end of the first inductor is connected between two third semiconductor chips in one pair of the two pairs of third semiconductor chips, and a second end of the first inductor is connected to a first end of a primary coil of the first transformer; a second capacitor, wherein a first end of the second capacitor is connected between two third semiconductor chips in another pair of the two pairs of third semiconductor chips, and a second end of the second capacitor is connected to a second end of the primary coil of the first transformer; a second inductor, a first end of the second inductor being connected between two fourth semiconductor chips in one pair of the two pairs of fourth semiconductor chips, and a second end of the second inductor being connected to a first end of a secondary coil of the first transformer; and A third capacitor, wherein a first end of the third capacitor is connected between two fourth semiconductor chips in another pair of fourth semiconductor chips in the two pairs of fourth semiconductor chips, and a second end of the third capacitor is connected to a second end of the secondary coil of the first transformer.

24. The charger according to claim 23, characterized in that: Also includes: A fourth capacitor is connected in parallel with the switch circuit of the resonant conversion secondary circuit.

25. The charger according to any one of claims 22 to 24, characterized in that: The charger also includes: A third inductor, wherein a first end of the third inductor is connected to the secondary coil of the second transformer, and a second end of the third inductor is connected between the first group of sixth semiconductor chips and the second group of sixth semiconductor chips.

26. The charger according to any one of claims 22 to 24, characterized in that: The plurality of pairs of first semiconductor chips include a first pair of first semiconductor chips, a second pair of first semiconductor chips, and a third pair of first semiconductor chips, wherein the charger further includes: a fourth inductor, wherein a first end of the fourth inductor is connected to an external power grid, and another end of the fourth inductor is connected between two first semiconductor chips of the first pair of first semiconductor chips; a fifth inductor, a first end of which is connected to the external power grid, and another end of which is connected between the two first semiconductor chips of the second pair of first semiconductor chips; and A sixth inductor, wherein a first end of the sixth inductor is connected to an external power grid, and the other end of the sixth inductor is connected between two first semiconductor chips of the third pair of first semiconductor chips.

27. An electric vehicle, characterized in that: Comprising a charger according to any one of claims 22-26.

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