Circuit structure and chip for measuring on resistance of MOS (Metal Oxide Semiconductor) tube

Abstract

The utility model provides a circuit structure and a chip used for measuring on resistance of an MOS tube. The circuit structure comprises the MOS tube, a first terminal, a second terminal, a third terminal and a fourth terminal. The MOS tube comprises a grid electrode, a drain electrode, a source electrode and a substrate electrode; the drain electrode is respectively connected with the first terminal and the second terminal; the source electrode is respectively connected with the third terminal and the fourth terminal; and the first wiring terminal, the second wiring terminal, the third wiring terminal, the fourth wiring terminal and the MOS tube in the conducting state are used for forming a Kelvin bridge circuit. According to the scheme, a principle similar to Kelvin resistance measurement is adopted, so that the influence of external introduced resistors such as contact resistance, resistance of measurement equipment and resistance of a lead in a measurement process on a measurement result can be reduced, and the accuracy of measuring the on resistance of the MOS tube is improved. When the on resistance of the MOS tube is small, the accuracy of the measurement result can be obviously improved by using the circuit structure provided by the utility model.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS tubes (Metal Oxide Semiconductor Field Effect Transistor), and in particular to a circuit structure and a chip for measuring the on-resistance of MOS tubes. Background Art

[0002] The on-resistance of a MOS tube is one of the important parameters of the MOS tube, which directly affects the performance of the MOS tube. It is necessary to accurately measure the on-resistance of the MOS tube. Figure 1 The circuit structure shown in the figure measures the on-resistance of the MOS tube of the device under test (DUT). The measurement method is as follows: Vdd is applied to the Gate terminal (i.e., the gate) to form a conduction channel; 0V is applied to the Source terminal (i.e., the source) and the Bulk terminal (i.e., the substrate) through the Source Pin (source probe); a lower voltage Vd (usually 0.1V) is applied to the Drain terminal (i.e., the drain) through the Drain Pin (drain probe) to ensure that it is in the linear region, and the current Id is measured at the Drain terminal; then the on-resistance R of the MOS tube is ds-DUT =Vd / Id.

[0003] When the on-resistance R ds-DUT When the value is large, the above circuit structure can be used to measure R more accurately. ds-DUT ; But when R ds-DUT When the resistance is small, the contact resistance introduced by the probe needle, the resistance of the measuring device and the resistance of the wire become non-negligible. ds-act =Vd / Id≈R ds-DUT +R contact-D +R contact-S , refer to Figure 2 The measured value R ds-act Between 118-125 (ohm), and the on-resistance of the MOS tube R ds-DUT Generally, it is between 10±10 (ohm), so the measured value R ds-act Much larger than the on-resistance R of the MOS tube ds-DUT , where R contact-D Represents the contact resistance introduced by the Drain end, R contact-S Represents the contact resistance introduced by the Source end. Utility Model Content

[0004] The utility model provides a circuit structure and a chip for measuring the on-resistance of a MOS tube, so as to solve the technical problem that when the on-resistance of the MOS tube is small, the measured value is greater than the on-resistance of the MOS tube.

[0005] In order to solve the above technical problems, the utility model provides a circuit structure for measuring the on-resistance of a MOS tube, comprising a MOS tube, a first terminal, a second terminal, a third terminal and a fourth terminal; the MOS tube comprises a gate, a drain, a source and a substrate; the drain is respectively connected to the first terminal and the second terminal; the source is respectively connected to the third terminal and the fourth terminal; the first terminal, the second terminal, the third terminal, the fourth terminal and the MOS tube in the on state are used to form a Kelvin bridge circuit.

[0006] Optionally, the MOS tube is an NMOS tube, the first terminal is connected to a first voltage source, the second terminal is connected to a first current source, the third terminal is connected to a ground terminal, the fourth terminal is connected to a second current source, the gate is connected to a second voltage source, and the substrate is connected to the ground terminal.

[0007] Optionally, the voltage output by the first voltage source is used to ensure that the NMOS is in a linear region, and its voltage value is 0.1V.

[0008] Optionally, the MOS tube is a PMOS tube, the first terminal is connected to a third voltage source, the second terminal is connected to a third current source, the third terminal is connected to a ground terminal, the fourth terminal is connected to a third current source, the gate is connected to a fourth voltage source, and the substrate is connected to the ground terminal.

[0009] Optionally, the voltage output by the third voltage source is used to ensure that the PMOS is in a linear region, and its voltage value is -0.1V.

[0010] The utility model also provides a chip for measuring the on-resistance of a MOS tube, comprising a MOS tube, a first terminal, a second terminal, a third terminal and a fourth terminal; the MOS tube comprises a gate, a drain, a source and a substrate; the chip comprises a substrate layer and a metal layer, the MOS tube is arranged on the substrate layer, the first terminal, the second terminal, the third terminal and the fourth terminal are all arranged on the metal layer; the drain is connected to the first terminal through a first terminal post and a first metal wire; the second terminal is connected to the first metal wire through a second metal wire; the source is connected to the third terminal through a third terminal post and a third metal wire; the fourth terminal is connected to the third metal wire through a fourth metal wire.

[0011] Optionally, the chip also includes a fifth terminal and a sixth terminal, the gate is connected to the fifth terminal via a fifth terminal post and a fifth metal wire, and the substrate is connected to the sixth terminal via a sixth terminal post and a sixth metal wire; the fifth terminal and the sixth terminal are both arranged on the metal layer.

[0012] The utility model provides a circuit structure and chip for measuring the on-resistance of a MOS tube. The circuit structure and chip adopt a principle similar to Kelvin resistance measurement, which can reduce the influence of external resistances such as contact resistance, resistance of measuring equipment and resistance of wire on the measurement result during the measurement process, and improve the accuracy of measuring the on-resistance of the MOS tube. An unexpected effect is that when the on-resistance of the MOS tube is small, the accuracy of the measurement result can be significantly improved by using the circuit structure provided by the utility model. When the on-resistance of the MOS tube is large, the measurement results of the circuit structure provided by the utility model and the circuit structure in the prior art are close. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a schematic diagram of a circuit structure for measuring the on-resistance of a MOS tube in the prior art.

[0014] Figure 2 yes Figure 1 The corresponding RV curve of a measurement result.

[0015] Figure 3 It is a schematic diagram of a circuit structure for measuring the on-resistance of a MOS tube provided by an embodiment of the utility model.

[0016] Figure 4 yes Figure 3 The corresponding layout diagram.

[0017] Figure 5 yes Figure 3 The corresponding RV curve of a measurement result.

[0018] [Description of reference numerals is as follows]:

[0019] The first terminal-1, the second terminal-2, the third terminal-3, the fourth terminal-4, the fifth terminal-5, the sixth terminal-6, the first terminal-7, the third terminal-8, the fifth terminal-9, the sixth terminal-10, the first metal wire-11, the second metal wire-12, the third metal wire-13, the fourth metal wire-14, the fifth metal wire-15, the sixth metal wire-16, the gate-G, the drain-D, the source-S, and the substrate-B. DETAILED DESCRIPTION

[0020] In order to make the purpose, advantages and features of the present invention clearer, the circuit structure and chip for measuring the on-resistance of a MOS tube proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0021] In the description of the present invention, the terms "first", "second", etc. are added for the convenience of description and reference, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined by the terms "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0022] like Figure 3 and Figure 4 As shown, this embodiment provides a circuit structure for measuring the on-resistance of a MOS tube, including a MOS tube, a first terminal 1, a second terminal 2, a third terminal 3 and a fourth terminal 4; the MOS tube includes a gate G, a drain D, a source S and a substrate B; the drain D is respectively connected to the first terminal 1 and the second terminal 2; the source S is respectively connected to the third terminal 3 and the fourth terminal 4; the first terminal 1, the second terminal 2, the third terminal 3, the fourth terminal 4 and the MOS tube in the on state are used to form a Kelvin bridge circuit. Figure 3 R contact-1 , R contact-2 , R contact-3 and R contact-4 The first terminal 1, the second terminal 2, the third terminal 3 and the fourth terminal 4 are sequentially represented by the contact resistance introduced when the probe is connected, and the contact resistance includes the device contact resistance, the resistance of the measuring device and the resistance of the wire, etc. Each terminal is usually called a pad (pad, pin).

[0023] Optional, such as Figure 3As shown, the MOS transistor is an NMOS transistor, the first terminal 1 is connected to the first voltage source, the second terminal 2 is connected to the first current source, the third terminal 3 is connected to the ground terminal, the fourth terminal 4 is connected to the second current source, the gate G is connected to the second voltage source, and the substrate B is connected to the ground terminal. The voltage output by the first voltage source can be adjusted according to the model of the NMOS transistor to ensure that the NMOS transistor is in the linear region. For example, the voltage output by the first voltage source can be 0.1V to 1.6V. The second voltage source is used to output the conduction voltage, which can be adjusted according to the model of the NMOS transistor, usually 3V to 20V, as long as the drain D and the source S can be conductive. The third terminal and the substrate are connected to the ground terminal respectively, so that the voltages of the third terminal and the substrate are both 0V. After the circuit structure is connected, the currents output by the first current source and the second current source are both 0A, and the voltage V of the second terminal 2 relative to the ground terminal is measured. Hi , the voltage V of the fourth terminal 4 relative to the ground terminal is measured Lo , the current I of the first terminal 1 is measured, then the on-resistance R of the NMOS tube ds =(V Hi –V Lo ) / I. The second terminal 2 and the fourth terminal 4 are connected to 0A, so that the second terminal 2 and the fourth terminal 4 have no shunting effect on the current I, thereby improving the accuracy of the measurement result. The principle is similar to the principle of Kelvin resistance measurement. The second terminal 2 and the fourth terminal 4 are connected to 0A to achieve the two ends of the MOS tube in the on state are between the ideal voltmeter, and the voltage difference between the second terminal 2 and the fourth terminal 4 is the reading of the ideal voltmeter. When using the circuit structure, a source meter (Source Measure Unit, SMU) can be used to provide the required voltage source and current source, and the source meter can be used to measure voltage and current.

[0024] Optional, such as Figure 3 As shown, the voltage output by the first voltage source is used to ensure that the NMOS is in the linear region, and its voltage value is 0.1 V. At present, the industry generally adopts the unified method of applying 0.1 V to the first terminal 1 to obtain the on-resistance of the NMOS tube, so the voltage output by the first voltage source is preferably 0.1 V. In other embodiments, the voltage value output by the first voltage source can be adjusted according to the model or design requirements of the NMOS tube.

[0025] When the on-resistance of the MOS tube is small, the circuit structure provided by the utility model can significantly improve the accuracy of the measurement result. Figure 2 and Figure 5 As shown, Figure 2 Is adopted Figure 1 According to the measurement results obtained from the circuit structure, the on-resistance R of the MOS tube is about 118Ω when the voltage output by the first voltage source is 0.1V; Figure 5 Is adopted Figure 3 The measurement results obtained from the circuit structure show that the on-resistance R of the MOS tube is about 14Ω when the voltage output by the first voltage source is 0.1V. Figure 2 The on-resistance R of the MOS tube obtained in Figure 5 The extra 104Ω is caused by the introduction of contact resistance, i.e. external resistance, during the measurement process, which leads to inaccurate measurement results.

[0026] Optional, reference Figure 3 As shown, the MOS tube is a PMOS tube, the first terminal 1 is connected to the third voltage source, the second terminal 2 is connected to the third current source, the third terminal 3 is connected to the ground terminal, the fourth terminal 4 is connected to the third current source, the gate G is connected to the fourth voltage source, and the substrate B is connected to the ground terminal. The voltage output by the third voltage source can be adjusted according to the model of the PMOS tube to ensure that the PMOS tube is in the linear region. For example, the voltage output by the third voltage source can be -0.1V to -1.6V. The fourth voltage source is used to output the conduction voltage, which can be adjusted according to the model of the PMOS tube, usually -3V to -20V, as long as the drain D and the source S can be conductive. The third terminal and the substrate are connected to the ground terminal respectively, so that the voltages of the third terminal and the substrate are both 0V. After the circuit structure is connected, the currents output by the third current source and the fourth current source are both 0A, and the voltage V of the fourth terminal 4 relative to the ground terminal is measured. Hi , the voltage V between the second terminal 2 and the ground terminal is measured Lo , the current I of the first terminal 1 is measured, then the on-resistance R of the PMOS tube ds =(V Hi –V Lo The second terminal 2 and the fourth terminal 4 are connected to 0A, so that the second terminal 2 and the fourth terminal 4 have no shunting effect on the current I, thereby improving the accuracy of the measurement result, and the principle is similar to the principle of Kelvin measurement of resistance.

[0027] Optional, reference Figure 3As shown, the voltage output by the third voltage source is used to ensure that the PMOS is in the linear region, and its voltage value is -0.1 V. At present, the industry generally adopts the unified application of -0.1 V to the first terminal 1 to obtain the on-resistance of the PMOS tube, so the voltage output by the third voltage source is preferably 0.1 V. In other embodiments, the voltage value output by the third voltage source can be adjusted according to the model or design requirements of the PMOS tube.

[0028] refer to Figure 3 and Figure 4 As shown, based on the same technical concept as the above-mentioned circuit structure for measuring the on-resistance of a MOS tube, this embodiment provides a chip for measuring the on-resistance of a MOS tube, including a MOS tube, a first terminal 1, a second terminal 2, a third terminal 3 and a fourth terminal 4; the MOS tube includes a gate G, a drain D, a source S and a substrate B; the chip includes a substrate layer and a metal layer, the MOS tube is arranged on the substrate layer, the first terminal 1, the second terminal 2, the third terminal 3 and the fourth terminal 4 are all arranged on the metal layer; the drain D is connected to the first terminal 1 through a first terminal 7 and a first metal wire 11; the second terminal 2 is connected to the first metal wire 11 through a second metal wire 12; the source S is connected to the third terminal 3 through a third terminal 8 and a third metal wire 13; the fourth terminal 4 is connected to the third metal wire 13 through a fourth metal wire 14. The shape of each terminal is usually a quadrangular prism or a cylinder. The connection point between the first metal wire 11 and the second metal wire 12 should be as close as possible to the first terminal 7, and the connection point between the third metal wire 13 and the fourth metal wire 14 should be as close as possible to the third terminal 8. In other embodiments, the first terminal 1, the second terminal 2, the third terminal 3 and the fourth terminal 4 can also be distributed in different layers of the chip.

[0029] The present embodiment provides a chip for measuring the on-resistance of a MOS tube. The chip is designed based on the current mainstream MOS layout, retains the gate, drain, source and substrate of the MOS tube, and then uses four terminals and the MOS tube in the on state to form a Kelvin bridge circuit. The overall structure is simple and compact. By adopting a principle similar to Kelvin resistance measurement, the influence of external resistances such as contact resistance, resistance of the measuring device and resistance of the wire on the measurement result can be reduced during the measurement process, thereby improving the accuracy of measuring the on-resistance of the MOS tube. An unexpected effect is that when the on-resistance of the MOS tube is small, the circuit structure provided by the utility model can significantly improve the accuracy of the measurement result.

[0030] Optional, such as Figure 4As shown, the chip further includes a fifth terminal 5 and a sixth terminal 6, the gate G is connected to the fifth terminal 5 through a fifth terminal 9 and a fifth metal wire 15, and the substrate B is connected to the sixth terminal 6 through a sixth terminal 10 and a sixth metal wire 16; the fifth terminal 5 and the sixth terminal 6 are both arranged on the metal layer. The fifth terminal 5 and the sixth terminal 6 are also arranged on the metal layer, which can facilitate circuit wiring when measuring the on-resistance of the MOS tube.

[0031] In summary, the utility model provides a circuit structure and chip for measuring the on-resistance of a MOS tube, which adopts a principle similar to Kelvin resistance measurement, and can reduce the influence of external resistances such as contact resistance, resistance of the measuring device and resistance of the wire on the measurement result during the measurement process, thereby improving the accuracy of measuring the on-resistance of the MOS tube. An unexpected effect is that when the on-resistance of the MOS tube is small, the accuracy of the measurement result can be significantly improved by using the circuit structure provided by the utility model. When the on-resistance of the MOS tube is large, the measurement results of the circuit structure provided by the utility model and the circuit structure in the prior art are close.

[0032] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation to the scope of the utility model. Any changes and modifications made by ordinary technicians in this field based on the above disclosure are within the protection scope of the utility model.

Claims

1. A circuit structure for measuring the on-resistance of a MOS tube, characterized in that: It comprises a MOS tube, a first terminal, a second terminal, a third terminal and a fourth terminal; the MOS tube comprises a gate, a drain, a source and a substrate; the drain is respectively connected to the first terminal and the second terminal; the source is respectively connected to the third terminal and the fourth terminal; the first terminal, the second terminal, the third terminal, the fourth terminal and the MOS tube in the on state are used to form a Kelvin bridge circuit.

2. A circuit structure for measuring the on-resistance of a MOS tube as claimed in claim 1, characterized in that: The MOS tube is an NMOS tube, the first terminal is connected to a first voltage source, the second terminal is connected to a first current source, the third terminal is connected to a ground terminal, the fourth terminal is connected to a second current source, the gate is connected to a second voltage source, and the substrate is connected to the ground terminal.

3. A circuit structure for measuring the on-resistance of a MOS tube as claimed in claim 2, characterized in that: The voltage output by the first voltage source is used to ensure that the NMOS is in a linear region, and the voltage value thereof is 0.1V.

4. A circuit structure for measuring the on-resistance of a MOS tube as claimed in claim 1, characterized in that: The MOS tube is a PMOS tube, the first terminal is connected to a third voltage source, the second terminal is connected to a third current source, the third terminal is connected to a ground terminal, the fourth terminal is connected to a third current source, the gate is connected to a fourth voltage source, and the substrate is connected to the ground terminal.

5. A circuit structure for measuring the on-resistance of a MOS tube as claimed in claim 4, characterized in that: The voltage output by the third voltage source is used to ensure that the PMOS is in a linear region, and the voltage value thereof is -0.1V.

6. A chip for measuring the on-resistance of a MOS tube, characterized in that: The invention comprises a MOS tube, a first terminal, a second terminal, a third terminal and a fourth terminal; the MOS tube comprises a gate, a drain, a source and a substrate; the chip comprises a substrate layer and a metal layer, the MOS tube is arranged on the substrate layer, the first terminal, the second terminal, the third terminal and the fourth terminal are all arranged on the metal layer; the drain is connected to the first terminal through a first terminal post and a first metal wire; the second terminal is connected to the first metal wire through a second metal wire; the source is connected to the third terminal through a third terminal post and a third metal wire; the fourth terminal is connected to the third metal wire through a fourth metal wire.

7. A chip for measuring the on-resistance of a MOS tube as claimed in claim 6, characterized in that: The chip also includes a fifth terminal and a sixth terminal, the gate is connected to the fifth terminal via a fifth terminal post and a fifth metal wire, and the substrate is connected to the sixth terminal via a sixth terminal post and a sixth metal wire; the fifth terminal and the sixth terminal are both arranged on the metal layer.

Images