Semiconductor device

Abstract

Some implementations described herein provide a semiconductor device including a layer of a silicon structure, a near-infrared photodiode within the layer of the silicon structure, a near-infrared light emitting diode within the layer of the silicon structure, and a deep trench isolation structure between the near-infrared photodiode and the near-infrared light emitting diode. A near-infrared photoelectric diode in a layer of a silicon structure includes a first epitaxial structure. The near infrared light emitting diode in the layer of the silicon structure includes a second epitaxial structure.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide semiconductor devices. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices use light-sensitive CMOS circuitry to convert light energy into electrical energy. The light-sensitive CMOS circuitry may include a photodiode formed in a silicon substrate. As the photodiode is exposed to light, an electric charge (called photocurrent) is induced in the photodiode. The photodiode may be coupled to a switching transistor that is used to sample the charge of the photodiode. Color may be determined by placing a filter above the light-sensitive CMOS circuitry. Utility Model Content

[0003] Some embodiments of the present disclosure provide a semiconductor device comprising: a layer of silicon structure; a near-infrared photodiode within the layer of silicon structure, comprising a first epitaxial structure; a near-infrared light-emitting diode within the layer of silicon structure, comprising a second epitaxial structure; and a deep trench isolation structure between the near-infrared photodiode and the near-infrared light-emitting diode.

[0004] Some embodiments of the present disclosure provide a semiconductor device comprising: a layer of a semiconductor structure; an array of multiple pixel structures, comprising: an array of multiple visible light photodiodes, within the layer of the semiconductor structure; and an array of multiple near-infrared photodiodes, comprising selectively grown epitaxial structures and interspersed in the array of these visible light photodiodes; multiple near-infrared light-emitting diodes, comprising selectively grown epitaxial structures, and the selectively grown epitaxial structures are dispersed near and along the periphery of the semiconductor device; and a sealing ring structure, between the near-infrared light-emitting diodes and the array of near-infrared photodiodes.

[0005] Some embodiments of the present disclosure provide a semiconductor device comprising: a layer of a semiconductor structure; a near-infrared photodiode within the layer of the semiconductor structure, comprising: a first selectively grown epitaxial structure; a visible light photodiode adjacent to the near-infrared photodiode; a near-infrared light-emitting diode within the layer of the semiconductor structure, comprising: a second selectively grown epitaxial structure; and a deep trench isolation structure between the near-infrared photodiode and the near-infrared light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are as follows: Figure 1The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a schematic diagram of a portion of an example optoelectronic device described herein;

[0009] Figure 3 is a schematic diagram of an example optoelectronic device described herein;

[0010] FIG. 4A to FIG. 4N is a schematic diagram of an example implementation for forming an optoelectronic device including a near-infrared photodiode and a near-infrared light-emitting diode;

[0011] Figure 5 A schematic diagram of an example implementation described herein;

[0012] Figure 6 For the purposes of this article Figure 1 schematic diagrams of example components of one or more devices;

[0013] Figure 7 is a flow chart of an example process associated with forming an optoelectronic device including a near-infrared photodiode and a near-infrared light emitting diode.

[0014]

Explanation of symbols

[0015] 100: Environment

[0016] 102:Semiconductor processing tools / deposition tools

[0017] 104:Semiconductor processing tools / exposure tools

[0018] 106:Semiconductor processing tools / development tools

[0019] 108:Semiconductor processing tools / etching tools

[0020] 110:Semiconductor processing tools / planarization tools

[0021] 112:Semiconductor processing tools / electroplating tools

[0022] 114:Semiconductor processing tools / ion implantation tools

[0023] 116:Semiconductor processing tools / bonding tools / debonding tools

[0024] 118: Wafer / die transfer tool

[0025] 200: Optoelectronic device / pixel array

[0026] 202: Pixel sensor array

[0027] 204a, 204b, 204c, 204d: pixel sensors

[0028] 206: Sealing ring structure

[0029] 208: Surrounding area

[0030] 210: Light Emitting Diode (LED) Device

[0031] 300: Optoelectronic devices

[0032] 302: buffer layer

[0033] 304: Dielectric region

[0034] 306: Interconnection structure

[0035] 308: Metallization layer

[0036] 310: Source / drain region

[0037] 312: substrate layer

[0038] 314: Photodiode

[0039] 316: Photodiode

[0040] 318: Light Emitting Diode (LED)

[0041] 320: Gate structure

[0042] 322: Shallow Trench Isolation (STI) Region

[0043] 324: Oxide layer

[0044] 326: Deep Trench Isolation (DTI) Structure

[0045] 328:HA District

[0046] 330: Backside illumination (BSI) oxide layer

[0047] 332: Buffer oxide layer

[0048] 334:Joint pad

[0049] 336: Filter layer

[0050] 338: Microlens layer

[0051] 400: Implementation

[0052] 402: Carrier structure

[0053] 404: Obscuration

[0054] 406, 408, 410, 412, 414: Cavity

[0055] 500: Implementation

[0056] 502: Layer stacking of epitaxial structure

[0057] 502a: n-type layer

[0058] 502b: Essence layer

[0059] 502c: p-type layer

[0060] 600: Device

[0061] 610: Bus

[0062] 620: Processor

[0063] 630: Memory

[0064] 640: Input component

[0065] 650: Output component

[0066] 660: Communication Components

[0067] 700: Craftsmanship

[0068] 710, 720, 730, 740, 750: Blocks

[0069] D1, D2: thickness DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0071] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0072] In some cases, an image detection system in a low-light environment may include a combination of discrete optoelectronic devices. For example, the image detection system may include a discrete near infrared (NIR) light emitting diode (LED) device for projecting NIR (near infrared, NIR) light waves onto a target (e.g., a target for reflecting an image), a discrete NIR pixel sensor device for detecting NIR light waves reflected from the target, and a discrete visible light (VIS) pixel sensor device for detecting visible light waves reflected from the target. In addition to the disadvantages associated with discrete devices consuming space within the system, the silicon-based photodiodes of the NIR pixel sensor devices may have low quantum efficiency (QE) performance.

[0073] Optoelectronic devices may include structures using epitaxially grown type III or type V materials (e.g., type III or type V periodic elements). Type III and type V materials are considered "wide bandgap materials" and have a higher energy gap than traditional semiconductor materials. This property enables type III and type V materials to absorb photons with higher energy, including photons in the infrared region of the spectrum, and therefore, can significantly improve the quantum efficiency of photodiodes. In addition, type III and type V materials have lower defect densities, which reduces noise levels and improves the signal-to-noise ratio of photodiodes. The use of type III or type V materials in photodiodes can lead to better detection of light, especially for applications that require high sensitivity in low light conditions. The improved quantum efficiency of these photodiodes is beneficial in fields such as medical imaging, remote sensing, and communication technology, where reliable and accurate light detection is critical.

[0074] Some implementations described herein include optoelectronic devices for low-light applications and techniques for forming optoelectronic devices. The optoelectronic devices include NIR LEDs, NIR photodiodes, and VIS photodiodes combined in a single substrate. The NIR LEDs and NIR photodiodes are formed using selectively grown epitaxial structures. The selectively grown epitaxial structures (e.g., silicon germanium (SiGe), gallium arsenide (GaAs), or another III / V type material) improve the QE performance of the NIR photodiode relative to another photodiode formed via a doped silicon structure.

[0075] By combining NIR LEDs, NIR photodiodes, and VIS photodiodes on a single substrate, the complexity and / or number of manufacturing operations to form an image detection system is smaller than the complexity and / or number of manufacturing operations to form another image detection system using discrete NIR LED devices, NIR photodiode devices, and VIS photodiode devices.

[0076] In this manner, the performance (e.g., QE) of a NIR pixel sensor device including a NIR photodiode is improved relative to another NIR pixel sensing device including a doped, organic photodiode. Improving the performance of the NIR pixel sensor device improves the manufacturing yield of the NIR pixel sensing device to a particular performance threshold. Additionally, combining the NIR LED, NIR photodiode, and VIS photodiode on a single substrate consumes less overall device space (e.g., silicon) and / or image detection system space. By increasing manufacturing yield and consuming less device space and / or image detection system space, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems (including NIR LEDs, NIR photodiodes, and VIS photodiodes) is reduced.

[0077] Figure 1 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in the example environment 100, the environment 100 may include a plurality of semiconductor processing tools 102 to 116 and a wafer / die transfer tool 118. The plurality of semiconductor processing tools 102 to 116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, a bonding / debonding tool 116, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor cleaning chamber, a semiconductor wafer fab, a semiconductor processing facility, and / or a manufacturing facility, among other examples.

[0078] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials on a substrate. In some implementations, the deposition tool 102 includes a spin-on coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool 102 includes a physical vapor deposition (PVD) tool such as a sputtering tool or another type of PVD tool. In some implementations, the example environment 100 includes multiple types of deposition tools 102 .

[0079] The exposure tool 104 is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures in a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0080] The developing tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some implementations, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some implementations, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0081] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some implementations, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some implementations, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0082] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 can grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive grinding). The planarization tool 110 can utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device can be pressed together via a dynamic polishing head and held in place via a retaining ring. The dynamic polishing head can rotate at different rotation axes to remove material and even out any irregular topography of the semiconductor device so that the semiconductor device is flat or planar.

[0083] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0084] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a resource material such as a gas or a solid in an arc chamber. The resource material can be provided into the arc chamber, and an arc voltage is released between a cathode and an electrode to generate a plasma containing ions of the resource material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate so that the ions are implanted below the surface of the substrate.

[0085] The bonding / debonding tool 116 is a semiconductor processing tool capable of connecting two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, the bonding / debonding tool 116 may include a eutectic bonding tool capable of forming a eutectic bond between two or more wafers. In these examples, the bonding / debonding tool 116 may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers. As another example, the bonding / debonding tool 116 may include a hybrid bonding tool, a direct bonding tool, and / or another type of bonding tool. In some implementations, the bonding / debonding tool 116 may heat the two or more wafers to separate the two or more wafers.

[0086] The wafer / die transfer tool 118 may be included in a cluster tool or another type of tool that includes multiple processing chambers and may be used to transfer substrates and / or semiconductor devices between multiple processing chambers, between a processing chamber and a buffer, between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or between a processing chamber and a transfer carrier (e.g., a front opening unified pod (FOUP)), among other things. In some implementations, the wafer / die transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition chambers (e.g., chambers for depositing different types of materials, chambers for performing different types of deposition operations).

[0087] One or more of the semiconductor processing tools 102 to the semiconductor processing tools 116 and / or the wafer / die transfer tool 118 may perform a series of one or more semiconductor processing operations described herein. In some implementations, and as an example, the series of one or more semiconductor processing operations includes forming a layer of a semiconductor structure on a dielectric region of a semiconductor device. The series of one or more semiconductor processing operations includes forming a first cavity in the layer of the semiconductor structure. The series of one or more semiconductor processing operations includes forming a second cavity in the layer of the semiconductor structure adjacent to the first cavity. The series of one or more semiconductor processing operations includes forming a near-infrared light emitting diode in the first cavity by selectively growing a first epitaxial structure in the first cavity. The series of one or more semiconductor processing operations includes forming a near-infrared photodiode in the second cavity by selectively growing a second epitaxial structure in the second cavity. In some implementations, the one or more semiconductor processing operations performed by the semiconductor processing tools 102 to the semiconductor processing tools 116 and / or the wafer / die transfer tool 118 may correspond to a combination of FIG. 4A to FIG. 4N and one or more semiconductor processing operations described elsewhere herein, among other examples.

[0088] Figure 1 The number and configuration of devices shown in the figure are provided as one or more examples. Figure 1 There may be additional devices, fewer devices, different devices, or differently configured devices than those shown in . Figure 1 Two or more of the devices shown in may be implemented in a single device, or Figure 1 The single device shown in the example environment 100 may be implemented as multiple, distributed devices. Additionally or alternatively, a set of devices (eg, one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0089] Figure 2 Schematic diagram of a portion of an example optoelectronic device 200 described herein. The optoelectronic device 200 may be deployed in a variety of implementations, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of low-light implementations.

[0090] like Figure 2 As shown in the top view of FIG. 2 , the optoelectronic device 200 includes a pixel sensor array 202. Figure 2 As shown in , the pixel sensor array 202 may include pixel sensors 204a to 204d. Figure 2 As further shown in FIG. 1 , the pixel sensors 204 a to 204 d are arranged in a grid. In some implementations, the pixel sensors 204 a to 204 d are square (eg, Figure 2). In some implementations, the pixel sensors 204a to 204d include other shapes, such as a circular shape, an octagonal shape, a diamond shape, and / or other shapes.

[0091] The pixel sensor array 202 may include a filter array that enables the pixel sensors 204a to 204d to sense and / or accumulate incident light of a particular wavelength (e.g., to direct light toward the pixel sensor array 202). For example, the pixel sensor 204a may include a color filter that limits the pixel sensor 204a to absorb and accumulate photons of incident light corresponding to blue visible light (e.g., electromagnetic waves having a wavelength in the range of about 450 nanometers to about 490 nanometers). Additionally or alternatively, the pixel sensor 204b may include a color filter that limits the pixel sensor 204b to absorb and accumulate photons of incident light corresponding to green visible light (e.g., electromagnetic waves having a wavelength in the range of about 490 nanometers to about 570 nanometers). Additionally or alternatively, the pixel sensor 204c may include a color filter that limits the pixel sensor 204c to absorb and accumulate photons of incident light corresponding to red visible light (e.g., electromagnetic waves having a wavelength in the range of about 620 nanometers to about 750 nanometers). Additionally or alternatively, the pixel sensor 204d may include a filter that limits the pixel sensor 204d to absorb and accumulate photons of incident light corresponding to NIR light (e.g., electromagnetic waves having a wavelength in the range of about 700 nanometers to about 2500 nanometers). The photodiode of each pixel sensor 204a to 204d in the pixel sensor array 202 may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a higher intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0092] like Figure 2 As further shown in FIG. 1 , the optoelectronic device 200 includes a seal ring structure 206 surrounding the pixel sensor array 202 and a peripheral region 208 including one or more LED devices 210 (e.g., NIR LED devices). The seal ring structure 206 can provide a physical barrier that substantially eliminates moisture and / or crack penetration into the optoelectronic device 200. In addition, if combined with Figure 3 As described in greater detail elsewhere herein, the seal ring structure 206 may include a combination of interconnect structures, metallization layers, and / or deep trench isolation structures that prevent NIR light from being transmitted directly from the LED device 210 to one or more photodiodes in the pixel sensors 204a to 204d.

[0093] As mentioned above, Figure 2 are provided as examples. Other examples may differ from those described in Figure 2 As described.

[0094] Figure 3 is a schematic diagram of an example optoelectronic device 300 described herein. Figure 3 As shown in (e.g., a cross-sectional view), optoelectronic device 300 may include pixel sensor 204c and pixel sensor 204d, seal ring structure 206, and LED device 210. Optoelectronic device 300 may be deployed in various implementations, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light sensing implementations.

[0095] like Figure 3 As further shown in FIG. 1 , the optoelectronic device 300 may include various layers and / or structures. In some implementations, the optoelectronic device 300 may be mounted and / or fabricated on a carrier substrate (not shown) during one or more semiconductor processing operations to form the optoelectronic device 300. Figure 3 As shown in FIG. 3 , the optoelectronic device 300 may include a buffer layer 302. The buffer layer 302 may include a dielectric material such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, and / or another dielectric material. The buffer layer 302 can be used as a layer through which the optoelectronic device 300 is bonded to a carrier substrate so that backside processing can be performed on the optoelectronic device 300.

[0096] like Figure 3 As further shown in FIG. 1 , the optoelectronic device 300 may include a dielectric region 304 on and / or above the buffer layer 302. The dielectric region 304 (eg, an intermetallic dielectric region) may include a dielectric material (eg, silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), fluoro-silicate glass (FSG), carbon-doped silicon oxide, and / or one or more layers of another dielectric material). Various interconnect structures 306 (e.g., vertical interconnect access structures, or vias) and metallization layers 308 may be formed in and / or between the layers of the dielectric region 304. The metallization layers 308 may include bonding pads, conductive wires, and / or other types of conductive structures that electrically connect various regions of the optoelectronic device 300 and / or electrically connect various regions of the optoelectronic device 300 to one or more external devices and / or external packages. The interconnect structures 306 and the metallization layers 308 may be referred to as a BEOL (Back End of Line) metallization stack and may include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof, as well as other examples.

[0097] In some implementations, portions of transistor circuitry can be included in dielectric region 304. For example, one or more source / drain regions 310 (eg, doped semiconductor material such as silicon (Si) or silicon germanium (SiGe)) can be included in dielectric region 304.

[0098] The optoelectronic device 300 may further include a substrate layer 312. The substrate layer 312 may include a semiconductor material such as silicon, a III-V compound such as gallium arsenide (GaAs), a silicon on insulator (SOI) layer, and / or another type of substrate capable of generating charges from photons of incident light.

[0099] The photodiodes for pixel array 200 are included in substrate layer 312. Photodiode 314 for sensing visible light may include a region of substrate layer 312 doped with multiple types of ions to form a pn junction or a pin junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, substrate layer 312 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 314 and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 314.

[0100] In addition, the substrate layer 312 may include a photodiode 316 for sensing NIR light and an LED 318 for emitting NIR light. The photodiode 316 and the LED 318 may include materials of type III periodic elements or type V periodic elements. Based on the properties of the material (e.g., type III periodic elements or type V periodic elements), the photodiode 316 may absorb photons with higher energy, including photons in the infrared region of the spectrum, to significantly improve the quantum efficiency of the photodiode 316 relative to the photodiode 314. Examples of materials that can be epitaxially grown within the cavity in the substrate layer 312 to selectively form the photodiode 316 and / or the LED 318 include germanium materials (Ge), silicon germanium materials (SiGe), gallium arsenide materials (GaAs), and indium phosphide materials (InP).

[0101] In some implementations, the substrate layer 312 may further include portions of transistor circuitry. For example, the substrate layer 312 may include a gate structure 320. The gate structure 320 formed between the source / drain regions 310 may include a conductive material such as a polysilicon structure, among other examples. In some implementations, the transistor formed by the source / drain regions 310 and the gate structure 320 may be associated with a photodiode (e.g., photodiode 314, photodiode 316) or an LED (e.g., LED 318). Additionally, in some implementations, a shallow trench isolation (STI) region 322 is above the dielectric region 304. The STI region 322 may electrically isolate the pixel sensor 204 (204a-204d) from other regions of the optoelectronic device 300.

[0102] like Figure 3 As shown in FIG. 1 , an oxide layer 324 is located on the substrate layer 312. The oxide layer 324 can be used as a passivation layer between the substrate layer 312 and the upper layers of the pixel sensors 204 (204a to 204d). In some implementations, the oxide layer 324 includes a silicon oxide (SiO x In some implementations, silicon nitride (SiN x ), Silicon Carbide (SiC x ), or a mixture thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another dielectric material to replace the oxide layer 324 as a passivation layer.

[0103] The oxide layer 324 may fill a deep trench isolation (DTI) structure 326, which is included in the substrate layer 312. In detail, the DTI structure 326 may be formed between each of the photodiodes 314 and 316. The DTI structure 326 may be formed in a grid layout, where the DTI structure 326 extends laterally across the pixel array 200 and intersects at various locations of the pixel array 200. The DTI structure 326 may include a trench (e.g., a deep trench) that extends down into the substrate layer 312 adjacent to the photodiodes 314 and 316. The DTI structure 326 may provide optical isolation between the pixel sensors 204 (204a to 204d) of the pixel array 200, thereby reducing the amount of optical crosstalk between adjacent pixel sensors 204 (204a to 204d). In particular, the DTI structure 326 can absorb, refract, and / or reflect incident light, which can reduce the amount of incident light that travels through the pixel sensor 204 (204a-204d) into the adjacent pixel sensor 204 (204a-204d) and is absorbed by the adjacent pixel sensor 204 (204a-204d). In some implementations, the DTI structure 326 is included as part of the seal ring structure 206 to prevent NIR light from the LED 318 from entering the photodiode 314 and / or 316.

[0104] One or more HA regions 328 may be located above one or more photodiodes 314 and / or 316. Each HA region 328 may be defined by a shallow trench. Multiple adjacent HA regions 328 may form a periodic structure or a zigzag structure in the substrate layer 312 and / or the photodiodes 314 and / or 316. One or more HA regions 328 may be formed in the same side of the substrate layer 312 as the DTI structure 326.

[0105] The HA region 328 can increase the absorption of incident light by the pixel sensor 204 (204a-204d) by modifying or changing the orientation of the refractive interface between the photodiodes 314 and 316 and the substrate layer 312 (thereby improving the quantum efficiency of the pixel sensor array 202). The slanted walls of the HA region 328 change the orientation of the interface between the photodiodes 314 and 316 and the substrate layer 312 by making the interface diagonal relative to the orientation of the top surface of the substrate layer 312. For the same incident angle of the incident light, this change in orientation can result in a smaller refraction angle relative to the flat surface of the top surface of the substrate layer 312. As a result, the HA region 328 is able to direct incident light at a wider angle toward the center of the photodiodes 314 and 316 than if the HA region 328 was not included in the optoelectronic device 300.

[0106] In some implementations, the top surface of substrate layer 312, the surface of DTI structure 326, and the surface of HA region 328 may be coated with an antireflective coating (ARC) layer to reduce the reflection of incident light from photodiode 314 and photodiode 316, thereby increasing the transmission of incident light into substrate layer 312 and photodiode 314, photodiode 316.

[0107] like Figure 3 As further shown in FIG. 1 , one or more passivation layers may be formed on the oxide layer 324. For example, a backside illumination (BSI) oxide layer 330 may be disposed on the oxide layer 324. As another example, a buffer oxide layer 332 may be disposed on the BSI oxide layer 330. In some implementations, the BSI oxide layer 330 and / or the buffer oxide layer 332 may include, for example, silicon oxide (SiO x In some implementations, silicon nitride (SiN x ), Silicon Carbide (SiC x ), or a mixture thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another dielectric material to replace the BSI oxide layer 330 and / or the buffer oxide layer 332 as a passivation layer.

[0108] The bonding pad 334 may be located on the STI region 322 and / or on the buffer oxide layer 332. The bonding pad 334 may pass through the buffer oxide layer 332, through the STI region 322, and extend to the dielectric region 304, and may contact one or more metallization layers 308 in the dielectric region 304. The bonding pad 334 may include a conductive material such as gold, silver, aluminum, copper, aluminum copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, a metal alloy, other metals, or a combination thereof. The bonding pad 334 may provide an electrical connection between the metallization layer 308 of the optoelectronic device 300 and an external device and / or external package.

[0109] A filter layer 336 (e.g., corresponding to a portion of a color filter array or a near infrared filter array) may be included on the buffer oxide layer 332 for one or more pixel sensors 204 (204a to 204d). The filter layer 336 may include one or more visible light color filter regions for filtering visible light of a particular wavelength or wavelength range (e.g., allowing visible light of a particular wavelength or wavelength range to pass through the filter layer 336); one or more near infrared (NIR) filter regions (e.g., NIR bandpass filter regions) for allowing wavelengths associated with NIR light to pass through the filter layer 336 and blocking light of other wavelengths; one or more NIR cutoff filter regions for blocking NIR light from passing through the filter layer 336; and / or other types of filter regions. In some implementations, one or more pixel sensors 204 (204a to 204d) are each configured with a filter region of the filter layer 336. In some implementations, a microlens layer 338 is included on the filter layer 336. The microlens layer 338 may include a plurality of microlenses. In detail, the microlens layer 338 may include individual microlenses for each of the pixel sensors 204 ( 204 a to 204 d ) included in the pixel array 200 .

[0110] Figure 3 The number and configuration of components, structures, and / or layers shown in optoelectronic device 300 are provided as examples. In practice, optoelectronic device 300 may include additional components, structures, and / or layers; fewer components, structures, and / or layers; different components, structures, and / or layers; and / or Figure 3 Components, structures, and / or layers in different configurations as shown.

[0111] As combined Figure 2 and Figure 3 As described, in an example implementation, a semiconductor device (e.g., optoelectronic device 300) includes a layer of semiconductor structure (e.g., substrate layer 312). The semiconductor device includes a near-infrared photodiode (e.g., photodiode 316) in a layer of silicon structure including a first epitaxial structure. The semiconductor device includes a near-infrared light-emitting diode (e.g., LED 318) in a layer of silicon structure including a second epitaxial structure. The semiconductor device includes a deep trench isolation structure (e.g., DTI structure 326) between the near-infrared photodiode and the near-infrared light-emitting diode.

[0112] In another example implementation, a semiconductor device (e.g., optoelectronic device 300) includes a layer of semiconductor structure (e.g., substrate layer 312). The semiconductor device includes an array of pixel structures (e.g., pixel sensor array 202 including pixel sensors 204 (204a-204d)), which includes an array of visible light photodiodes (e.g., photodiode 314) and an array of near infrared photodiodes (e.g., photodiode 316) within the layer of semiconductor structure, the near infrared photodiodes including selectively grown epitaxial structures and interspersed in the array of visible light photodiodes. The semiconductor device includes a plurality of near infrared light emitting diodes (e.g., LED 318) including selectively grown epitaxial structures and dispersed near and along a periphery of the semiconductor device (e.g., periphery region 208). The semiconductor device includes a seal ring structure (e.g., seal ring structure 206) between the plurality of near infrared light emitting diodes and the array of near infrared photodiodes.

[0113] A semiconductor device (e.g., optoelectronic device 300) includes a NIR LED (e.g., LED 318), a NIR photodiode (e.g., photodiode 316), and a VIS photodiode (e.g., photodiode 314) combined in a single substrate (e.g., substrate layer 312). The NIR LED and the NIR photodiode are formed using a selectively grown epitaxial structure. The selectively grown epitaxial structure (e.g., silicon germanium (SiGe), gallium arsenide (GaAs), or another III / V type material) improves the QE performance of the NIR photodiode relative to other NIR photodiodes that can be formed via doped silicon structures.

[0114] By combining NIR LEDs, NIR photodiodes, and VIS photodiodes on a single substrate, the complexity and / or number of manufacturing operations to form an image detection system is smaller than the complexity and / or number of manufacturing operations to form another image detection system using discrete NIR LED devices, NIR photodiode devices, and VIS photodiode devices.

[0115] In this manner, the performance (e.g., QE) of a NIR pixel sensor device including a NIR photodiode is improved relative to another NIR pixel sensing device including a doped, organic photodiode. Improving the performance of the NIR pixel sensor device improves the manufacturing yield of the NIR pixel sensing device to a particular performance threshold. Additionally, combining the NIR LED, NIR photodiode, and VIS photodiode on a single substrate consumes less overall device space (e.g., silicon) and / or image detection system space. By improving manufacturing yield and consuming less device space and / or image detection system space, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems (including NIR LED devices, NIR pixel sensor devices, and VIS photodiodes) is reduced.

[0116] FIG. 4A to FIG. 4N Schematic diagram of an example implementation 400 for forming an optoelectronic device including a near-infrared photodiode and a near-infrared light-emitting diode. As part of implementation 400, Figure 1 One or more of the semiconductor processing tool 102 to the semiconductor processing tool 116 and / or the wafer / die transfer tool 118 perform a series of operations.

[0117] like Figure 4A As shown in FIG. 4 , a carrier structure 402 (a glass carrier structure or a silicon carrier structure, among other examples) holds the substrate layer 312. The deposition tool 102 can be used in PVD operations, ALD operations, CVD operations, epitaxy operations, oxidation operations, bonding operations, etc. Figure 1 The substrate layer 312 is deposited in another type of deposition operation, and / or another suitable deposition operation. In some implementations, the planarization tool 110 planarizes the substrate layer 312 after the deposition tool 102 deposits the substrate layer 312 .

[0118] To accommodate the formation of photodiodes (eg, photodiodes 314 and / or 316) and / or LEDs (eg, LED 318), substrate layer 312 may include a thickness D1 of about 2.25 microns to about 2.75 microns. However, other values ​​and ranges of thickness D1 are within the scope of the present disclosure.

[0119] As part of a series of operations, STI regions 322 are formed in substrate layer 312. As an example, deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 may perform a combination of photolithography, etching, and deposition operations to form STI regions 322 in substrate layer 312.

[0120] like Figure 4BAs shown in FIG. 1 , as part of a series of operations, a masking layer 404 is formed and patterned over the substrate layer 312. For example, as part of forming the masking layer 404, the deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The planarization tool 110 may planarize the masking layer 404 after the masking layer 404 is deposited by the deposition tool 102. In addition, as part of patterning the masking layer 404, the exposure tool 104, the development tool 106, and / or the etching tool 108 may perform a combination of optical lithography and etching operations to form a pattern.

[0121] like Figure 4B As further shown in FIG. 1 , a cavity 406 (e.g., a cavity for photodiode 316) and a cavity 408 (e.g., a cavity for LED 318) are formed in substrate layer 312. To form cavity 406 and cavity 408, a pattern in masking layer 404 is used. Etching tool 108 etches substrate layer 312 based on the pattern to form cavities 406 and 408 in substrate layer 312. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique).

[0122] Go to Figure 4C , photodiode 316 and LED 318 are formed in cavities 406 and 408, respectively. Deposition tool 102 can be used in epitaxy operations (e.g., selective epitaxial growth operations), combined Figure 1 The photodiode 316 and the LED 318 are deposited in the deposition operation described above, and / or in another suitable deposition operation. In some implementations, after the deposition tool 102 deposits the photodiode 316 and the LED 318, the planarization tool 110 planarizes the photodiode 316 and the LED 318. Additionally or alternatively, after the deposition tool 102 deposits the photodiode 316 and the LED 318, the planarization tool 110 can remove the masking layer 404.

[0123] In some implementations, the thickness D2 of the LED 318 and / or the photodiode 316 (eg, the thickness of the selectively grown epitaxial structure) is included in the range of about 1.8 microns to about 2.2 microns. However, other values ​​and ranges of thickness D2 are within the scope of the present disclosure.

[0124] like Figure 4DAs shown in , as part of a series of operations, a photodiode 314 is formed in a substrate layer 312. For example, the deposition tool 102, the exposure tool 104, the development tool 106, the etching tool 108, and / or the ion implantation tool 114 may perform a combination of deposition, photolithography, etching, and / or implantation operations to implant ions in a defined region below the surface of the substrate to form the photodiode 314.

[0125] In addition, if Figure 4D As shown in , gate structure 320 can be formed in substrate layer 312. For example, deposition tool 102, exposure tool 104, development tool 106, etching tool 108, and / or ion implantation tool 114 can perform a combination of deposition, photolithography, etching, and / or implantation operations to form gate structure 320.

[0126] like Figure 4E As shown in FIG. 1 , dielectric region 304 is formed on and / or over substrate layer 312. As part of forming dielectric region 304, and as an example, deposition tool 102 may use a CVD operation, a PVD operation, an ALD operation, a combination of the above, or a combination of the above. Figure 1 The other deposition operation, and / or another suitable deposition operation, deposits one or more dielectric layers 304 of the dielectric region. In some implementations, after the deposition tool 102 deposits the dielectric layers, the planarization tool 110 planarizes one or more of the dielectric layers.

[0127] Additionally or alternatively, as part of forming the dielectric region 304, the deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108 may perform a combination of deposition, photolithography, and / or etching operations to form the interconnect structure 306. The deposition tool 102 or the electroplating tool 112 may further form one or more of the metallization layers 308. To form one or more of the metallization layers 308, the deposition tool 102 and / or the electroplating tool 112 may be in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, a combination of the above, or a combination of the above. Figure 1 One or more of the metallization layers 308 are deposited in another deposition operation, and / or another suitable deposition operation. In some implementations, the planarization tool 110 planarizes one or more of the metallization layers 308 after deposition.

[0128] like Figure 4F As shown in FIG. 1 , the bonding / debonding tool 116 may remove the carrier structure 402 (eg, separate the carrier structure 402 from the substrate layer 312) as part of a sequence of operations. Figure 4F As shown in FIG. 1 , buffer layer 302 is formed above and / or on dielectric region 304. Deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The buffer layer 302 is deposited in another type of deposition operation, and / or another suitable deposition operation. In some implementations, the planarization tool 110 planarizes the buffer layer 302 after the deposition tool 102 deposits the buffer layer 302 .

[0129] Go to Figure 4G As part of a series of operations, the etching tool 108 can form a cavity 408 (e.g., a cavity for the DTI structure 326) and a cavity 410 (e.g., a cavity for the HA region 328). In some implementations, the pattern in the photoresist layer is used to etch the substrate layer 312 to form the cavities 408 and 410. In these implementations, the deposition tool 102 forms a photoresist layer on the substrate layer 312. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops the photoresist layer and removes a portion thereof to expose the pattern. The etching tool 108 etches the substrate layer 312 based on the pattern to form the cavities 408 and 410 in the substrate layer 312. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the substrate layer 312 .

[0130] like Figure 4H As shown in FIG. 1 , an oxide layer 324 is formed on the substrate layer 312. The deposition tool 102 can be used in a PVD operation, an ALD operation, a CVD operation, an epitaxy operation, an oxidation operation, a combination of Figure 1 The oxide layer 324 is deposited in another type of deposition operation, and / or another suitable deposition operation as described above. In some implementations, after the deposition tool 102 deposits the oxide layer 324, the planarization tool 110 planarizes the oxide layer 324. As part of forming the oxide layer 324, the cavities 408 and cavities 410 may be filled with oxide to form the DTI structure 326 and the HA region 328. In some implementations, the deposition tool 102 deposits an antireflective coating (ARC) layer before depositing the oxide layer 324.

[0131] like Fig. 4I As shown in FIG. 1 , a BSI oxide layer 330 is formed over the oxide layer 324. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1The BSI oxide layer 330 is deposited in another type of deposition operation, and / or another suitable deposition operation. In some implementations, the planarization tool 110 planarizes the BSI oxide layer 330 after the deposition tool 102 deposits the BSI oxide layer 330 .

[0132] Go to Figure 4J , as part of a series of operations, a cavity 412 is formed through the BSI oxide layer 330, the oxide layer 324, and the substrate layer 312 to the STI region 322. In some implementations, the pattern in the photoresist layer is used to etch the BSI oxide layer 330, the oxide layer 324, and the substrate layer 312 to form the cavity 412. In these implementations, the deposition tool 102 forms a photoresist layer on the substrate layer 312. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops the photoresist layer and removes a portion thereof to expose the pattern. The etching tool 108 etches the cavity 412 based on the pattern to form the cavity 412 in the BSI oxide layer 330, the oxide layer 324, and the substrate layer 312. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, the photoresist removal tool removes the remaining portion of the photoresist layer (eg, using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the BSI oxide layer 330, oxide layer 324, and substrate layer 312.

[0133] like Figure 4K As shown in FIG. 1 , a buffer oxide layer 332 is formed above and / or on the BSI oxide layer 330. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The buffer oxide layer 332 is deposited in another type of deposition operation, and / or another suitable deposition operation. In some implementations, the planarization tool 110 planarizes the buffer oxide layer 332 after the deposition tool 102 deposits the buffer oxide layer 332 .

[0134] like Figure 4L, a cavity 414 is formed through the buffer oxide layer 332, through the STI region 322, and into the dielectric region 304. In some implementations, the cavity 414 exposes a portion of the metallization layer 308. In some implementations, the pattern in the photoresist layer is used to etch the buffer oxide layer 332, the STI region 322, and the dielectric region 304 to form the cavity 414. In these implementations, the deposition tool 102 forms a photoresist layer on the buffer oxide layer 332. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops the photoresist layer and removes a portion thereof to expose the pattern. The etching tool 108 etches the buffer oxide layer 332, the STI region 322, and the dielectric region 304 based on the pattern to form a cavity 414 through the buffer oxide layer 332, through the STI region 322, and into the dielectric region 304. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based etching of the buffer oxide layer 332, the STI regions 322, and the dielectric regions 304.

[0135] As part of a series of operations, such as Figure 4M , the bonding pad 334 is formed in the cavity 414. In some implementations, a portion of the bonding pad 334 is formed on a portion of the metallization layer 308. As an example, the deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108 can perform a combination of deposition, photolithography, and / or etching operations to form the bonding pad 334.

[0136] Go to Figure 4N As part of a series of operations, filter layer 336 and microlens layer 338 are formed above and / or on buffer oxide layer 332. As an example, deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 may perform a combination of deposition, optical lithography, and / or etching operations to form filter layer 336 and microlens layer 338.

[0137] As mentioned above, FIG. 4A to FIG. 4N are provided as examples. Other examples may differ from those described in FIG. 4A to FIG. 4N described.

[0138] Figure 5 Schematic diagram of an example implementation 500 described herein. Example implementation 500 includes an example epitaxial structure layer stack 502 that can be selectively grown to form photodiode 316 and / or LED 318.

[0139] like Figure 5 As shown in , an n-type layer 502a of silicon germanium material may be formed in the cavity. Figure 5 As further shown in FIG. 5 , an intrinsic layer 502b of silicon germanium material may be formed above an n-type layer 502a of silicon germanium material. Figure 5 As further shown in FIG. 1 , a p-type layer 502c of silicon germanium material may be formed above an intrinsic layer 502b of silicon germanium material. The deposition tool 102 may be used in conjunction with Figure 1 The epitaxial operation, and / or another suitable deposition operation, is used to deposit the layer stack 502 of the epitaxial structure.

[0140] In some implementations, the deposition tool 102 forms the epitaxial structure layer stack 502 in only a single cavity (e.g., cavity 406 or cavity 408). In this case, the epitaxial structure in the first cavity (e.g., cavity 408) can be a selectively grown epitaxial structure that is different from the selectively grown epitaxial structure in the second cavity, and separate masking and patterning operations can be performed to form the different selectively grown epitaxial structures.

[0141] In some implementations, the deposition tool 102 forms the epitaxial structure layer stack 502 in multiple cavities (e.g., cavity 406 and cavity 408) simultaneously. In this case, a single masking and patterning operation (e.g., as combined with Figure 4B as described above) to form the same selectively grown epitaxial structure.

[0142] As mentioned above, Figure 5 are provided as examples. Other examples may differ from those described in Figure 5 described.

[0143] Figure 6 6 is a schematic diagram of example components of an apparatus 600 associated with forming an optoelectronic device including a near-infrared photodiode and a near-infrared light-emitting diode. The apparatus 600 may correspond to one or more of the semiconductor processing tools 102 to the semiconductor processing tools 116 and / or the wafer / die transfer tool 118. In some implementations, one or more of the semiconductor processing tools 102 to the semiconductor processing tools 116 and / or the wafer / die transfer tool 118 may include one or more apparatuses 600 and / or one or more components of the apparatus 600. Figure 6 As shown in , device 600 may include a bus 610 , a processor 620 , a memory 630 , an input component 640 , an output component 650 , and / or a communication component 660 .

[0144] The bus 610 may include one or more components that enable wired and / or wireless communication between components of the device 600. The bus 610 may include one or more components that enable wired and / or wireless communication between components of the device 600. Figure 6Two or more components of a computer system may be coupled together, such as via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 610 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 620 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, a special application integrated circuit, and / or another type of processing component. Processor 620 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 620 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0145] The memory 630 may include volatile and / or non-volatile memory. For example, the memory 630 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 630 may include internal memory (e.g., RAM, ROM, or hard drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 630 may be a non-transitory computer-readable medium. The memory 630 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 600. In some implementations, the memory 630 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620), such as via the bus 610. The communicative coupling between the processor 620 and the memory 630 may enable the processor 620 to read and / or process information stored in the memory 630 and / or store information in the memory 630 .

[0146] Input components 640 may enable device 600 to receive inputs, such as user inputs and / or sensory inputs. For example, input components 640 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a GPS sensor, a GNSS sensor, an accelerometer, a gyroscope, and / or an actuator. Output components 650 may enable device 600 to provide outputs, such as through a display, a speaker, and / or a light emitting diode. Communication components 660 may enable device 600 to communicate with other devices via wired and / or wireless connections. For example, communication components 660 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0147] The device 600 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 630) may store an instruction set (e.g., one or more instructions or codes) for execution by the processor 620. The processor 620 may execute the instruction set to perform one or more operations or processes described herein. In some implementations, execution of the instruction set by one or more processors 620 causes one or more processors 620 and / or the device 600 to perform one or more operations or processes described herein. In some implementations, fixed-line circuitry may be used instead of instructions or in combination with instructions to perform one or more operations or processes described herein. Additionally or otherwise, the processor 620 may be used to perform one or more operations or processes described herein. Therefore, the implementations described herein are not limited to any particular combination of hardware circuitry and software.

[0148] Figure 6 The number and configuration of components shown in are provided as examples. The device 600 may include Figure 6 Additional components, fewer components, different components, or differently configured components than those shown in . Additionally or alternatively, a set of components (e.g., one or more components) of device 600 may perform one or more functions described as being performed by another set of components of device 600.

[0149] Figure 7 FIG. 7 is a flow chart of an example process 700 associated with forming an optoelectronic device including a near-infrared photodiode and a near-infrared light-emitting diode. In some implementations, Figure 7 One or more process blocks of are performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tool 102 to the semiconductor processing tool 116 and / or the wafer / die transfer tool 118). Additionally or alternatively, Figure 7 One or more process blocks may be executed by one or more components of the apparatus 600 , such as the processor 620 , the memory 630 , the input component 640 , the output component 650 , and / or the communication component 660 .

[0150] like Figure 7 As shown in , process 700 may include forming a layer of a semiconductor structure on a dielectric region of a semiconductor device (block 710). For example, one or more of semiconductor processing tools 102-116 may form a layer of a semiconductor structure (e.g., substrate layer 312) on a dielectric region (e.g., dielectric region 304) of a semiconductor device (e.g., optoelectronic device 300) as described herein.

[0151] like Figure 7As further shown in FIG. 7 , process 700 may include forming a first cavity in a layer of a semiconductor structure (block 720). For example, one or more of semiconductor processing tools 102 to 116 may form a first cavity (e.g., cavity 406) in a layer of a semiconductor structure as described herein.

[0152] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a second cavity in a layer of the semiconductor structure adjacent to the first cavity (block 730). For example, one or more of semiconductor processing tools 102-116 may form the second cavity (e.g., cavity 408) in a layer of the semiconductor structure adjacent to the first cavity, as described herein.

[0153] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a near-infrared light emitting diode in the first cavity by selectively growing a first epitaxial structure in the first cavity (block 740). For example, one or more of semiconductor processing tools 102 to 116 may form a near-infrared light emitting diode (e.g., LED 318) in the first cavity by selectively growing a first epitaxial structure in the first cavity, as described herein.

[0154] like Figure 7 As further shown in FIG. 7 , process 700 may include forming a near-infrared photodiode in the second cavity by selectively growing a second epitaxial structure in the second cavity (block 750). For example, one or more of semiconductor processing tools 102 to semiconductor processing tools 116 may form a near-infrared photodiode (e.g., photodiode 316) in the second cavity by selectively growing a second epitaxial structure in the second cavity, as described herein.

[0155] Process 700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0156] In a first embodiment, forming a near-infrared photodiode in a first cavity by selectively growing a first epitaxial structure in a first cavity includes selectively growing an n-type layer of silicon germanium material in the first cavity, selectively growing an intrinsic layer of silicon germanium material over the n-type layer of silicon germanium material in the first cavity, and selectively growing a p-type layer of silicon germanium material over the intrinsic layer of silicon germanium material in the first cavity.

[0157] In a second embodiment, either alone or in combination with the first embodiment, forming a near-infrared light-emitting diode in the second cavity by selectively growing a second epitaxial structure in the second cavity includes selectively growing an n-type layer of silicon germanium material in the second cavity, selectively growing an intrinsic layer of silicon germanium material over the n-type layer of silicon germanium material in the second cavity, and selectively growing a p-type layer of silicon germanium material over the intrinsic layer of silicon germanium material in the second cavity.

[0158] In a third implementation, alone or in combination with one or more of the first and second implementations, process 700 includes bonding a layer of semiconductor structure with a layer of dielectric material (eg, dielectric region 304 ) after forming the near-infrared photodiode and the near-infrared light-emitting diode.

[0159] In a fourth implementation, alone or in combination with one or more of the first to third implementations, process 700 includes forming a lens over the near-infrared photodiode.

[0160] although Figure 7 Example blocks of process 700 are shown, but in some implementations, process 700 includes Figure 7 Additional blocks, fewer blocks, different blocks, or differently configured blocks than those depicted in . Additionally or alternatively, two or more blocks in process 700 may be performed in parallel.

[0161] Some implementations described herein include optoelectronic devices for low-light applications and techniques for forming optoelectronic devices. The optoelectronic devices include NIR LEDs, NIR photodiodes, and VIS photodiodes combined in a single substrate. The NIR LEDs and NIR photodiodes are formed using selectively grown epitaxial structures. The selectively grown epitaxial structures (e.g., silicon germanium (SiGe), gallium arsenide (GaAs), or another III / V type material) improve the QE performance of the NIR photodiode relative to another photodiode formed via a doped silicon structure.

[0162] By combining NIR LEDs, NIR photodiodes, and VIS photodiodes on a single substrate, the complexity and / or number of manufacturing operations to form an image detection system is smaller than the complexity and / or number of manufacturing operations to form another image detection system using discrete NIR LED devices, NIR photodiode devices, and VIS photodiode devices.

[0163] In this manner, the performance (e.g., QE) of a NIR pixel sensor device including a NIR photodiode is improved relative to another NIR pixel sensing device including a doped, organic photodiode. Improving the performance of the NIR pixel sensor device improves the manufacturing yield of the NIR pixel sensing device to a particular performance threshold. Additionally, combining the NIR LED, NIR photodiode, and VIS photodiode on a single substrate consumes less overall device space (e.g., silicon) and / or image detection system space. By increasing manufacturing yield and consuming less device space and / or image detection system space, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems (including NIR LEDs, NIR photodiodes, and VIS photodiodes) is reduced.

[0164] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a layer of silicon structure. The semiconductor device includes a near-infrared photodiode, including a layer of silicon structure of a first epitaxial structure. The semiconductor device includes a near-infrared light-emitting diode within a layer of silicon structure of a second epitaxial structure. The semiconductor device includes a deep trench isolation structure between the near-infrared photodiode and the near-infrared light-emitting diode.

[0165] In some embodiments, the first epitaxial structure and the second epitaxial structure are the same selectively grown epitaxial structure. In some embodiments, the first epitaxial structure and the second epitaxial structure are different selectively grown epitaxial structures. In some embodiments, the first epitaxial structure or the second epitaxial structure comprises a III-type periodic element, or a V-type periodic element. In some embodiments, the first epitaxial structure or the second epitaxial structure comprises: a germanium material; a silicon germanium material; a gallium arsenide material; or an indium phosphide material. In some embodiments, the semiconductor device further comprises: a sealing ring structure between a near-infrared photodiode and a near-infrared light-emitting diode. In some embodiments, the semiconductor device further comprises: a visible light photodiode adjacent to the near-infrared photodiode.

[0166] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a layer of semiconductor structure. The semiconductor device includes an array of pixel structures, the array of multiple pixel structures including an array of multiple visible light photodiodes within the layer of semiconductor structure and an array of near infrared photodiodes including selectively grown epitaxial structures and interspersed in the array of visible light photodiodes. The semiconductor device includes multiple near infrared light emitting diodes, the multiple near infrared light emitting diodes including selectively grown epitaxial structures, and the selectively grown epitaxial structures are dispersed near and along the periphery of the semiconductor device. The semiconductor device includes a sealing ring structure between the multiple near infrared light emitting diodes and the array of near infrared photodiodes.

[0167] In some embodiments, the array of visible light photodiodes within the layer of semiconductor structure comprises: a selectively grown epitaxial structure. In some embodiments, the layer of semiconductor structure comprises a silicon structure, and wherein the array of visible light photodiodes within the layer of silicon structure comprises: the silicon structure is doped with a plurality of ions to form a pn junction or a pin junction. In some embodiments, the semiconductor device further comprises: at least one deep trench isolation structure between the near-infrared light emitting diode and the array of near-infrared photodiodes. In some embodiments, the semiconductor device further comprises: a color filter array above the array of visible light photodiodes. In some embodiments, the semiconductor device further comprises: a transistor circuit system within the layer of semiconductor structure. In some embodiments, the semiconductor device further comprises: a near-infrared filter array above the array of near-infrared photodiodes. In some embodiments, the semiconductor device further comprises: one or more dielectric layers below the layer of semiconductor structure; and one or more conductive structures interspersed with this or these dielectric layers.

[0168] As described in more detail above, some implementations described herein provide a method. The method includes forming a layer of a semiconductor structure on a dielectric region of a semiconductor device. The method includes forming a first cavity in the layer of the semiconductor structure. The method includes forming a second cavity in the layer of the semiconductor structure adjacent to the first cavity. The method includes forming a near-infrared light emitting diode in the first cavity by selectively growing a first epitaxial structure in the first cavity. The method includes forming a near-infrared photodiode in the second cavity by selectively growing a second epitaxial structure in the second cavity.

[0169] In some embodiments, forming a near-infrared light emitting diode in a first cavity by selectively growing a first epitaxial structure in a first cavity includes: selectively growing an n-type layer of silicon germanium material in the first cavity; selectively growing an intrinsic layer of silicon germanium material over the n-type layer of silicon germanium material in the first cavity; and selectively growing a p-type layer of silicon germanium material over the intrinsic layer of silicon germanium material in the first cavity. In some embodiments, forming a near-infrared photodiode in a second cavity by selectively growing a second epitaxial structure in a second cavity includes: selectively growing an n-type layer of silicon germanium material in the second cavity; selectively growing an intrinsic layer of silicon germanium material over the n-type layer of silicon germanium material in the second cavity; and selectively growing a p-type layer of silicon germanium material over the intrinsic layer of silicon germanium material in the second cavity. In some embodiments, the method further includes: connecting a layer of a semiconductor structure and a layer of a dielectric material after forming the near-infrared light emitting diode and the near-infrared photodiode. In some embodiments, the method further includes: forming a lens over the near-infrared photodiode.

[0170] Some embodiments described herein provide a semiconductor device comprising: a layer of a semiconductor structure; a near-infrared photodiode within the layer of the semiconductor structure, comprising: a first selectively grown epitaxial structure; a visible light photodiode adjacent to the near-infrared photodiode; a near-infrared light-emitting diode within the layer of the semiconductor structure, comprising: a second selectively grown epitaxial structure; and a deep trench isolation structure between the near-infrared photodiode and the near-infrared light-emitting diode.

[0171] As used herein, "satisfying a threshold value" may refer to a value that is greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, and / or the like, depending on the context.

[0172] As used herein, when used in conjunction with multiple items, the term "and / or" is intended to cover each of the multiple items individually as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A but not B", and "B but not A".

[0173] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A layer of a silicon structure; A near infrared photodiode within the layer of the silicon structure, comprising: a first epitaxial structure; A near infrared light emitting diode within the layer of the silicon structure, comprising: a second epitaxial structure; and A deep trench isolation structure is provided between the near-infrared photodiode and the near-infrared light-emitting diode.

2. The semiconductor device according to claim 1, wherein The first epitaxial structure and the second epitaxial structure are the same selectively grown epitaxial structure.

3. The semiconductor device according to claim 1, wherein: Further including: A sealing ring structure is provided between the near-infrared photodiode and the near-infrared light-emitting diode.

4. The semiconductor device according to claim 1, wherein: Further including: A visible light photodiode is adjacent to the near infrared photodiode.

5. A semiconductor device, characterized in that: Include: a layer of a semiconductor structure; An array of a plurality of pixel structures comprises: an array of a plurality of visible light photodiodes within the layer of the semiconductor structure; and an array of a plurality of near-infrared photodiodes, comprising a selectively grown epitaxial structure interspersed with the array of a plurality of visible light photodiodes; A plurality of near-infrared light-emitting diodes, including the selectively grown epitaxial structure, wherein the selectively grown epitaxial structure is dispersed near and along a periphery of the semiconductor device; and A sealing ring structure is provided between the plurality of near-infrared light emitting diodes and the array of the plurality of near-infrared photodiodes.

6. The semiconductor device according to claim 5, wherein: Further including: At least one deep trench isolation structure is provided between the plurality of near infrared light emitting diodes and the array of the plurality of near infrared photodiodes.

7. The semiconductor device according to claim 5, wherein: Further including: A color filter array is disposed above the array of visible light photodiodes.

8. The semiconductor device according to claim 5, wherein: Further including: A transistor circuit system within the layer of the semiconductor structure.

9. The semiconductor device according to claim 5, further comprising: A near infrared filter array is disposed above the array of near infrared photodiodes.

10. A semiconductor device, characterized in that: Include: a layer of a semiconductor structure; A near infrared photodiode within the layer of the semiconductor structure, comprising: a first selectively grown epitaxial structure; a visible light photodiode adjacent to the near infrared photodiode; A near infrared light emitting diode in the layer of the semiconductor structure, comprising: a second selectively grown epitaxial structure; and A deep trench isolation structure is provided between the near-infrared photodiode and the near-infrared light-emitting diode.

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