Transistor metal gate structure and transistor
By adopting a multi-layer composite transition layer structure in the transistor, the problem of aluminum wedge and silicon precipitation is solved, the yield of the transistor and the bonding effect of the metal gate are improved, and the adverse effects of multi-interface performance are reduced.
Patent Information
- Application Number
- CN202323370260.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-11
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2033-12-11
AI Technical Summary
In transistor production, silicon dissolution when aluminum comes into contact with silicon wafers leads to cracks, aluminum tip wedges form, resulting in low transistor yield, and silicon precipitation during cooling, resulting in bonding failure.
Using a multi-layer composite transition layer structure, including AlCuSi layer with high silicon concentration, medium silicon concentration and low silicon concentration, it is arranged between the metal gate and the substrate, and the silicon concentration is controlled to show a specific gradient trend, avoid silicon dissolution and aluminum migration, and form Good transition structure.
It effectively solves the problems of aluminum tip wedge and silicon precipitation, improves the bonding effect between the metal gate and the lead and the yield of the transistor, and reduces the adverse effects of performance of multiple interfaces.
Smart Images
Figure CN222190735U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors, and in particular relates to a transistor gate structure and a transistor. Background Art
[0002] In the transistor production process, the formation of metal gate is a key step in metal interconnection; among them, aluminum and its alloys have good electrical properties, thermal properties and processing properties, and thus become commonly used raw materials for metal gate. However, the main semiconductor material used in transistor substrates is silicon, which has a large solubility in aluminum. When aluminum contacts silicon wafers, silicon dissolves in aluminum, causing cracks in the silicon wafers. Aluminum atoms enter the cracks to form sharp wedges, resulting in local weak points in the crystal, which easily leads to Mosfet Bvdss segmentation problems, and the resulting transistors have low yield rates.
[0003] Currently, silicon is added to aluminum or its alloys as the raw material of the metal gate to avoid the wedge problem; however, when the lead is bonded to the metal gate, the silicon dissolved in the aluminum or its alloy will precipitate on the surface of the metal gate due to cooling, resulting in silicon segregation problems, which ultimately leads to bonding failure and has great limitations. Utility Model Content
[0004] The utility model aims to ensure the bonding effect between the metal gate and the lead and the yield rate in transistor production, and provides a transistor metal gate structure and a transistor.
[0005] In the first aspect, the transistor gate structure provided by the utility model adopts the following technical solutions:
[0006] A transistor metal gate structure comprises a transition layer and an AlCu metal gate layer, wherein the transition layer is arranged between a transistor substrate and the AlCu metal gate layer, and the transition layer comprises N layers of AlCuSi layers, where N=1-3.
[0007] Further, when N=3, along the direction close to the AlCu metal gate layer, the transition layer includes a high silicon concentration layer, a medium silicon concentration layer and a low silicon concentration layer.
[0008] Furthermore, the high silicon concentration layer is AlCuSi (0.75～1wt％) The silicon concentration layer is AlCuSi (0.5～0.75wt％) layer; the low silicon concentration layer is AlCuSi (0.25～0.5wt％) layer.
[0009] Furthermore, the thickness of the AlCuSi layer is 0.5-2.5 um.
[0010] Furthermore, the AlCu metal gate layer is AlCu (0.3～0.7wt％) layer.
[0011] Furthermore, the thickness of the AlCu metal gate layer is 0.2-2.5 um.
[0012] In the second aspect, the transistor provided by the utility model adopts the following technical solution:
[0013] A transistor comprises any of the above transistor metal gate structures.
[0014] Furthermore, the transistor is selected from field effect transistors and / or insulated gate bipolar transistors.
[0015] Beneficial effects:
[0016] (1) In the present invention, a transition layer including an AlCuSi layer of an N layer is provided between the metal gate layer and the transistor substrate. The provision of the transition layer can effectively solve the aluminum wedge problem and silicon precipitation problem occurring in the transistor production process, ensure the bonding effect between the metal gate and the lead, and effectively improve the yield rate in transistor production.
[0017] (2) In the present invention, by controlling the multi-layer composite layer structure including a silicon concentration presenting a specific gradual change trend in the transition layer, silicon dissolution, aluminum migration and silicon precipitation in the transistor production process occur inside the transition layer or at the interface between the transition layer and the AlCu metal gate layer, which can better avoid the occurrence of aluminum wedge problems and silicon precipitation problems.
[0018] (3) In the present invention, the high silicon concentration layer is adjusted to be AlCuSi (0.75～1wt％) layer, medium silicon concentration layer is AlCuSi (0.5～0.75wt％) The layer and the low silicon concentration layer are AlCuSi (0.25～0.5wt％) The layer makes it possible to utilize silicon dissolution, aluminum migration, and silicon precipitation that occur during transistor production to form a better transition structure inside the metal gate structure of the transistor, greatly reducing the adverse effects of the introduction of multiple interfaces in the metal gate on transistor performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a schematic structural diagram of the metal gate structure of the transistor provided in Example 1 of the present utility model.
[0020] Figure 2 This is a schematic structural diagram of a transistor metal gate structure provided in Example 2 of the present utility model.
[0021] Figure 3 This is a schematic diagram of the structure of the transistor provided in Example 3 of the present utility model.
[0022] Figure 4This is a schematic diagram of the structure of the transistor provided in Example 4 of the utility model.
[0023] Figure 5 A schematic diagram of the structure of a transistor provided for comparative example.
[0024] Reference numerals: 1, AlCuSi layer; 11, high silicon concentration layer; 12, medium silicon concentration layer; 13, low silicon concentration layer; 2, AlCu 0.7wt％ layer; 3, crystal base; 4, substrate; 5, silicon wafer; 6, source; 7, drain; 8, oxide insulating layer; 9, metal gate. DETAILED DESCRIPTION
[0025] In order to solve the aluminum wedge problem and silicon precipitation problem existing in the existing transistor production, the inventor improved the structure of the existing transistor metal gate and obtained the technical solution of the utility model.
[0026] In the present invention, the transistor metal gate structure specifically includes a transition layer and an AlCu metal gate layer, wherein the transition layer is disposed between the transistor substrate and the AlCu metal gate layer, and the transition layer includes N layers of AlCuSi layers, where N = 1 to 3. In some specific embodiments, the AlCuSi layer included in the transition layer may specifically be 1 layer, 2 layers, or 3 layers.
[0027] In the present invention, in order to better solve the aluminum wedge problem and silicon precipitation problem existing in the existing transistor production, it is preferred to select and regulate the silicon concentration change trend of the AlCuSi layer in the transition layer, which is specifically reflected in the structure as follows: along the direction close to the AlCu metal gate layer, the transition layer includes a high silicon concentration layer, a medium silicon concentration layer and a low silicon concentration layer.
[0028] In the present invention, the high silicon concentration, medium silicon concentration and low silicon concentration in the high silicon concentration layer, medium silicon concentration layer and low silicon concentration layer only represent the relationship between the silicon concentrations within the transition layer and between the layers, and do not have any other limiting meaning.
[0029] In some preferred embodiments, the high silicon concentration layer is preferably AlCuSi (0.75～1wt％) The AlCuSi layer is a layer having a silicon concentration of 0.75 to 1 wt%. The AlCuSi layer can be obtained by conventionally adjusting the addition amount of each element in the preparation process. (0.75～1wt％) The silicon concentration layer is AlCuSi (0.5～0.75wt％) The AlCuSi layer is a layer having a silicon concentration of 0.5 to 0.75 wt %. The AlCuSi layer can be obtained by conventionally adjusting the addition amount of each element in the preparation process. ((0.5～0.75wt％) layer; the low silicon concentration layer is AlCuSi (0.25～0.5wt％)The AlCuSi layer is 0.25-0.5 wt % AlCuSi layer. The AlCuSi layer can be obtained by adjusting the addition amount of each element in the preparation process. (0.25～0.5wt％) It should be noted that the sum of the concentrations of Al, Cu and Si in the high silicon concentration layer, the medium silicon concentration layer and the low silicon concentration layer is 1.
[0030] In the present invention, the high silicon concentration layer is further preferably AlCu (0.3～0.7wt％) Si (0.75～1wt％) The AlCuSi layer is a layer having a copper concentration of 0.3-0.7 wt% and a silicon concentration of 0.75-1 wt%. The AlCuSi layer can be obtained by conventionally adjusting the addition amount of each element in the preparation process. (0.3～0.7wt％) Si (0.75～1wt％) layer.
[0031] In the present invention, the medium silicon concentration layer is further preferably AlCu (0.3～0.7)wt％ Si (0.5～0.75wt％) The AlCuSi layer is a layer having a copper concentration of 0.3-0.7 wt% and a silicon concentration of 0.5-0.75 wt%. The AlCuSi layer can be obtained by conventionally adjusting the addition amount of each element in the preparation process. (0.3～0.7wt％) Si (0.5～0.75wt％) layer.
[0032] In the present invention, the low silicon concentration layer is preferably AlCu (0.3～0.7wt％) Si (0.25～0.5wt％) The AlCuSi layer is a layer having a copper concentration of 0.3-0.7 wt% and a silicon concentration of 0.25-0.5 wt%. The AlCuSi layer can be obtained by conventionally adjusting the addition amount of each element in the preparation process. (0.3～0.7wt％) Si (0.25～0.5wt％) layer.
[0033] In the present invention, the thickness of the AlCuSi layer is preferably 0.5-2.5um, specifically 0.5um, 0.6um, 0.8um, 1.0um, 1.5um, 2.0um, 2.5um or any value therebetween.
[0034] In the present invention, the AlCu metal gate layer is preferably AlCu (0.3～0.7wt％) The AlCu layer is a layer having a copper concentration of 0.3 to 0.7 wt%. The AlCu layer can be obtained by conventionally adjusting the addition amount of each element in the preparation process. (0.3～0.7wt％) It should be noted that the sum of the concentrations of Al and Cu in the AlCu metal gate layer is 1.
[0035] In the present invention, the thickness of the AlCu metal gate layer is preferably 0.5-2.5um, and specifically can be 0.5um, 0.8um, 1.0um, 1.5um, 1.6um, 2.0um, 2.5um or any value therebetween.
[0036] In the present invention, a transistor is also provided, the transistor comprising the above transistor metal gate structure. In some specific implementations, the transistor may be but is not limited to a field effect transistor and / or an insulated gate bipolar transistor.
[0037] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.
[0038] Example 1
[0039] This embodiment is used to illustrate a transistor metal gate structure. Figure 1 The structure specifically includes a transition layer 1 and an AlCu metal gate layer 2. The transition layer 1 is located at the AlCu 0.7wt％ Between layer 2 and the crystalline substrate 3, the transition layer 1 only includes a layer of AlCu 0.7wt％ Si 0.75wt％ layer; and AlCu 0.7wt％ Si 0.75wt％ The thickness of the layer is 2.5um, AlCu 0.7wt％ The thickness of the metal gate layer 2 is 2.5 um.
[0040] Example 2
[0041] This embodiment is used to illustrate a transistor metal gate structure. Figure 2 The structure specifically includes a transition layer 1 and an AlCu 0.7wt％ Layer 2. Transition layer 1 is located between AlCu 0.7wt％ Between the layer 2 and the crystalline substrate 3, the transition layer 1 includes a 0.7wt％ The high silicon concentration layer 11, the medium silicon concentration layer 12 and the low silicon concentration layer 13 are arranged in the order of the layers. 0.7wt％ The thickness of layer 2 is 2.0um, and the high silicon concentration layer 11 is selected as AlCu with a thickness of 0.5um. 0.3wt％ Si 1.00wt％ medium silicon concentration layer 12 is selected to be 0.5um thick AlCu 0.3wt％ Si 0.75wt％ The low silicon concentration layer 13 is selected as AlCu with a thickness of 0.5um. 0.3wt％ Si 0.50wt％ layer.
[0042] Example 3
[0043] This embodiment is used to illustrate a field effect transistor. Figure 3 The field effect transistor specifically includes a substrate 4, a silicon wafer 5, a source 6, a drain 7, an oxidized insulating layer 8 and a metal gate 9. One side of the substrate 4 is bonded to the silicon wafer 5, the source 6 and the drain 7 are both embedded in the side of the silicon wafer 5 away from the substrate 4, and the channel length between the source 6 and the drain 7 is 10um; the oxidized insulating layer 8 is located between the source 6 and the drain 7, and one side is bonded to the side of the silicon wafer 5 away from the substrate 4; the metal gate 9 is bonded to the side of the oxidized insulating layer 8 away from the silicon wafer 5, and the metal gate 9 has the transistor metal gate structure provided in Example 1.
[0044] The 500 finished field effect transistors provided in this embodiment were verified by piecewise segmentation, and the yield rate was 92.31%.
[0045] Example 4
[0046] The field effect transistor provided in this embodiment is basically the same as that in embodiment 3. Figure 4 , the difference is that the metal gate 9 is the transistor metal gate structure provided in Example 2, and the other structures are the same.
[0047] The 500 finished field effect transistors provided in this embodiment were verified by slice verification, and the yield rate was 97.51%.
[0048] Comparative Example
[0049] The field effect transistor provided in this comparative example is basically the same as that in Example 3. Figure 5 The difference is that the metal gate 9 is an AlCu metal gate layer, and the other structures are the same.
[0050] The 500 finished field effect transistors provided by the comparative example were verified by piecewise division, and the yield rate was 75.64%.
[0051] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A transistor metal gate structure, characterized in that: The invention comprises a transition layer and an AlCu metal gate layer, wherein the transition layer is arranged between the transistor substrate and the AlCu metal gate layer, and the transition layer comprises N layers of AlCuSi layers, where N=1-3.
2. The transistor metal gate structure according to claim 1, characterized in that: When N=3, along the direction close to the AlCu metal gate layer, the transition layer includes a high silicon concentration layer, a medium silicon concentration layer and a low silicon concentration layer.
3. The transistor metal gate structure according to claim 1, characterized in that: The thickness of the AlCuSi layer is 0.5-2.5 um.
4. The transistor metal gate structure according to claim 1, characterized in that: The thickness of the AlCu metal gate layer is 0.5-2.5 um.
5. A transistor, characterized in that: The invention comprises the transistor metal gate structure as claimed in any one of claims 1 to 4.
6. The transistor according to claim 5, characterized in that The transistor is selected from a field effect transistor and / or an insulated gate bipolar transistor.