Low-resistance plane gate silicon carbide MOSFET

Abstract

The utility model provides a low-resistance planar gate silicon carbide MOSFET. The low-resistance planar gate silicon carbide MOSFET is characterized in that a well region is connected with a silicon carbide substrate; the isolation dielectric layer is connected with the well region; the body diode region is connected with the well region, and the body diode region is connected with the isolation dielectric layer; the transverse conductive channel region is connected to the isolation dielectric layer and the body diode region; a source region is arranged on the transverse conductive channel region and is connected to the isolation dielectric layer; the longitudinal conductive channel region sequentially passes through the transverse conductive channel region, the isolation dielectric layer and the well region; the longitudinal conductive channel region is connected to the silicon carbide substrate; the gate dielectric layer is connected to the transverse conductive channel region and the source region; the source electrode metal layer is connected to the source region; the source electrode metal layer is connected with the body diode region and the isolation dielectric layer; the gate metal layer is connected to the gate dielectric layer, the gate metal layer is located over the transverse conductive channel region, and the portion, located above the longitudinal conductive channel region, of the gate metal layer is hollowed out; the drain metal layer is connected to the silicon carbide substrate, so that the on-resistance of the power device is further reduced.

Description

Technical Field

[0001] The utility model relates to a low-resistance planar gate silicon carbide MOSFET. Background Art

[0002] Silicon carbide (SiC) material, as a wide bandgap semiconductor, has good properties and has been widely used in the design and application of power devices. Power MOSFET made of it has the advantages of high input impedance, good temperature characteristics, strong voltage resistance, excellent frequency characteristics, and fast switching speed, and is widely used in various fields.

[0003] As a representative device among SiC power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. Especially under high current application conditions, reducing its on-resistance can effectively reduce device losses, which is of great significance for improving energy efficiency and achieving the "dual carbon goals". Therefore, it is urgent to further reduce the resistance of this power device. Utility Model Content

[0004] The technical problem to be solved by the utility model is to provide a low-resistance planar gate silicon carbide MOSFET, so that the on-resistance of the power device is further reduced, thereby effectively reducing the loss of the device.

[0005] The utility model is implemented as follows: a low-resistance planar gate silicon carbide MOSFET, comprising:

[0006] A silicon carbide substrate,

[0007] a well region, wherein the lower side of the well region is connected to the upper side of the silicon carbide substrate;

[0008] An isolation dielectric layer, wherein the lower side of the isolation dielectric layer is connected to the well region;

[0009] A body diode region, wherein a lower side of the body diode region is connected to the well region, and an inner side of the body diode region is connected to an outer side of the isolation dielectric layer;

[0010] A lateral conductive channel region, wherein the lower side of the lateral conductive channel region is connected to the upper side of the isolation dielectric layer and the upper side of the body diode region; a source region is disposed on the lateral conductive channel region, wherein the lower side of the source region is connected to the upper side of the isolation dielectric layer;

[0011] A longitudinal conductive channel region, wherein the longitudinal conductive channel region sequentially passes through the transverse conductive channel region, the isolation dielectric layer and the well region; the lower side of the longitudinal conductive channel region is connected to the upper side of the silicon carbide substrate;

[0012] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the lateral conductive channel region and the upper side of the source region;

[0013] A source metal layer, wherein a side surface of the source metal layer is connected to a side surface of the source region, and a lower side surface of the source metal layer is connected to an upper side surface of the body diode region and an upper side surface of the isolation dielectric layer;

[0014] A gate metal layer, the gate metal layer is connected to the gate dielectric layer, the gate metal layer is located directly above the lateral conductive channel region, and the gate metal layer is hollowed out above the longitudinal conductive channel region;

[0015] and a drain metal layer, the upper side of the drain metal layer being connected to the lower side of the silicon carbide substrate.

[0016] The utility model has the following advantages: the utility model is a low-resistance planar gate silicon carbide MOSFET, which adopts the cooperation of the lateral conductive channel region and the longitudinal conductive channel region to ensure the low-resistance path when the current flows longitudinally, the lateral conductive channel region is symmetrically distributed on both sides of the longitudinal conductive channel region, the width of the gate metal layer is equal to the width of the lateral conductive channel region, the potential of the gate metal layer can achieve complete control of the lateral conductive channel region, and enhance the gate control capability, when the gate metal layer is positively pressurized, that is, when the device is turned on, the carriers in the lateral conductive channel region are inverted to form a low-resistance lateral conductive channel, the lateral conductive channel is directly connected to the longitudinal conductive channel, thereby achieving low impedance of the full conductive channel of the device and reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0018] Figure 1 The utility model is a schematic diagram of a low-resistance planar gate silicon carbide MOSFET.

[0019] Figure 2 The utility model is a flow chart of a method for manufacturing a low-resistance planar gate silicon carbide MOSFET.

[0020] Figure 3 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 1 .

[0021] Figure 4 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 2 .

[0022] Figure 5 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 3 .

[0023] Figure 6 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 4 .

[0024] Figure 7 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 5 .

[0025] Figure 8 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 6 .

[0026] Fig. 9 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 7 .

[0027] Fig.10 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 8 .

[0028] Fig.11 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 9 .

[0029] Fig.12 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 10 .

[0030] Fig.13 This is a cross-sectional view of the process of a low-resistance planar gate silicon carbide MOSFET of the utility model. Figure 10 one. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] The doping concentration of the silicon carbide substrate 1 is 2e18cm -3 , is N+ type; the doping concentration of the well region 2 is 3e16cm -3 , is P type; the doping concentration of the longitudinal conductive channel region 6 is 5e17cm -3, is N+ type; the doping concentration of the body diode region 4 is 6e18 cm -3 The doping concentration of the source region 51 is 2e18cm -3 , is N+ type; the doping concentration of the lateral conductive channel region 5 is 3e16 cm -3 , is P type; high doping is used in the longitudinal conductive channel region 6 to reduce the on-resistance, low doping of the inversion conductive layer is easy to invert, reducing the driving voltage, and low doping of the withstand voltage structure to improve the withstand voltage.

[0037] like Figure 1 As shown, the embodiment of the present application provides a low-resistance planar gate silicon carbide MOSFET, including:

[0038] A silicon carbide substrate 1,

[0039] a well region 2, wherein the lower side of the well region 2 is connected to the upper side of the silicon carbide substrate 1;

[0040] An isolation dielectric layer 3, wherein the lower side of the isolation dielectric layer 3 is connected to the well region 2;

[0041] A body diode region 4, wherein the lower side of the body diode region 4 is connected to the well region 2, and the inner side of the body diode region 4 is connected to the outer side of the isolation dielectric layer 3;

[0042] A lateral conductive channel region 5, wherein the lower side of the lateral conductive channel region 5 is connected to the upper side of the isolation dielectric layer 3 and the upper side of the body diode region 4; a source region 51 is provided on the lateral conductive channel region 5, wherein the lower side of the source region 51 is connected to the upper side of the isolation dielectric layer 3;

[0043] A longitudinal conductive channel region 6, wherein the longitudinal conductive channel region 6 sequentially passes through the transverse conductive channel region 5, the isolation dielectric layer 3 and the well region 2; the lower side of the longitudinal conductive channel region 6 is connected to the upper side of the silicon carbide substrate 1;

[0044] A gate dielectric layer 7, wherein the lower side of the gate dielectric layer 7 is connected to the upper side of the lateral conductive channel region 5 and the upper side of the source region 51;

[0045] A source metal layer 8, wherein a side surface of the source metal layer 8 is connected to a side surface of the source region 51, and a lower side surface of the source metal layer 8 is connected to an upper side surface of the body diode region 4 and an upper side surface of the isolation dielectric layer 3;

[0046] A gate metal layer 9, wherein the gate metal layer 9 is connected to the gate dielectric layer 7, and the gate metal layer 9 is located directly above the lateral conductive channel region 5, and is hollow above the longitudinal conductive channel region 6;

[0047] and a drain metal layer 10 , wherein the upper side of the drain metal layer 10 is connected to the lower side of the silicon carbide substrate 1 .

[0048] The isolation dielectric layer 3 is intrinsic diamond; the doping concentration of the well region 2 is equal to the doping concentration of the lateral conductive channel region 5 .

[0049] The gate dielectric layer 7 is made of silicon dioxide or high-k dielectric.

[0050] The isolation dielectric layer 3 is intrinsic diamond, which has no conductivity but has a high breakdown field strength, thereby isolating the lateral conductive channel region 5 and the well region 2. When the control device is turned on, it verifies the flow of the lateral and longitudinal conductive channels to prevent the current from flowing in other high-resistance directions. The intrinsic diamond material can not only ensure the voltage resistance characteristics, but also dissipate heat, achieve high resistance, and control the current flow direction.

[0051] The gate metal layer 9 is located directly above the transverse conductive channel region 5, and the transverse conductive channel region 5 and the longitudinal conductive channel region 6 are used in combination. The longitudinal conductive channel region 6 is heavily N-type doped to ensure a low-resistance path when the current flows longitudinally. The transverse conductive channel region 5 is symmetrically distributed on both sides of the longitudinal conductive channel region 6. The transverse conductive channel region 5 is covered by the gate metal layer 9, that is, the width of the gate metal layer 9 is equal to the width of the transverse conductive channel region 5. The potential of the gate metal layer 9 can achieve complete control of the transverse conductive channel region 5, thereby enhancing the gate control capability. When the gate metal layer 9 is applied with a positive voltage, that is, when the device is turned on, the carriers in the transverse conductive channel region 5 are inverted to form a low-resistance transverse conductive channel. The transverse conductive channel is directly connected to the longitudinal conductive channel, thereby achieving low impedance of the device's full conductive channel and reducing the on-resistance of the device.

[0052] There is a P+ type body diode region 4 below the source metal layer 8, which is used to form the body diode of the device. The body diode is used to complete the freewheeling of the current from the source to the drain when the device is not turned on.

[0053] like Figures 2 to 13 As shown, the manufacturing method of the above silicon carbide MOSFET includes the following steps:

[0054] Step 1: depositing metal on one side of the silicon carbide substrate 1 to form a drain metal layer 10, and epitaxially growing a well region 2 on the other side of the silicon carbide substrate 1;

[0055] Step 2, depositing a barrier layer a above the well region 2, etching the barrier layer to form a through hole, and performing ion implantation into the through hole to form a body diode region 4;

[0056] Step 3, removing the barrier layer a, re-forming the barrier layer a, etching the barrier layer a and the well region 2 to form an isolation region b, and depositing an isolation dielectric layer 3 in the isolation region b;

[0057] Step 4, removing the barrier layer a, and depositing a lateral conductive channel region 5 having the same doping concentration as the well region 2;

[0058] Step 5, forming a barrier layer a, etching to form a through hole, and performing ion implantation into the well region 2 through the through hole to form a longitudinal conductive channel region 6;

[0059] Step 6, removing the barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing ion implantation on the lateral conductive channel region 5 to form a source region 51;

[0060] Step 7, removing the barrier layer a, and depositing to form a gate dielectric layer 7;

[0061] Step 8, re-forming the barrier layer a, etching the barrier layer a and the lateral conductive channel region 5 to form a source metal region c, and performing metal deposition to form a source metal layer 8;

[0062] Step 9, remove the barrier layer a, re-form the barrier layer a, etch the barrier layer to form a through hole, deposit metal in the through hole, and form a gate metal layer 9.

[0063] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A low resistance planar gate silicon carbide MOSFET, characterized in that: include: A silicon carbide substrate, a well region, wherein the lower side of the well region is connected to the upper side of the silicon carbide substrate; An isolation dielectric layer, wherein the lower side of the isolation dielectric layer is connected to the well region; A body diode region, wherein a lower side of the body diode region is connected to the well region, and an inner side of the body diode region is connected to an outer side of the isolation dielectric layer; A lateral conductive channel region, wherein the lower side of the lateral conductive channel region is connected to the upper side of the isolation dielectric layer and the upper side of the body diode region; a source region is disposed on the lateral conductive channel region, wherein the lower side of the source region is connected to the upper side of the isolation dielectric layer; A longitudinal conductive channel region, wherein the longitudinal conductive channel region sequentially passes through the transverse conductive channel region, the isolation dielectric layer and the well region; the lower side of the longitudinal conductive channel region is connected to the upper side of the silicon carbide substrate; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the lateral conductive channel region and the upper side of the source region; A source metal layer, wherein a side surface of the source metal layer is connected to a side surface of the source region, and a lower side surface of the source metal layer is connected to an upper side surface of the body diode region and an upper side surface of the isolation dielectric layer; A gate metal layer, the gate metal layer is connected to the gate dielectric layer, the gate metal layer is located directly above the lateral conductive channel region, and the gate metal layer is hollowed out above the longitudinal conductive channel region; and a drain metal layer, the upper side of the drain metal layer being connected to the lower side of the silicon carbide substrate.

2. A low resistance planar gate silicon carbide MOSFET according to claim 1, characterized in that: The isolation medium layer is made of intrinsic diamond.

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