Embedded core board, embedded mother board and electronic equipment

Abstract

The embodiment of the utility model discloses an embedded core board, an embedded mother board and electronic equipment, the embedded core board comprises a main control chip, a memory chip and a storage chip, the storage chip comprises a memory time sequence storage unit and a boot loader unit; the main control chip is connected with the memory chip, and a boot loader unit and a memory time sequence storage unit in the memory chip; the main control chip is provided with a first external interface, and the first external interface is used for being connected with the extended storage medium. According to the embedded core board, the first external interface is arranged on the main control chip in the embedded core board, so that the embedded core board can be connected with the corresponding extended storage medium through the first external interface according to actual use requirements on the basis of realizing a basic storage function through the storage chip of the embedded core board, and the overall storage space is expanded; therefore, the operation effect of the embedded core board is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of embedded technology, and in particular to an embedded core board, an embedded mainboard and an electronic device. Background Art

[0002] With the continuous development of electronic technology, the integration and performance of PCB boards are constantly improving. PCB boards are widely used in many fields such as smart terminals, Internet of Things, smart homes, smart manufacturing, medical electronics, aerospace, etc.

[0003] The core board is a common PCB board used in the embedded field. The memory and storage of existing embedded core boards are often fixed, such as the ratio of memory to storage is 1:4 or 1:8. In actual applications, it is very easy to have a situation where the memory is suitable but the storage is insufficient or excessive; or the storage is suitable but the memory is insufficient or excessive; resulting in poor operation of the embedded core board. Utility Model Content

[0004] The embodiments of the present application provide an embedded core board, an embedded motherboard and an electronic device, which can solve the problem of poor operating performance of existing embedded core boards, and provide an interface for external expansion storage media, so that in actual applications, corresponding expansion storage media can be externally connected as needed, thereby improving the operating performance of the embedded core board.

[0005] The embodiment of the present application provides an embedded core board, the embedded core board includes a main control chip, a memory chip and a storage chip, the storage chip includes a memory timing storage unit and a boot loader unit, the memory timing storage unit is used to store memory timing data;

[0006] The main control chip is connected to the memory chip, the boot loader unit in the storage chip and the memory timing storage unit, and the main control chip is used to obtain memory timing data from the memory timing storage unit and initialize the memory chip according to the memory timing parameters;

[0007] The main control chip is provided with a first external interface, and the first external interface is used to connect to an extended storage medium.

[0008] Furthermore, the main control chip is a CPU or a SoC processor.

[0009] Furthermore, the memory chip is a DDR memory chip.

[0010] Furthermore, the storage chip is a Nor Flash storage chip.

[0011] Furthermore, the first external interface is an SDIO interface.

[0012] Furthermore, the embedded core board also includes a core power module;

[0013] The core power module is connected to the main control chip, the memory chip and the storage chip.

[0014] The embodiment of the present application also provides an embedded motherboard, the embedded motherboard comprising a memory and the above-mentioned embedded core board;

[0015] The memory is connected to the main control chip in the embedded core board.

[0016] Furthermore, the embedded motherboard also includes an optional power supply module;

[0017] The optional power supply module is connected to the main control chip, the memory chip and the storage chip in the embedded core board.

[0018] Furthermore, the embedded motherboard also includes a second external interface;

[0019] The second external interface is connected to a corresponding terminal in the main control chip, and the external interface is used for communication with an external device.

[0020] Furthermore, the second external interface includes one or more of a CAN interface, an RS485 interface, an HDMI interface, a USB interface and an Ethernet interface.

[0021] An embodiment of the present application also provides an electronic device, including the above-mentioned embedded core board or the above-mentioned embedded motherboard.

[0022] The embodiments of the present application provide an embedded core board, an embedded motherboard and an electronic device, which have the following beneficial effects:

[0023] By setting the first external interface on the main control chip in the embedded core board, the embedded core board is made to realize basic storage function by the memory chip of itself.On this basis, the corresponding extended storage medium can also be connected according to actual use demand by the first external interface, to expand the overall storage space, compared with the embedded core board of the collocation ratio of the existing fixed memory and storage, the present embodiment is by providing the first external interface of the external extended storage medium, so that the corresponding extended storage medium can be externally connected according to actual demand during actual application, the collocation ratio of memory and storage is dynamically adjusted, so as to improve the operation effect of the embedded core board.Meanwhile, the memory chip includes a boot loader unit and a memory timing storage unit, and is physically isolated from other data stored in the memory, and the boot loader unit and the memory timing storage unit are protected, and the stability of the core board is improved, so as to further improve the operation effect of the core board. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a first schematic diagram of an embedded core board provided in an embodiment of the present application;

[0025] Figure 2 It is a second schematic diagram of the embedded core board provided in the embodiment of the present application;

[0026] Figure 3 is a first schematic diagram of an embedded motherboard provided in an embodiment of the present application;

[0027] Figure 4 This is a second schematic diagram of the embedded motherboard provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0029] Figure 1 is a first schematic diagram of an embedded core board provided in an embodiment of the present application, such as Figure 1 As shown, the embedded core board 11 includes a main control chip 111, a memory chip 112 and a storage chip 113. Among them, the storage chip 113 includes a memory timing storage unit 1131 and a boot loader unit 1132, the memory timing storage unit 1131 is used to store memory timing data, and the boot loader unit 1132 is used to store boot loading data, such as Bootloader data. The main control chip 111 is connected to the memory chip 112, the boot loader unit 1132 in the storage chip 113, and the memory timing storage unit 1131. The main control chip 111 is used to load the Bootloader data from the boot loader unit 1132 to initialize itself, and obtain the memory timing data from the memory timing storage unit 1131, and initialize the memory chip 112 according to the memory timing parameters. The main control chip 111 is provided with a first external interface 1111, and the first external interface 1111 is used to connect the extended storage medium. Figure 1The solid line in represents a signal line, and the arrow direction represents that the host points to the slave, that is, represents that the host controls the slave. It should be noted that, based on the signal flow direction being bidirectional, the solid arrow does not represent the signal flow direction, and is only used to identify the master and slave. Above, by arranging the first external interface 1111 on the main control chip 111 in the embedded core board 11, on the basis of enabling the embedded core board 11 to realize the basic storage function by its own memory chip 113, the corresponding extended storage medium can also be connected according to the actual use demand through the first external interface 1111, to expand the overall storage space, compared with the embedded core board of the existing fixed memory and storage matching ratio, the present embodiment provides the first external interface 1111 of the external extended storage medium, so that the corresponding extended storage medium can be connected according to the actual demand during actual application, and the memory and storage matching ratio are dynamically adjusted, so as to improve the operation effect of the embedded core board 11.

[0030] Figure 2 is a second schematic diagram of the embedded core board provided in the embodiment of the present application, such as Figure 2 As shown, the embedded core board 11 includes a main control chip 111, a memory chip 112, a storage chip 113 and a core power module 114. Among them, the storage chip 113 includes a memory timing storage unit 1131 and a boot loader unit 1132, the memory timing storage unit 1131 is used to store memory timing data, and the boot loader unit 1132 is used to store boot loading data, such as Bootloader data. The core power module 114 is connected to the main control chip 111, the memory chip 112 and the storage chip 113. The main control chip 111 is connected to the memory chip 112, the boot loader unit 1132 in the storage chip 113 and the memory timing storage unit 1131, and the main control chip 111 is used to load the Bootloader data from the boot loader unit 1132 to initialize itself, and obtain the memory timing data from the memory timing storage unit 1131, and initialize the memory chip 112 according to the memory timing parameters. The main control chip 111 is provided with a first external interface 1111 , and the first external interface 1111 is used to connect an extended storage medium. Figure 2In the dotted line represents the power line, and the arrow direction represents the power supply current direction. The solid line represents the signal line, and the arrow direction represents that the host points to the slave, that is, represents that the host controls the slave. It should be noted that, based on the signal flow direction being bidirectional, the solid arrow does not represent the signal flow direction, and is only used to identify the master and slave. Above, by arranging the first external interface 1111 on the main control chip 111 in the embedded core board 11, on the basis of enabling the embedded core board 11 to realize the basic storage function by its own memory chip 113, the corresponding extended storage medium can also be connected according to the actual use demand by the first external interface 1111, to expand the overall storage space, compared with the embedded core board of the existing fixed memory and storage matching ratio, the present embodiment provides the first external interface 1111 of the external extended storage medium, so that the corresponding extended storage medium can be connected according to the actual demand during actual application, and the memory and storage matching ratio are dynamically adjusted, so as to improve the operation effect of the embedded core board 11.

[0031] In one embodiment, the main control chip 111 is a CPU or a SoC processor. The CPU or SoC processor is connected to a memory chip 112, a storage chip 113, and a core power module 114, and the core power module 114 is used to power the CPU or SoC processor. The CPU or SoC processor power supply is provided with a first external interface 1111, and the first external interface 1111 is used to connect an extended storage medium.

[0032] In one embodiment, the memory chip 112 is a DDR memory chip, which is connected to the main control chip 111 (ie, a CPU or a SoC processor) and the core power module 114 .

[0033] In one embodiment, the memory chip 113 is a Nor Flash memory chip, which is connected to the main control chip 111 (ie, the CPU or SoC processor) and the core power module 114 .

[0034] In one embodiment, the Nor Flash storage chip includes a memory timing storage unit 1131 and a boot loader unit 1132, the memory timing storage unit 1131 is used to store memory timing data (e.g., DDR timing data), and the boot loader unit 1132 is used to store boot loading data, such as Bootloader data. The boot loader unit 1132 is connected to the main control chip 111 (i.e., CPU or SoC processor), and the main control chip 111 (i.e., CPU or SoC processor) is used to load Bootloader data from the boot loader unit 1132 to initialize itself. The memory timing storage unit 1131 is connected to the main control chip 111 (i.e., CPU or SoC processor), and the main control chip 111 (i.e., CPU or SoC processor) is used to obtain memory timing parameters from the memory timing storage unit 1131, and initialize the memory chip 112 according to the memory timing parameters. Exemplarily, when the main control chip 111 (i.e., the CPU or SoC processor) is powered on, the boot loader unit 1132 (e.g., BootLoader program) in the Nor Flash storage chip (i.e., the storage chip 113) is started. Based on the operation of the boot loader unit 1132 (e.g., BootLoader program), the boot loader unit 1132 (e.g., BootLoader program) loads the Bootloader data into the main control chip 111 (i.e., the CPU or SoC processor), and the main control chip 111 (i.e., the CPU or SoC processor) initializes itself based on the Bootloader data. The main control chip 111 (i.e., the CPU or SoC processor) obtains the DDR timing data from the memory timing storage unit 1131, and initializes the memory chip 112 (i.e., the DDR memory chip) according to the DDR timing data. After the initialization process is completed, that is, after ensuring that the memory chip 112 (i.e., the DDR memory chip) is running stably, the system firmware is loaded and run. It should be noted that the system firmware is stored in other storage chips, such as an external eMMC storage chip. As described above, by separating the DDR timing data from the system firmware, that is, storing the DDR timing data in the Nor Flash storage chip (i.e., storage chip 113), and storing the system firmware in other storage chips, compared with the existing method of storing the DDR timing data in the system firmware, when the system firmware is changed, this embodiment does not need to change the timing data, thereby improving the stability of the system.

[0035] In one embodiment, the embedded core board 11 has a length of 40 mm and a width of 30 mm.

[0036] In one embodiment, the embedded core board 11 has a length of 40 mm and a width of 35 mm.

[0037] Figure 3 is a first schematic diagram of an embedded motherboard provided in an embodiment of the present application, referring to Figure 3 The embedded motherboard 1 comprises the above-mentioned embedded core board 11 and an optional power supply module 12. The embedded core board 11 is mounted on the embedded motherboard 1. The optional power supply module 12 is connected to a main control chip 111, a memory chip 112 and a storage chip 113 in the embedded core board 11. Figure 3 The dotted line in represents the power line, and the direction of the arrow represents the direction of the power supply current. The solid line represents the signal line, and the direction of the arrow represents the host pointing to the slave, that is, it represents the host controlling the slave. It should be noted that, based on the fact that the signal flow is bidirectional, the solid arrow does not represent the signal flow, but is only used to identify the master and slave. The optional power supply module 12 is also connected to other components in the embedded motherboard 1 to power the other components. The optional power supply module 12 powers on the main control chip 111, and the main control chip 111 is used to transmit an indication signal to the optional power supply module 12 after power-on, so that the optional power supply module 12 powers on other components in the embedded motherboard 1, so that the embedded core board 11 is powered on first, and the other components of the baseboard are powered on later, which can avoid IO current backflow, thereby protecting the embedded core board 11 and improving system stability. It should be noted that, Figure 3 As shown, the embedded core board 11 in this embodiment is not provided with a power module, and the components in the embedded core board 11 are all powered by the optional power module 12.

[0038] Figure 4 is a second schematic diagram of an embedded motherboard provided in an embodiment of the present application, referring to Figure 4 The embedded motherboard 1 includes the above-mentioned embedded core board 11 and an optional power supply module 12. The embedded core board 11 is installed on the embedded motherboard 1, and a core power supply module 114 is provided on the embedded core board 11. The optional power supply module 12 is connected to the main control chip 111, the memory chip 112 and the storage chip 113 in the embedded core board 11. Figure 4The dotted line in represents the power line, and the arrow direction represents the power supply current direction. The solid line represents the signal line, and the arrow direction represents that the host points to the slave, that is, represents that the host controls the slave. It should be noted that based on the signal flow direction being bidirectional, the solid arrow does not represent the signal flow direction, and is only used to identify the master and slave. The optional power supply module 12 is also connected with other components in the embedded motherboard 1 to power other components. The core power supply module 114 in the embedded core board 11 is powered on for the main control chip 111, and the main control chip 111 is used to transmit the indication signal to the optional power supply module 12 after powering on, so that the optional power supply module 12 is powered on for other components in the bottom plate except the embedded core board 11 in the embedded motherboard 1, and the embedded core board 11 is powered on first, and the other components of the bottom plate are powered on later, and the IO current backflow can be avoided, thereby protecting the embedded core board 11, and then improving the system stability.

[0039] In one embodiment, the optional power supply module 12 has multiple output voltage values, for example, 3.3V output voltage and 1.8V output voltage are configured. The indication signal transmitted by the main control chip 111 is a GPIO signal, and multiple GPIO signals can be set, and each GPIO signal corresponds to an output voltage value. For example, the GPIO1 signal corresponds to a 3.3V output voltage, and the GPIO2 signal corresponds to a 1.8V output voltage. When the main control chip 111 is powered on, when the GPIO1 signal is sent to the optional power supply module 12, the optional power supply module 12 outputs a 3.3V output voltage to power the components in the embedded motherboard 1. When the main control chip 111 is powered on, when the GPIO2 signal is sent to the optional power supply module 12, the optional power supply module 12 outputs a 1.8V output voltage to power the components in the embedded motherboard 1. As described above, by configuring multiple output voltage values, in actual use, the corresponding output voltage value can be selected for power supply according to actual needs, thereby improving the flexibility of voltage supply and thus improving the user experience.

[0040] In one embodiment, the embedded motherboard 1 also includes a memory 13. The memory 13 may be an eMMC memory chip, a hard disk, a USB flash drive, a memory card, etc. The memory 13 is connected to the main control chip 111 and the optional power supply module 12. Among them, the main control chip 111 is connected to the memory 13 via the first external interface 111. The first external interface 111 may be an SDIO interface. The memory 13 is used to store system firmware. Exemplarily, when the main control chip 111 (i.e., the CPU or SoC processor) is powered on, the BootLoader program in the Nor Flash storage chip (i.e., the storage chip 113) is started, and based on the running of the BootLoader program, the boot loader unit 1132 (e.g., the BootLoader program) loads the Bootloader data into the main control chip 111 (i.e., the CPU or SoC processor), and the main control chip 111 (i.e., the CPU or SoC processor) initializes itself based on the Bootloader data. The main control chip 111 (i.e., the CPU or SoC processor) obtains the DDR timing data from the memory timing storage unit 1131, and initializes the memory chip 112 (i.e., the DDR memory chip 112) according to the DDR timing data. After the initialization is completed, that is, after ensuring that the memory chip 112 (i.e., the DDR memory chip 112) is running stably, the system firmware is loaded from the memory 13, and the running system firmware is started. As described above, by separating the DDR timing data from the system firmware, that is, storing the DDR timing data in the NorFlash storage chip (i.e., the storage chip 113), and storing the system firmware in the memory 13, compared with the existing method of storing the DDR timing data in the system firmware, when the system firmware in the memory 13 is changed, the timing data of the Nor Flash storage chip (i.e., the storage chip 113) does not need to be changed. Compared with the existing method of needing to change the system firmware and the timing data at the same time, the method of this embodiment reduces the maintenance difficulty, thereby improving the overall operation stability of the system.

[0041] In one embodiment, the embedded motherboard 1 further includes a second external interface 14. The second external interface 14 is connected to a corresponding terminal in the main control chip 111, and the second external interface 14 is used to communicate with an external device. The main control chip 111 is connected to the second external interface 14 through an IO interface or other dedicated interface. The second external interface 14 includes one or more of a CAN interface, an RS485 interface, an HDMI interface, a USB interface, and an Ethernet interface.

[0042] As mentioned above, by arranging the memory 13 outside the embedded core board 11, the main control chip 111 in the embedded core board 11 has the first external interface 1111 of the externally extended storage medium, and the corresponding extension interface of the embedded core board 11 can be realized, so that the memory 13 can be not arranged in the embedded core board 11, and the size of the embedded core board 11 can be greatly reduced, so that the volume of the embedded core board 11 is more compact. In addition, by only arranging the core power module 114 on the embedded core board 11, the core power module 114 provides the corresponding power supply circuit of the core function, and the simplification of the power module is achieved, so that the core power module 114 on the embedded core board 11 is compared with the existing large power module with complete functions, and the size and weight are greatly reduced, and the size of the embedded core board 11 is further reduced, so that the volume of the embedded core board 11 is more compact.

[0043] An embodiment of the present application also provides an electronic device, including the above-mentioned embedded core board or the above-mentioned embedded motherboard.

[0044] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0045] In the present invention, unless otherwise clearly specified and limited, the terms "module", "setting", "installation", "connection", "connection", "fixation" and the like should be understood in a broad sense, for example, it can be a physical module or an abstractly divided functional module; it can be a fixed connection, a detachable connection, or an integrated one; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] It should be noted that, in the present utility model, unless otherwise clearly specified and limited, the first feature being "above" or "below" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0048] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An embedded core board, characterized in that: It includes a main control chip, a memory chip and a storage chip, wherein the storage chip includes a memory timing storage unit and a boot loader unit, and the memory timing storage unit is used to store memory timing data; The main control chip is connected to the memory chip, the boot loader unit in the storage chip and the memory timing storage unit, and the main control chip is used to obtain memory timing data from the memory timing storage unit and initialize the memory chip according to the memory timing parameters; The main control chip is provided with a first external interface, and the first external interface is used to connect to an extended storage medium.

2. The embedded core board according to claim 1, characterized in that: The main control chip is a CPU or a SoC processor.

3. The embedded core board according to claim 1, characterized in that: The memory chip is a DDR memory chip.

4. The embedded core board according to claim 1, characterized in that: The memory chip is a Nor Flash memory chip.

5. The embedded core board according to claim 1, characterized in that: The first external interface is an SDIO interface.

6. The embedded core board according to claim 1, characterized in that: The embedded core board also includes a core power module; The core power module is connected to the main control chip, the memory chip and the storage chip.

7. An embedded motherboard, characterized in that: Comprising a memory and an embedded core board as described in any one of claims 1 to 6; The memory is connected to the main control chip in the embedded core board.

8. The embedded motherboard according to claim 7, characterized in that: Also includes optional power supply module; The optional power supply module is connected to the main control chip, the memory chip and the storage chip in the embedded core board.

9. The embedded motherboard according to claim 7, characterized in that: Also includes a second external interface; The second external interface is connected to a corresponding terminal in the main control chip, and the external interface is used for communication with an external device.

10. The embedded motherboard according to claim 9, characterized in that: The second external interface includes one or more of a CAN interface, an RS485 interface, an HDMI interface, a USB interface and an Ethernet interface.

11. An electronic device, characterized in that: It comprises the embedded core board described in any one of claims 1-6 or the embedded motherboard described in any one of claims 7-10.

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