Laminated structure and semiconductor structure
By using a dense buffer layer with low water absorption in semiconductor manufacturing, the incomplete etching problem caused by water absorption in the buffer layer in traditional etching processes is solved, and a more efficient etching rate and more stable product is achieved. performance.
Patent Information
- Application Number
- CN202420018733.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-04
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2034-01-04
AI Technical Summary
In semiconductor manufacturing, in the traditional integrated etching process, the buffer layer absorbs water, causes the etching speed to slow down, and the contact holes formed are incomplete, affecting the performance of semiconductor devices.
Using conductive layer, dielectric layer, dense buffer layer and hard mask layer stacked from bottom to top, the water absorption rate of the dense buffer layer is less than that of ethyl silicate, including a dense layer and a buffer layer, and the dense layer is covered on the dielectric layer. to avoid water absorption and provide sufficient etching rate.
It effectively avoids incomplete etching problems, ensures etching rate, reduces product quality differences due to different cargo control time and waiting time, and improves the performance stability of semiconductor devices.
Smart Images
Figure CN222261053U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuit design and manufacturing, in particular to a stacked structure and a semiconductor structure. Background Art
[0002] In the semiconductor manufacturing process, an etching process is usually used to etch a film layer on a semiconductor substrate to form a desired structure. For example, an integrated etching process can be used to etch the film layer to form interconnected grooves and through holes.
[0003] However, in the traditional process of integrated etching technology, the buffer layer used will absorb water under long-term exposure, which can easily lead to structural instability and slow down the etching speed of the integrated etching process, resulting in incomplete opening of the contact holes formed in the integrated etching process, thereby affecting the performance of the semiconductor device. Utility Model Content
[0004] Based on this, the present disclosure provides a stacked structure and a semiconductor structure, which can effectively solve the problem of incomplete etching in the integrated etching process caused by water absorption of the buffer layer in the stacked structure.
[0005] In order to solve the above technical problems, according to some embodiments, one aspect of the present disclosure provides a stacked structure, which is applied to an integrated etching process, and the stacked structure includes a conductive layer, a dielectric layer, a dense buffer layer and a hard mask layer stacked in sequence from bottom to top; wherein the water absorption rate of the dense buffer layer is less than the water absorption rate of ethyl silicate.
[0006] In some embodiments, the dielectric layer includes a silicon oxycarbide layer.
[0007] In some embodiments, the dense buffer layer includes a dense layer and a buffer layer which are stacked; wherein the dense layer is located on a side of the buffer layer close to the dielectric layer, and the water absorption rate of the dense layer is lower than the water absorption rate of ethyl silicate.
[0008] In some embodiments, the thickness of the dense layer is greater than or equal to the thickness of the buffer layer; the thickness is the dimension along the stacking direction.
[0009] In some embodiments, the dense layer includes a silicon nitride layer or a silicon oxynitride layer; and the buffer layer includes an ethyl silicate layer.
[0010] In some embodiments, the dense buffer layer includes a hydrophobic buffer layer.
[0011] In some embodiments, the stacked structure further includes a barrier layer between the conductive layer and the dielectric layer.
[0012] In some embodiments, the conductive layer includes a metal layer; and the barrier layer includes a doped silicon carbide layer.
[0013] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, which includes a stacked structure in any of the above embodiments, and at least one etching structure arranged in the stacked structure; the etching structure includes a groove and a through hole; the groove passes through the hard mask layer and is at least partially located in the dense buffer layer; the through hole is located below the groove, connected to the groove, and passes through the dense buffer layer and the dielectric layer to expose the conductive layer; wherein the water absorption rate of the dense buffer layer is less than the water absorption rate of ethyl silicate.
[0014] In some embodiments, the stacked structure further includes a barrier layer located between the conductive layer and the dielectric layer; wherein the through hole further penetrates the barrier layer.
[0015] The unexpected technical effects of the utility model are:
[0016] In the disclosed embodiment, the stacked structure can be etched by an integrated etching process to obtain a semiconductor structure, wherein the etching structure in the semiconductor structure includes a groove and a through hole, wherein the groove is at least partially located in the dense buffer layer of the stacked structure, and the through hole located below the groove penetrates the dense buffer layer and the dielectric layer of the stacked structure and exposes the conductive layer of the stacked structure; thus, after the groove is formed, since the water absorption rate of the dense buffer layer is lower than the water absorption rate of ethyl silicate, the dense buffer layer exposed by the groove will not absorb a large amount of water during the waiting stage between the processes, and since the dense buffer layer covers the dielectric layer, it is also beneficial to avoid water absorption by the dielectric layer; therefore, when forming the through hole, the dense buffer layer can ensure a sufficient etching rate while providing a buffering effect, so as to avoid incomplete etching of the through hole due to water absorption by the buffer layer, and can effectively avoid product quality differences caused by short control time and different waiting times between processes during the processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 It is a cross-sectional schematic diagram of a laminated structure in the related art;
[0019] Figure 2 Zhongwei Figure 1 A schematic cross-sectional view of the structure obtained after a groove is formed in the structure shown;
[0020] Figure 3 Figure (a) is Figure 2Schematic diagram of crystal particles in the structure shown in (a) when the silicon oxycarbide layer does not absorb water, (b) is a schematic diagram of the cross-section of the structure shown in (a) after etching to form a through hole;
[0021] Figure 4 Figure (a) is Figure 2 Schematic diagram of crystal particles after the silicon oxycarbide layer absorbs water in the structure shown in (a); (b) is a schematic cross-sectional diagram of the structure obtained after etching to form a through hole in the structure shown in (a);
[0022] Figure 5 A schematic cross-sectional view of a stacked structure provided in one embodiment of the present disclosure;
[0023] Figure 6 For a Figure 5 A schematic cross-sectional view of a structure obtained after a photoresist layer is formed on the stacked structure shown;
[0024] Figure 7 For a Figure 5 The schematic cross-sectional view of the structure obtained after the stacked structure is formed with grooves;
[0025] Figure 8 For a Figure 5 A schematic cross-sectional view of a structure obtained after a through hole is formed in the stacked structure shown;
[0026] Fig. 9 is a cross-sectional schematic diagram of a stacked structure provided in another embodiment of the present disclosure;
[0027] Fig.10 For a Fig. 9 A schematic cross-sectional view of a structure obtained after a photoresist layer is formed on the stacked structure shown;
[0028] Fig.11 For a Fig. 9 The schematic cross-sectional view of the structure obtained after the stacked structure is formed with grooves;
[0029] Fig.12 For a Fig. 9 A schematic cross-sectional view of a structure obtained after a through hole is formed in the stacked structure shown;
[0030] Fig.13 The graph is a graph showing the change in curvature of a silicon oxycarbide layer, a stacked structure of ethyl silicate and silicon oxycarbide, and a stacked structure of silicon nitride and silicon oxycarbide as a function of standing time provided in an embodiment of the present disclosure.
[0031] Description of reference numerals:
[0032] 1. Stacked structure; 11. Conductive layer; 12. Dielectric layer; 13. Dense buffer layer; 131. Dense layer; 132. Buffer layer; 14. Hard mask layer; 15. Barrier layer; 16. Photoresist layer; 2. Etching structure; 21. Groove; 22. Through hole; 31. Metal layer; 32. Doped silicon carbide layer; 33. Silicon oxycarbide layer; 34. Ethyl silicate layer; 35. Mask layer; 4. Water molecules. DETAILED DESCRIPTION
[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0035] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and cannot be understood as having one number.
[0036] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0037] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.
[0038] In the integrated etching process, etching can be performed by Figure 1The stacked structure shown in the figure is used to form interconnected grooves and through holes. After the semiconductor process enters the copper process, the stacked structure may generally include a metal layer 31, a doped silicon carbide layer 32, a silicon carbide layer 33, an ethyl silicate layer 34 and a mask layer 35 stacked in sequence from bottom to top, wherein the ethyl silicate layer 34 is used to buffer the stress on the structure when forming the grooves 21 and the through holes 22. Figure 2 As shown, in the conventional process, after etching to form the groove 21, the ethyl silicate layer 34 is exposed. Figure 3 As shown in FIG. 2( a ), when the waiting time for subsequent through-hole formation is short, the ethyl silicate layer 34 will not absorb a large amount of water, so the etching rate will not be affected when the through-hole 22 is formed. Figure 3 As shown in FIG. 2( b ), the through hole 22 formed at this time can completely penetrate the silicon oxycarbide layer 33 and the doped silicon carbide layer 32 , and expose the metal layer 31 .
[0039] However, combined with Figure 3 Figure (a) and Figure 4 As shown in Figure (a), the crystal particles of the ethyl silicate layer 34 are relatively loose. When waiting for a long time to form a through hole, the long-term exposure causes water molecules 4 in the environment to enter the gaps between the crystal particles of the ethyl silicate layer 34, causing the ethyl silicate layer 34 to absorb a large amount of water, and the silicon oxycarbide layer 33 also absorbs the water in the ethyl silicate layer 34, resulting in a slow etching speed for the subsequent formation of the through hole. Figure 4 As shown in (b), the slow etching speed at this time will result in the formed through hole 22 being unable to penetrate the silicon oxycarbide layer 33 and the doped silicon carbide layer 32 to expose the metal layer 31, thereby affecting the performance of the semiconductor device.
[0040] The present disclosure aims to provide a stacked structure and a semiconductor structure, which can effectively solve the problem of incomplete etching in an integrated etching process caused by water absorption of a buffer layer in the stacked structure.
[0041] Please refer to Figure 5 and Fig. 9 According to some embodiments, one aspect of the present disclosure provides a stacked structure 1, which is applied to an integrated etching process, and the stacked structure 1 includes a conductive layer 11, a dielectric layer 12, a dense buffer layer 13 and a hard mask layer 14 stacked in sequence from bottom to top; wherein the water absorption rate of the dense buffer layer 13 is less than the water absorption rate of ethyl silicate.
[0042] It can be understood that since the water absorption rate of the dense buffer layer 13 is lower than that of ethyl silicate, the dense buffer layer 13 can be prevented from absorbing a large amount of water during the waiting period between processes, and since the dense buffer layer 13 covers the dielectric layer 12, the dielectric layer 12 can also be prevented from absorbing water, thereby ensuring a sufficient etching rate while providing a buffering effect, so as to avoid incomplete etching of the through holes formed in subsequent processes due to water absorption, and can effectively avoid product quality differences caused by short control time and different waiting times between processes during the processing.
[0043] In some embodiments, the conductive layer 11 includes a metal layer; illustratively, the metal layer includes a copper layer.
[0044] In some embodiments, the dielectric layer 12 includes a silicon oxycarbide layer. The silicon oxycarbide layer is a material with a low dielectric constant, which is beneficial for solving the RC delay problem.
[0045] In some embodiments, the stacked structure 1 further includes a barrier layer 15 located between the conductive layer 11 and the dielectric layer 12. For example, the barrier layer 15 includes a Nitride Doped Silicon Carbide (NDC) layer. The barrier layer 15 can block mutual diffusion between the conductive layer 11 and the dielectric layer 12.
[0046] For example, the hard mask layer 14 on the dense buffer layer 13 may be a single-layer structure or a multi-layer structure. In an embodiment where the hard mask layer 14 includes a multi-layer structure, the hard mask layer 14 may include a stacked bottom anti-reflective coating (BARC) layer, an anti-corrosion layer, and an anti-reflection coating (ARC), wherein the anti-corrosion layer may include a titanium nitride layer.
[0047] For example, the dense buffer layer 13 may be a single-layer structure or a multi-layer structure.
[0048] like Figure 5 As shown, in an embodiment where the dense buffer layer 13 is a multi-layer structure, the dense buffer layer 13 includes a dense layer 131 and a buffer layer 132 which are stacked; wherein the dense layer 131 is located on a side of the buffer layer 132 close to the dielectric layer 12, and the water absorption rate of the dense layer 131 is less than the water absorption rate of ethyl silicate.
[0049] It can be understood that since the water absorption rate of the dense layer 131 is lower than that of ethyl silicate, the dense layer 131 can be prevented from absorbing water, thereby preventing the etching rate from being reduced while the buffer layer 132 provides a buffering effect, thereby effectively solving the problem of incomplete etching of the through hole 22 due to water absorption.
[0050] In some embodiments, the thickness of the dense layer 131 is greater than or equal to the thickness of the buffer layer 132 to ensure the effect of the dense layer 131, which is more conducive to solving the problem of incomplete etching of the through hole 22 due to water absorption. It can be understood that the thickness is the dimension along the stacking direction. For example, the thickness is as follows: Figure 5 Y direction shown.
[0051] In some embodiments, the dense layer 131 includes a silicon nitride layer or a silicon oxynitride layer; and the buffer layer 132 includes a tetraethylorthosilicate (TEOS) layer.
[0052] like Fig. 9 As shown, in the embodiment where the dense buffer layer 13 is a single-layer structure, the dense buffer layer 13 includes a hydrophobic buffer layer. It can be understood that the hydrophobic buffer layer can play a role of both hydrophobicity and buffering, so as to effectively solve the problem of incomplete etching of the through hole 22 due to water absorption.
[0053] Illustratively, the hydrophobic buffer layer includes a silicon nitride layer or a silicon oxynitride layer.
[0054] Please combine Figures 5 to 8 as well as Figure 9~Figure 12 It is understood that some embodiments of the present disclosure also provide a semiconductor structure. The semiconductor structure includes the stacked structure 1 in any of the above embodiments, and at least one etching structure 2 disposed in the stacked structure 1. It is understood that the etching structure 2 can be prepared based on the stacked structure 1 using an integrated etching process, and the etching structure 2 can be used to form a Damascus structure.
[0055] By way of example, the etching structure 2 includes a groove 21 and a through hole 22; the groove 21 penetrates the hard mask layer 14 and is at least partially located in the dense buffer layer 13; the through hole 22 is located below the groove 21, is connected to the groove 21, and penetrates the dense buffer layer 13 and the dielectric layer 12 to expose the conductive layer 11; wherein the water absorption rate of the dense buffer layer 13 is less than the water absorption rate of ethyl silicate.
[0056] In the above embodiment, since the dense buffer layer 13 has a low water absorption rate, the dense buffer layer 13 can be prevented from absorbing water after the groove 21 is formed, and since the dense buffer layer 13 covers the dielectric layer 12, the dielectric layer 12 can also be prevented from absorbing water, and the etching rate can be ensured not to be reduced when the through hole 22 is formed while providing a buffering effect, thereby avoiding incomplete etching of the through hole 22 due to water absorption.
[0057] In some embodiments, the stacked structure 1 further includes a barrier layer 15 located between the conductive layer 11 and the dielectric layer 12; wherein the through hole 22 also penetrates the barrier layer 15. For example, the barrier layer 15 includes a doped silicon carbide layer. The barrier layer 15 can block the mutual diffusion between the conductive layer 11 and the dielectric layer 12.
[0058] By way of example, the dielectric layer 12 includes a silicon oxycarbide layer. The silicon oxycarbide layer is a material with a low dielectric constant, which is beneficial for solving the RC delay problem.
[0059] For example, the semiconductor structure further includes a photoresist layer 16 , and the pattern in the photoresist layer 16 defines the shape and position of the groove 21 , which can be used to define the shape and position of the groove 21 during the process of forming the groove 21 .
[0060] Please combine the following Figures 5 to 8 It is understood that in an embodiment where the dense buffer layer 13 is a multi-layer structure, the dense buffer layer 13 includes a dense layer 131 and a buffer layer 132 which are stacked; wherein the dense layer 131 is located on the side of the buffer layer 132 close to the dielectric layer 12, and the water absorption rate of the dense layer 131 is less than the water absorption rate of ethyl silicate.
[0061] It can be understood that since the water absorption rate of the dense layer 131 is lower than that of ethyl silicate, the dense layer 131 can be prevented from absorbing water, thereby preventing the etching rate from being reduced while the buffer layer 132 provides a buffering effect, so as to effectively solve the problem of incomplete etching of the through hole 22 due to water absorption, and can effectively avoid product quality differences caused by short control time and different waiting times between processes during the processing.
[0062] In some embodiments, the thickness of the dense layer 131 is greater than or equal to the thickness of the buffer layer 132 to ensure the effect of the dense layer 131, which is more conducive to solving the problem of incomplete etching of the through hole 22 due to water absorption. It can be understood that the thickness is the dimension along the stacking direction. For example, the thickness is as follows: Figure 5 Y direction shown.
[0063] In some embodiments, the dense layer 131 includes a silicon nitride layer or a silicon oxynitride layer; and the buffer layer 132 includes an ethyl silicate layer.
[0064] Based on Figure 5 When the stacked structure 1 shown in FIG. 1 is formed into a semiconductor structure, Figure 6 As shown, the photoresist layer 16 includes a pattern defining the shape and position of the groove 21, such as Figure 7 As shown, the hard mask layer 14 and the dense buffer layer 13 are etched to transfer the pattern in the photoresist to the hard mask layer 14 and the dense buffer layer 13 to form a groove 21. At this time, the dense layer 131 in the dense buffer layer 13 at the bottom of the groove 21 is exposed. Since the dense layer 131 has good hydrophobicity, it is further formed as shown in FIG. Figure 8 When the through hole 22 is formed, the etching rate can be guaranteed, so that the through hole 22 is completely opened and the conductive layer 11 is exposed, thereby effectively solving the problem that the through hole 22 is not completely opened due to water absorption by the buffer layer 132 .
[0065] Please combine the following Figures 9 to 12 It is understood that in the stacked structure 1 including the dense buffer layer 13 having a single-layer structure, the dense buffer layer 13 includes, for example, a hydrophobic buffer layer. The hydrophobic buffer layer can simultaneously play the role of hydrophobicity and buffering, so as to effectively solve the problem of incomplete etching of the through hole 22 due to water absorption.
[0066] Illustratively, the hydrophobic buffer layer includes a silicon nitride layer or a silicon oxynitride layer.
[0067] Based on Fig. 9 When the stacked structure 1 shown in FIG. 1 is formed into a semiconductor structure, Fig.10 As shown, the photoresist layer 16 includes a pattern defining the shape and position of the groove 21, such as Fig.11 As shown, the hard mask layer 14 and the dense buffer layer 13 are etched to transfer the pattern in the photoresist to the hard mask layer 14 and the dense buffer layer 13 to form a groove 21. At this time, the dense buffer layer 13 at the bottom of the groove 21 is exposed. Since the dense buffer layer 13 has good hydrophobicity, the dense buffer layer 13 is further formed. Fig.12 When the through hole 22 is formed, the etching rate can be guaranteed, so that the through hole 22 is completely opened and the conductive layer 11 is exposed, thereby effectively solving the problem of incomplete opening of the through hole 22 due to water absorption by the buffer layer.
[0068] In order to clearly illustrate the etching effect of the stacked structure in the embodiment of the present disclosure to form an etched structure under the integrated etching process, Fig.13 Taking the silicon oxycarbide layer as the dielectric layer as an example, the changes in the curvature of the silicon oxycarbide layer, the stacked structure of ethyl silicate and silicon oxycarbide, and the stacked structure of silicon nitride and silicon oxycarbide as the standing time are detected and illustrated, wherein curve 1 is a curve showing the change in the curvature of the silicon oxycarbide layer as the standing time, curve 2 is a curve showing the change in the curvature of the stacked structure of silicon oxycarbide and ethyl silicate as the standing time, and curve 3 is a curve showing the change in the curvature of the stacked structure of silicon oxycarbide and silicon nitride as the standing time.
[0069] It is worth mentioning that bow is used to characterize the curvature of wafers in semiconductor manufacturing. Bow can be defined by measuring the maximum deviation between the center and edge of the wafer, that is, the deviation between the minimum and maximum values of the surface of the center point of the wafer from the reference plane when the wafer is not tightly attached. The deviation includes concave and convex shapes. The concave bow is a negative value, and the convex bow is a positive value.
[0070] Moreover, in the stacked structure provided in the embodiment of the present disclosure, regardless of whether the dense buffer layer adopts a single-layer structure or a multi-layer structure as in the above example, after the groove is formed, the corresponding structure of the dielectric layer and the dense buffer layer remaining on its surface can be expressed as a stacked structure of silicon carbide oxide and silicon nitride.
[0071] Through comparative analysis Fig.13 From curve 1, curve 2 and curve 3 in the figure, we can see that Fig.13 As shown in curve 1 in , although the curvature of the silicon oxycarbide layer changes slightly with the static time, the absolute value of the curvature of the silicon oxycarbide layer is large, which is not conducive to structural stability; Fig.13 As shown in curve 2 in , although the absolute value of the curvature of the laminated structure of silicon oxycarbide and ethyl silicate is small, the laminated structure of silicon oxycarbide and ethyl silicate will absorb a large amount of water after being left standing for a period of time, and the water absorption will cause a sudden change in the curvature of the structure, that is, the curvature of the laminated structure of silicon oxycarbide and ethyl silicate changes greatly with the standing time, resulting in a large difference in the quality of the product obtained by the integrated etching process due to the different waiting times between the processes, which is not conducive to the stability of product performance and reduces the product yield; Fig.13 As shown in curve 3 in the figure, the curvature of the stacked structure of silicon carbide oxide and silicon nitride used in the embodiment of the present disclosure changes little with the standing time. Therefore, during the integrated etching process, the stacked structure of silicon carbide oxide and silicon nitride can obtain a more stable structure while ensuring a low water absorption rate.
[0072] In summary, the unexpected technical effects of the utility model are:
[0073] In the disclosed embodiment, the stacked structure can be etched by an integrated etching process to obtain a semiconductor structure, wherein the etching structure in the semiconductor structure includes a groove and a through hole, wherein the groove is at least partially located in the dense buffer layer of the stacked structure, and the through hole located below the groove penetrates the dense buffer layer and the dielectric layer of the stacked structure and exposes the conductive layer of the stacked structure; thus, after the groove is formed, since the water absorption rate of the dense buffer layer is lower than the water absorption rate of ethyl silicate, the dense buffer layer exposed by the groove will not absorb a large amount of water during the waiting stage between the processes, and since the dense buffer layer covers the dielectric layer, it is also beneficial to avoid water absorption by the dielectric layer; therefore, when forming the through hole, the dense buffer layer can ensure a sufficient etching rate while providing a buffering effect, so as to avoid incomplete etching of the through hole due to water absorption by the buffer layer, and can effectively avoid product quality differences caused by short control time and different waiting times between processes during the processing.
[0074] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
[0075] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0076] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0077] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.
Claims
1. A laminated structure, characterized in that: Applied to an integrated etching process, the stacked structure comprises a conductive layer, a dielectric layer, a dense buffer layer and a hard mask layer stacked in sequence from bottom to top; Wherein, the water absorption rate of the dense buffer layer is lower than the water absorption rate of ethyl silicate.
2. The laminate structure according to claim 1, characterized in that The dielectric layer includes a silicon oxycarbide layer.
3. The laminate structure according to claim 2, characterized in that: The dense buffer layer comprises: a dense layer and a buffer layer stacked in layers; The dense layer is located on a side of the buffer layer close to the dielectric layer, and the water absorption rate of the dense layer is lower than the water absorption rate of ethyl silicate.
4. The laminate structure according to claim 3, characterized in that The thickness of the dense layer is greater than or equal to the thickness of the buffer layer; the thickness is the dimension along the stacking direction.
5. The laminate structure according to claim 3, characterized in that: The dense layer includes a silicon nitride layer or a silicon nitride oxide layer; and the buffer layer includes an ethyl silicate layer.
6. The laminate structure according to claim 2, characterized in that: The dense buffer layer includes a hydrophobic buffer layer.
7. The laminated structure according to any one of claims 1 to 6, characterized in that: Also included is a barrier layer located between the conductive layer and the dielectric layer.
8. The laminate structure according to claim 7, characterized in that The conductive layer includes a metal layer; and the barrier layer includes a doped silicon carbide layer.
9. A semiconductor structure, characterized in that: include: The stacked structure according to any one of claims 1 to 8, and at least one etching structure arranged in the stacked structure; the etching structure comprises: a groove, penetrating the hard mask layer and at least partially located in the dense buffer layer; a through hole, located below the groove, communicating with the groove, and penetrating the dense buffer layer and the dielectric layer to expose the conductive layer; Wherein, the water absorption rate of the dense buffer layer is lower than that of ethyl silicate.
10. The semiconductor structure according to claim 9, wherein: The stacked structure further includes a barrier layer located between the conductive layer and the dielectric layer; Wherein, the through hole also penetrates the barrier layer.