Integrated circuit device

Abstract

Various embodiments of the utility model relate to an integrated circuit device. The integrated circuit device comprises a first type active region semiconductor structure and a second type active region semiconductor structure which extend in a first direction. The second type active region semiconductor structure and the first type active region semiconductor structure are stacked. The integrated circuit device also includes a front side conductive layer over the two active region semiconductor structures and a back side conductive layer under the two active region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device also includes a first source conductive section connected to the front side power rail and a second source conductive section connected to the back side power rail.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated circuit device. Background Art

[0002] An integrated circuit (IC) typically includes a plurality of IC devices fabricated according to one or more IC layouts. An IC device sometimes includes a complementary field effect transistor (CFET) device. A CFET device generally has an upper FET overlying a lower field effect transistor (FET) in a stacked configuration. Both the upper FET and the lower FET in a CFET device are positioned above a conductive line in a backside conductive layer, but below a conductive line in a frontside conductive layer. Utility Model Content

[0003] One aspect of the utility model provides an integrated circuit device. The integrated circuit device includes: a first type active region semiconductor structure extending in a first direction; a first conductive segment extending in a second direction perpendicular to the first direction and intersecting with the first type active region semiconductor structure at a source region of a first type transistor; a second type active region semiconductor structure extending in the first direction, stacked with the first type active region semiconductor structure, and offset from the first type active region semiconductor structure along a third direction perpendicular to both the first direction and the second direction; a second conductive segment extending in the second direction and intersecting with the second type active region semiconductor structure at a source region of the second type transistor; a front conductive layer extending in a second direction and intersecting with the second type active region semiconductor structure at a source region of the second type transistor; and a front conductive layer extending in a second direction and intersecting with the second type active region semiconductor structure at a source region of the second type transistor. direction, positioned above the first type active region semiconductor structure and the second type active region semiconductor structure; a back-side conductive layer, oriented toward a third direction, positioned below the first type active region semiconductor structure and the second type active region semiconductor structure; a front-side power rail, extending in the front-side conductive layer in the second direction, configured to maintain a first supply voltage; a back-side power rail, extending in the back-side conductive layer in the second direction, configured to maintain a second supply voltage; a first through-hole connector, directly connected between the first conductive segment and the front-side power rail; and a second through-hole connector, directly connected between the second conductive segment and the back-side power rail.

[0004] Another aspect of the utility model provides an integrated circuit device. The integrated circuit device includes: a first type active region semiconductor structure extending in a first direction; a second type active region semiconductor structure extending in the first direction and stacked with the first type active region semiconductor structure; a front side conductive layer located above the first type active region semiconductor structure and the second type active region semiconductor structure; a back side conductive layer located below the first type active region semiconductor structure and the second type active region semiconductor structure; a plurality of gate conductors extending in a second direction perpendicular to the first direction, each of the plurality of gate conductors intersecting with one or both of the first type active region semiconductor structure and the second type active region semiconductor structure, and being constructed as a gate terminal of at least one transistor, wherein adjacent gate conductors of the plurality of gate conductors are separated by a pitch distance of a contact poly pitch (“CPP”); a plurality of conductive segments extending in the second direction, each of the plurality of conductive segments intersecting with the first type active region semiconductor structure and the second type active region semiconductor structure one or both of which intersect and are constructed as a source terminal or a drain terminal of at least one transistor; a plurality of front power rails extending in the second direction in the front conductive layer, wherein the front power rails of the plurality of front power rails are configured to maintain a first supply voltage; a plurality of rear power rails extending in the second direction in the rear conductive layer, wherein the rear power rails of the plurality of rear power rails are configured to maintain a second supply voltage; a plurality of front signal lines located between adjacent front power rails of the plurality of front power rails, wherein each of the plurality of front signal lines extends in the second direction in the front conductive layer and occupies a front conductor track selected from a plurality of front conductor tracks equally spaced apart; and a plurality of rear signal lines located between adjacent rear power rails of the plurality of rear power rails, wherein each of the plurality of rear signal lines extends in the second direction in the rear conductive layer and occupies a rear conductor track selected from a plurality of rear conductor tracks equally spaced apart.

[0005] Another aspect of the utility model provides a method for manufacturing an integrated circuit device. The method includes: manufacturing a first type active region semiconductor structure extending in a first direction on a substrate; manufacturing a first conductive segment intersecting the first type active region semiconductor structure at a first source region of a first type transistor; manufacturing a second type active region semiconductor structure extending in the first direction on top of a dielectric material layer, wherein the second type active region semiconductor structure is stacked with the first type active region semiconductor structure; manufacturing a second conductive segment intersecting the second type active region semiconductor structure at a second source region of a second type transistor; depositing a front side metal layer on a first insulating material and patterning the front side metal layer to form a front side power rail, wherein the front side power rail extends in a second direction perpendicular to the first direction, and wherein the front side power rail is conductively connected to the second conductive segment through a front side through-hole connector; and forming a back side metal layer on a back side of the substrate and patterning the back side metal layer to form a back side power rail extending in the second direction, wherein the back side power rail is conductively connected to the first conductive segment through a back side through-hole connector.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram of an inverter circuit according to some embodiments.

[0008] FIG. 2A to FIG. 2B According to some embodiments Figure 1 Layout diagram of the inverter circuit shown in FIG.

[0009] FIG. 3A to FIG. 3C According to some embodiments Figure 1 The inverter circuit shown is composed of FIG. 2A to FIG. 2B Cross-sectional views in various cutting planes as indicated in the layout shown.

[0010] FIG. 4A to FIG. 4B According to some embodiments Figure 1 The inverter circuit shown is composed of FIG. 2A to FIG. 2B Cross-sectional views in various cutting planes as indicated in the layout shown.

[0011] FIG. 5A to FIG. 5B is a layout diagram of an inverter circuit according to some embodiments.

[0012] FIG. 6A to FIG. 6B is a layout diagram of an inverter circuit according to some embodiments.

[0013] FIG. 7A to FIG. 7B is a layout diagram of an inverter circuit according to some embodiments.

[0014] FIG. 8A to FIG. 8C is a layout diagram of an integrated circuit having columns formed of circuit cells according to some embodiments.

[0015] Fig. 9 is a layout diagram of an integrated circuit having a plurality of columns formed of circuit cells according to some embodiments.

[0016] FIG. 10A to FIG. 10B is a layout diagram of an inverter circuit according to some embodiments.

[0017] Fig. 10C The inverter circuit according to some embodiments is composed of FIG. 10A to FIG. 10B Cross-sectional view in the cutting plane indicated in the layout shown.

[0018] FIG. 11A to FIG. 11B is a layout diagram of a NAND circuit according to some embodiments.

[0019] FIG. 12A to FIG. 12B is a layout diagram of an AND-OR-Inverter ("AOI") circuit according to some embodiments.

[0020] FIG. 13A to FIG. 13B is a layout diagram of an inverter circuit according to some embodiments.

[0021] FIG. 13C to FIG. 13D According to some embodiments FIG. 13A to FIG. 13B A cross-sectional view of the inverter circuit shown.

[0022] FIG. 14A to FIG. 14B is a layout diagram of an INVER circuit according to some embodiments.

[0023] FIG. 15A to FIG. 15B is a layout diagram of an AOI circuit according to some embodiments.

[0024] FIG. 16A to FIG. 16C are schematic diagrams of various designs of power rails in three metal layers according to some embodiments.

[0025] Fig.17 is a flow chart of a method 1700 of fabricating an integrated circuit (IC) having a CFET device, according to some embodiments.

[0026] Fig.18 is a block diagram of an electronic design automation (EDA) system 1800 according to some embodiments.

[0027] Fig.19 is a block diagram of an integrated circuit (IC) manufacturing system 1900 and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0028] The present invention provides many different embodiments or examples for implementing the different features of the provided target. The following describes specific examples of components, materials, values, steps, operations, arrangements or similar elements to simplify the present invention. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements or similar elements. For example, in the following description, forming a first feature on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0029] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0030] A complementary field effect transistor (CFET transistor) generally has a stacked first type transistor and a second type transistor. The first type transistor has a channel region located in a first type active region semiconductor structure, and the second type transistor has a channel region located in a second type active region semiconductor structure. An IC device having a CFET transistor generally includes a front side conductive layer located above the CFET transistor and a back side conductive layer located below the CFET transistor. In some embodiments, each of the first type active region semiconductor structure and the second type active region semiconductor structure extends in a first direction. The layout design of the front side power rail in the first front side conductive layer with the front side signal line affects the layout area of ​​the circuit cell. The layout design of the back side power rail in the first back side conductive layer with the back side signal line also affects the layout area of ​​the circuit cell. When the front side power rail in the first front side conductive layer and / or the back side power rail in the first back side conductive layer extend in a second direction perpendicular to the first direction, some embodiments of the circuit cell have a reduced cell height while preventing an additional increase in the current-resistance (IR) drop in the power rail.

[0031] Figure 1 1 is a diagram of an inverter circuit 100 implemented using CFETs according to some embodiments, the inverter circuit 100 having power rails and signal lines in both the front side conductive layer and the back side conductive layer. The inverter circuit 100 includes a p-type metal oxide semiconductor (PMOS) transistor T1p and an n-type metal oxide semiconductor (NMOS) transistor T1n. The gate terminal of the PMOS transistor T1p is connected to the gate terminal of the NMOS transistor T1n and serves as an input terminal of the inverter. The drain terminal of the PMOS transistor T1p is connected to the drain terminal of the NMOS transistor T1n and serves as an output terminal of the inverter. The source terminal of the PMOS transistor T1p and the source terminal of the NMOS transistor T1n are maintained at an upper supply voltage VDD and a lower supply voltage VSS, respectively.

[0032] exist Figure 1 In FIG. 1 , the inverter circuit 100 includes a p-type active region semiconductor structure 50 p extending in the X direction and an n-type active region semiconductor structure 50 n extending in the X direction. Figure 1 The X direction, Y direction and Z direction in the structure are mutually orthogonal and form an orthogonal coordinate frame. The p-type active region semiconductor structure 50p is stacked with the n-type active region semiconductor structure 50n and is offset from the n-type active region semiconductor structure along the Z direction. The gate conductor 150 extending in the Y direction intersects both the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n. The gate conductor 150 serves as two stacked gate conductors conductively connected together: one of the two gate conductors intersects with the p-type active region semiconductor structure 50p at the channel region of the PMOS transistor T1p, and the other of the two gate conductors intersects with the n-type active region semiconductor structure 50n at the channel region of the NMOS transistor T1n. The gate conductor 150 is conductively connected to the gate terminal of the PMOS transistor T1p and the gate terminal of the NMOS transistor T1n.

[0033] In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more nano-sheets, and thus, each of the PMOS transistor T1p and the NMOS transistor T1n is a nanosheet transistor. In some embodiments, each of the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n includes one or more nano-wires, and thus, each of the PMOS transistor T1p and the NMOS transistor T1n is a nanowire transistor.

[0034] exist Figure 1 In the embodiment, the inverter circuit 100 also includes conductive segments 132p, 134p, 132n and 134n. Each of the conductive segments 132p and 134p extending in the Y direction intersects with the p-type active region semiconductor structure 50p at one of the terminal regions of the PMOS transistor T1p. Each of the conductive segments 132n and 134n extending in the Y direction intersects with the n-type active region semiconductor structure 50n at one of the terminal regions of the NMOS transistor T1n. The terminal region of the transistor is the source region or the drain region of the transistor. The conductive segment 132p as the source conductive segment forms the source terminal of the PMOS transistor T1p. The conductive segment 132n as the source conductive segment forms the source terminal of the NMOS transistor T1n. The conductive segment 134p as the drain conductive segment forms the drain terminal of the PMOS transistor T1p. Conductive segment 134n, which is a drain conductive segment, forms a drain terminal of NMOS transistor T1n. Conductive segment 134p is conductively connected to conductive segment 134n through a conductive-segment inter-connector VMD. Although the drain terminal of PMOS transistor T1p and the drain terminal of NMOS transistor T1n are conductively connected together through the conductive-segment inter-connector VMD, the source terminal of PMOS transistor T1p is conductively connected to front power rail 30F through front via connector VD, and the source terminal of NMOS transistor T1n is conductively connected to back power rail 30B through back via connector VDb. Front power rail 30F is configured to be maintained at a high supply voltage VDD, and back power rail 30B is configured to be maintained at a low supply voltage VSS.

[0035] The front power rail 30F extending in the Y direction is located in the front conductive layer. The rear power rail 30B extending in the Y direction is located in the rear conductive layer. Each of the front conductive layer and the rear conductive layer is located in a plane having a normal vector oriented toward the Z direction. The front conductive layer is located above both the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n. The rear conductive layer is located below both the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n. In some embodiments, the rear conductive layer is fabricated on a substrate as a buried conductive layer, and then, the n-type active region semiconductor structure 50n is fabricated above the buried conductive layer. Subsequently, the p-type active region semiconductor structure 50p is fabricated above the n-type active region semiconductor structure 50n, and the front conductive layer is fabricated above the p-type active region semiconductor structure 50p. Other arrangements of the rear conductive layer are also within the intended scope of the present invention.

[0036] exist Figure 1 , the inverter circuit 100 includes front signal lines 174F and 176F located in the front conductive layer and also includes back signal lines 174B and 176B located in the back conductive layer. Each of the front signal lines 174F and 176F and the back signal lines 174B and 176B extends in the Y direction. The front signal line 174F is conductively connected to the gate conductor 150 through the front through-hole connector VG and is configured as an input signal line of the inverter circuit. The front signal line 176F is conductively connected to the conductive segment 134p through the through-hole connector VD and is configured as an output signal line of the inverter circuit. The front power rail 30F is conductively connected to the conductive segment 132p through the front through-hole connector VD, and the back power rail 30B is conductively connected to the conductive segment 132n through the back through-hole connector VDb.

[0037] In some embodiments, even if Figure 1 The backside signal lines 174B and 176B in the inverter circuit 100 are not directly connected to any circuit node in the inverter circuit 100, and the backside signal lines 174B and 176B are also configured to route signals between adjacent cells located at opposite sides of the inverter circuit. For example, in some embodiments, a signal is transmitted from a first adjacent cell located at a first side of the inverter circuit 100 to a second adjacent cell located at a second side of the inverter circuit 100 via one of the backside signal lines 174B and 176B along the Y direction.

[0038] FIG. 2A to FIG. 2B According to some embodiments Figure 1 Schematic diagram of the inverter circuit 100 is shown in FIG. Figure 2AThe illustrated layout includes layout patterns for indicating p-type active region semiconductor structure 50p, gate conductor 150, conductive segments 132p and 134p, front side signal lines 174F and 176F, front side power rail 30F, conductive segment intermediate connector VMD, and various through-hole connectors. Figure 2B The illustrated layout diagram includes layout patterns for indicating n-type active region semiconductor structure 50n, gate conductor 150, conductive segments 132n and 134n, backside signal lines 174B and 176B, backside power rail 30B, conductive segment intermediate connector VMD, and various through-hole connectors.

[0039] Figure 2A The layout diagram shown indicates that each of the p-type active region semiconductor structure 50p, the front side signal lines 174F and 176F, and the front side power rail 30F extends in the Y direction. The gate conductor 150 extending in the Y direction intersects the p-type active region semiconductor structure 50p at the channel region of the PMOS transistor T1p. The conductive segment 132p extending in the Y direction intersects the p-type active region semiconductor structure 50p at the source region of the PMOS transistor T1p. The conductive segment 134p extending in the Y direction intersects the p-type active region semiconductor structure 50p at the drain region of the PMOS transistor T1p.

[0040] The via connector pattern VD overlapping both the conductive segment 132p and the front side power rail 30F indicates that the conductive segment 132p and the front side power rail 30F are conductively connected together through the front side via connector VD. The top via connector pattern VG overlapping both the gate conductor 150 and the front side signal line 174F indicates that the gate conductor 150 and the front side signal line 174F are conductively connected together through the front side via connector VG. The via connector pattern VD overlapping both the conductive segment 134p and the front side signal line 176F indicates that the conductive segment 134p and the front side signal line 176F are conductively connected together through the front side via connector VD.

[0041] Figure 2BThe layout diagram shown indicates that each of the n-type active region semiconductor structure 50n, the backside signal lines 174B and 176B, and the backside power rail 30B extends in the X direction. The gate conductor 150 extending in the Y direction intersects the n-type active region semiconductor structure 50n at the channel region of the NMOS transistor T1n. The conductive segment 132n extending in the Y direction intersects the n-type active region semiconductor structure 50n at the source region of the NMOS transistor T1n. The conductive segment 134n extending in the Y direction intersects the n-type active region semiconductor structure 50n at the drain region of the NMOS transistor T1n. The via connector pattern VDb overlapping both the conductive segment 132n and the backside power rail 30B indicates that, in the inverter circuit 100, the conductive segment 132n and the backside power rail 30B are conductively connected together through the backside via connector VDb.

[0042] Figure 2A The middle connection pattern VMD in the embodiment (which overlies the conductive segment 134p) and Figure 2B The intermediate connector patterns VMD in the layout diagram (which overlie the conductive segment 134n) match each other at the same position in the XY coordinates. The matching intermediate connector patterns VMD in the layout diagram indicate that the conductive segments 134p and 134n in the inverter circuit 100 are conductively connected together through the conductive segment intermediate connector VMD.

[0043] Figure 3A According to some embodiments Figure 1 The inverter circuit 100 shown is composed of FIG. 2A to FIG. 2B The cross-sectional view is in the cutting plane indicated by the line PP' in the illustrated layout. Figure 3B According to some embodiments Figure 1 The inverter circuit 100 shown is composed of FIG. 2A to FIG. 2B The cross-sectional view in the cutting plane indicated by the line Q-Q' in the illustrated layout. Figure 3C According to some embodiments Figure 1 The inverter circuit 100 shown is composed of FIG. 2A to FIG. 2B The cross-sectional view is in the cutting plane indicated by the line RR' in the illustrated layout. Figure 4A According to some embodiments Figure 1 The inverter circuit 100 shown is composed of FIG. 2A to FIG. 2B The cross-sectional view is in the cutting plane indicated by the line AA' in the illustrated layout. Figure 4B According to some embodiments Figure 1 The inverter circuit 100 shown is composed of FIG. 2A to FIG. 2B The cross-sectional view is in the cutting plane indicated by the line BB' in the illustrated layout.

[0044] exist FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4BIn the embodiment, the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n are stacked. The front signal lines 174F and 176F and the front power rail 30F are located in the front conductive layer, which is located above the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n. The rear signal lines 174B and 176B and the rear power rail 30B are located in the rear conductive layer, which is located below the p-type active region semiconductor structure 50p and the n-type active region semiconductor structure 50n.

[0045] In the cross-sectional view of the P-P' cutting plane, Figure 3A As shown in , the conductive segment 132p intersects the P-type active region semiconductor structure 50p at the source region of the PMOS transistor, and the conductive segment 132n intersects the n-type active region semiconductor structure 50n at the source region of the NMOS transistor. The conductive segment 132p is conductively connected to the front power rail 30F through the front via connector VD, and the conductive segment 132n is conductively connected to the back power rail 30B through the back via connector VDb.

[0046] In the cross-sectional view of the Q-Q' cutting plane, Figure 3B As shown in , the conductive segment 134p intersects with the p-type active region semiconductor structure 50p at the drain region of the PMOS transistor, and the conductive segment 134n intersects with the n-type active region semiconductor structure 50n at the drain region of the NMOS transistor. The conductive segment 134n is conductively connected to the front signal line 176F through the front through-hole connector VD. The conductive segment 134p is conductively connected to the conductive segment 134n through the conductive segment intermediate connector VMD.

[0047] In the cross-sectional view of the R-R' cutting plane, Figure 3C As shown in FIG. 1 , the gate conductor 150 intersects the p-type active region semiconductor structure 50p at the channel region of the PMOS transistor and intersects the n-type active region semiconductor structure 50n at the channel region of the NMOS transistor. The front side signal line 174F is conductively connected to the gate conductor 150 through the front side via connector VG.

[0048] exist Figure 4A The A-A' cutting plane and Figure 4BIn the cross-sectional view of the BB' cutting plane in FIG. 1 , the front signal lines 174F and 176F and the front power rail 30F are located in the front conductive layer, while the back signal lines 174B and 176B and the back power rail 30B are located in the back conductive layer. The gate conductor 150 and the conductive segments 132p, 132n, 134n and 134p are all located between the front conductive layer and the back conductive layer. The front power rail 30F is aligned with the conductive segment 132p located below the front conductive layer, the front signal line 174F is aligned with the gate conductor 150 located below the front conductive layer, and the front signal line 176F is aligned with the conductive segment 134p located below the front conductive layer. Backside power rail 30B is aligned with conductive segment 132n over the backside conductive layer, backside signal line 174B is aligned with gate conductor 150 over the backside conductive layer, and backside signal line 176B is aligned with conductive segment 134n over the backside conductive layer.

[0049] exist Figure 4A In the cross-sectional view of the AA' cutting plane in FIG. 1 , the front power rail 30F is conductively connected to the conductive segment 132p through the front through-hole connector VD, and the front signal line 176F is conductively connected to the conductive segment 134p through the through-hole connector VD. The back power rail 30B is conductively connected to the conductive segment 132n through the back through-hole connector VDb.

[0050] exist Figure 4B In the cross-sectional view of the BB' cutting plane in FIG. 1 , the front side signal line 174F is conductively connected to the gate conductor 150 through the front side via connector VG. The conductive segment 134p is conductively connected to the conductive segment 134n through the conductive segment intermediate connector VMD.

[0051] In some embodiments, Figure 1 The inverter circuit 100 shown in FIG. 1 is implemented in a circuit cell. FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B and FIG. 7A to FIG. 7B is a layout diagram of a circuit cell having the inverter circuit 100 according to some embodiments.

[0052] exist FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B and FIG. 7A to FIG. 7B In each layout diagram of FIG. 1 , a vertical cell boundary 101 of a circuit cell is aligned with a dummy gate conductor 151, and a vertical cell boundary 109 of a circuit cell is aligned with a dummy gate conductor 159. Each of the dummy gate conductors 151 and 159 is separated from the gate conductor 150 by a pitch distance equal to one contacted poly pitch (“Contacted PolyPitch”, CPP) distance.

[0053] The vertical cell boundary 101 (which extends in the Y direction) passes through the boundary isolation region 101pI in the p-type active region semiconductor structure 50p and through the boundary isolation region 101nI in the n-type active region semiconductor structure 50n. The boundary isolation region 101pI is discernible at the intersection between the dummy gate conductor 151 and the p-type active region semiconductor structure 50p, while the boundary isolation region 101nI is discernible at the intersection between the dummy gate conductor 151 and the n-type active region semiconductor structure 50n.

[0054] The vertical cell boundary 109 (which extends in the Y direction) passes through a boundary isolation region 109pI in the p-type active region semiconductor structure 50p and through a boundary isolation region 109nI in the n-type active region semiconductor structure 50n. The boundary isolation region 109pI is discernible at the intersection between the dummy gate conductor 159 and the p-type active region semiconductor structure 50p, while the boundary isolation region 109nI is discernible at the intersection between the dummy gate conductor 159 and the n-type active region semiconductor structure 50n.

[0055] Due to the boundary isolation regions 101pI and 109pI, the active regions (e.g., source regions, channel regions, and drain regions) of the PMOS transistors in the circuit cells between the vertical cell boundaries 101 and 109 (which have the inverter circuit 100) are isolated from the active regions of the neighboring cells in the p-type active region semiconductor structure 50p. Similarly, due to the boundary isolation regions 101nI and 109nI, the active regions (e.g., source regions, channel regions, and drain regions) of the NMOS transistors in the circuit cells between the vertical cell boundaries 101 and 109 (which have the inverter circuit 100) are isolated from the active regions of the neighboring cells in the n-type active region semiconductor structure 50n. Various suitable techniques for creating boundary isolation regions in the active region semiconductor structure (50p or 50n) are within the intended scope of the present invention. For example, in some embodiments, the border isolation region in the active region semiconductor structure (50p or 50n) is created based on the continuous poly on oxide definition edge (CPODE) technology. In some other embodiments, the border isolation region in the active region semiconductor structure (50p or 50n) is created based on the poly on oxide definition edge (PODE) technology.

[0056] FIG. 5A to FIG. 5B The layout diagram in the FIG. 2A to FIG. 2B The modification includes using the layout diagram of FIG. 2A to FIG. 2B1 and 179B. The inverter circuit 100 is implemented according to the layout indicated by the layout diagram in FIG. 1 , and dummy gate conductors 151 and 159 are added correspondingly at the vertical cell boundaries 101 and 109 of the circuit cell having the inverter circuit 100. The modification also includes adding front signal lines 171F and 179F in the front conductive layer and adding back signal lines 171B and 179B in the back conductive layer. The front signal lines 171F and 179F are aligned with the vertical cell boundaries 101 and 109, respectively, and each of the front signal lines 171F and 179F extends in the Y direction in the front conductive layer. The back signal lines 171B and 179B are aligned with the vertical cell boundaries 101 and 109, respectively, and each of the back signal lines 171B and 179B extends in the Y direction in the back conductive layer.

[0057] In some embodiments, the front signal line 171F is separated from the front power rail 30F by a pitch distance of 0.5 CPP, the front signal line 179F is separated from the front signal line 176F by a pitch distance of 0.5 CPP, and the front signal line 174F is separated from each of the front signal line 176F and the front power rail 30F by a pitch distance of 0.5 CPP. In some embodiments, the back signal line 171B is separated from the back power rail 30B by a pitch distance of 0.5 CPP, the back signal line 179B is separated from the back signal line 176B by a pitch distance of 0.5 CPP, and the back signal line 174B is separated from each of the back signal line 176B and the back power rail 30B by a pitch distance of 0.5 CPP.

[0058] FIG. 6A to FIG. 6B The layout diagram in the FIG. 5A to FIG. 5B The modification includes: Figure 5A The front signal line 171F and the front power rail 30F in the Fig. 6A The modification also includes widening the front power rail 30MF. Figure 5B The rear signal line 171B and the rear power rail 30B in the Figure 6B The widened rear power rail in the 30MB. FIG. 5A to FIG. 5B For the corresponding power rails (e.g. 30F and 30B) in FIG. 6A to FIG. 6B The widened power rails in the FPGA (e.g., 30MF and 30MB) have reduced IR drop.

[0059] FIG. 7A to FIG. 7B The layout diagram in the FIG. 5A to FIG. 5BThe modification includes adding conductive segments 738p and 738n in adjacent circuit cells adjacent to the vertical cell boundary 101. The conductive segment 738p extending in the Y direction intersects the p-type active region semiconductor structure 50p at the source region or drain region of the PMOS transistor in the adjacent circuit cell. The conductive segment 738n extending in the Y direction intersects the n-type active region semiconductor structure 50n at the source region or drain region of the NMOS transistor in the adjacent circuit cell. In addition, Fig. 7A middle, Figure 5A The front signal line 171F and the front power rail 30F in the front conductive layer are merged into a wide front power rail 30WF in the front conductive layer, and the wide front power rail 30WF is further widened to occupy the area above the conductive segment 738p. Figure 7B middle, Figure 5B The backside signal line 171B and the backside power rail 30B in the backside conductive layer are merged into a wide backside power rail 30WB in the backside conductive layer, and the wide backside power rail 30WB is further widened to occupy the area under the conductive segment 738n.

[0060] In some embodiments, the edge-to-edge distance between the wide front power rail 30WF and the front signal line 176F (e.g., the distance from edge L30WF to edge L176F) is 2CPP. In addition, the edge-to-edge distance between the wide back power rail 30WB and the back signal line 176B (e.g., the distance from edge L30WB to edge L176B) is also 2CPP. FIG. 5A to FIG. 5B , or compared to the corresponding power rails (e.g., 30F and 30B) in FIG. 6A to FIG. 6B For the corresponding widened power rails (e.g. 30MF and 30MB), FIG. 7A to FIG. 7B Wide power rails in the MCU (such as 30WF and 30WB) have reduced IR drop.

[0061] exist FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B and FIG. 7A to FIG. 7B In each of the layout diagrams of , only one front-side power rail or only one back-side power rail is shown. FIG. 8A to FIG. 8C In each of the layout diagrams of FIG. 1 , an array of power rails in the front side conductive layer or the back side conductive layer is shown.

[0062] exist FIG. 8A to FIG. 8CIn each of the layout diagrams of , three circuit cells 820, 840, and 860 are arranged as columns formed by circuit cells. Circuit cell 820 includes three gate conductors 852[1], 852[2], and 852[3] located between dummy gate conductors 851 and 853. Circuit cell 840 includes seven gate conductors 854[1] to 854[7] located between dummy gate conductors 853 and 855. Circuit cell 860 includes three gate conductors 856[1] to 856[3] located between dummy gate conductors 855 and 857. Each of the vertical cell boundaries of circuit cells 820, 840, and 860 is aligned with the corresponding dummy gate conductor. For example, the two vertical cell boundaries of circuit cell 820 are aligned with dummy gate conductors 851 and 853 respectively, the two vertical cell boundaries of circuit cell 840 are aligned with dummy gate conductors 853 and 855 respectively, and the two vertical cell boundaries of circuit cell 860 are aligned with dummy gate conductors 855 and 857 respectively.

[0063] exist Fig. 8A In the embodiment, a power rail array extending in the Y direction is implemented and configured to provide power supply voltage to circuit cells 820, 840 and 860. The power rail array includes power rails 30[1], 30[2], 30[3], 30[4] and 30[5]. Fig. 8A In the exemplary embodiment shown in , the pitch distance between two adjacent power rails is four CPPs. Other values ​​of the pitch distance between two adjacent power rails are also within the intended scope of the present invention. For example, in some embodiments, the pitch distance between two adjacent power rails is greater than four CPPs.

[0064] exist Fig. 8A In the embodiment, signal lines extending in the Y direction are implemented between power rails. For example, seven signal lines 871 to 877 are implemented between power rails 30[1] and 30[2]. Each of the seven signal lines 871 to 877 occupies an equally spaced conductor track. Fig. 8A Signal lines between other power rails in the are not explicitly shown in the figure. Fig. 8A In the exemplary embodiment shown in , the pitch distance between two signal lines is 0.5 CPP. Other values ​​of the pitch distance between two adjacent signal lines are also within the intended scope of the present invention.

[0065] exist Fig. 8AIn the embodiment of the present invention, each of the signal lines occupies one vertical routing track. Each of the power rails also occupies one vertical routing track. In some embodiments, the pitch distance between two vertical routing tracks is selected based on IR drop and electromigration requirements. Increasing the pitch distance between two vertical routing tracks results in wider power rails and wider vertical signal lines, which reduces IR drop and electromigration in the circuit. Reducing the pitch distance between two vertical routing tracks results in narrower power rails and wider vertical signal lines, which increases signal routing flexibility in the circuit, but increases IR drop in the power rails.

[0066] exist Fig. 8A In the embodiment, when the power rails 30[1] to 30[5] indicated by the layout diagram are implemented in the front side conductive layer, Fig. 8A Each of the power rails 30[1] to 30[5] in the layout diagram represents a front-side power rail, and each of the signal lines represents a front-side signal line occupying one of the plurality of front-side conductor tracks. Power rails 30[1] and 30[2] are two adjacent front-side power rails. When the power rails 30[1] to 30[5] indicated by the layout diagram are implemented in the back-side conductive layer, Fig. 8A Each of the power rails 30[1] to 30[5] in represents a rear power rail, and each of the signal lines represents a rear signal line occupying one of the plurality of rear conductor tracks. The power rails 30[1] and 30[2] are two adjacent rear power rails.

[0067] Figure 8B The layout diagram in the Fig. 8A The modification includes using Figure 8B The widened power rails 30M[1] to 30M[5] in the Fig. 8A The power rails 30[1] to 30[5] in the signal line. Figure 8B Each of the widened power rails is removed to accommodate Figure 8B Each widened power rail in occupies two vertical routing tracks. For example, Fig. 8A The signal line 877 in Figure 8B This is because the widening of the power rail 30M[2] also occupies space for implementation Fig. 8A Vertical routing of signal line 877 in. Figure 8B The IR drop in the widened power rails 30M[1] to 30M[5] is less than Fig. 8A IR drops in power rails 30[1] to 30[5] are shown.

[0068] exist Figure 8BWhen the widened power rails 30M[1] to 30M[5] indicated by the layout diagram are implemented in the front side conductive layer, Figure 8B Each of the widened power rails 30M[1] to 30M[5] in the layout diagram represents a front-side power rail, and each of the signal lines represents a front-side signal line. When the widened power rails 30M[1] to 30M[5] indicated by the layout diagram are implemented in the back-side conductive layer, Figure 8B Each of the widened power rails 30M[1] to 30M[5] in represents a backside power rail, and each of the signal lines represents a backside signal line.

[0069] Figure 8C The layout diagram in the Fig. 8A The modification includes using Figure 8C Replace the Wide Power Rail 30W[1] to Wide Power Rail 30W[5] in Fig. 8A In addition, due to the power rail 30[1] to the power rail 30[5] in Figure 8C Each wide power rail in occupies three vertical routing tracks, so some signal lines adjacent to wide power rails 30W[1] to wide power rails 30W[5] are removed. For example, since wide power rail 30W[2] (which now occupies three vertical routing tracks for implementation Fig. 8A Vertical routing of signal line 876 to signal line 877 in FIG. Fig. 8A The signal line 876 to the signal line 877 in are removed. Figure 8C The IR drop in the wide power rail 30W[1] to wide power rail 30W[5] shown is less than Fig. 8A The IR drop or Figure 8B IR voltage drop in power rail 30M[1] to power rail 30M[5] is shown.

[0070] exist Figure 8C In the embodiment, when the wide power rails 30W[1] to 30W[5] indicated by the layout diagram are implemented in the front side conductive layer, Figure 8C Each of the wide power rails 30W[1] to 30W[5] shown represents a front-side power rail, and each of the signal lines represents a front-side signal line. When the wide power rails 30W[1] to 30W[5] indicated by the layout diagram are implemented in the back-side conductive layer, Figure 8B In Figure 8C Each of the wide power rails 30W[1] to 30W[5] shown represents a backside power rail, and each of the signal lines represents a backside signal line.

[0071] exist FIG. 8A to FIG. 8CIn the layout diagram in FIG. 1 , the power rail is shown as extending in the Y direction and crossing the columns formed by the circuit cells. When the power rail described in the present invention is implemented in an integrated circuit, the power rail usually crosses multiple columns formed by the circuit cells.

[0072] Fig. 9 is a layout diagram of an integrated circuit having a plurality of columns formed of circuit cells according to some embodiments. Fig. 9 The integrated circuit 900 in FIG. 1 includes five columns 910 to 950 formed by circuit cells, and each of the five columns 910 to 950 is formed by a plurality of circuit cells arranged along the X direction. Fig. 9 In the embodiment, a power rail array (where each power rail extends in the Y direction) is implemented and configured to provide power supply voltages for at least the circuit cells in the five columns 910 to 950. The power rail array includes power rails 30[1], 30[2], 30[3], 30[4], 30[5] and 30[6]. Fig. 8A In the embodiment, when the power rails 30[1] to 30[6] indicated by the layout diagram are implemented in the front side conductive layer, Fig. 9 Each of the power rails 30[1] to 30[6] in the layout diagram represents a front-side power rail. When the power rails 30[1] to 30[6] indicated by the layout diagram are implemented in the back-side conductive layer, Fig. 9 Each of the power rails 30[1] to 30[6] in FIG. 5 represents a backside power rail.

[0073] In the present invention, it is described that the vertical power rail (eg Fig. 9 Various exemplary layout designs of circuit cells powered by power rail arrays in FIG. 1 are shown in FIG. 1A . An exemplary layout design of circuit cells implemented using CFET transistors is shown in FIG. Figures 10A to 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14B and FIG. 15A to FIG. 15B middle.

[0074] Figures 10A to 10B is a layout diagram of an inverter circuit according to some embodiments. FIG. 10A to FIG. 10B In the embodiment, adjacent gate conductors are separated by a pitch distance of one CPP. Fig. 10C The inverter circuit according to some embodiments is composed of FIG. 10A to FIG. 10B The cross-sectional view is in the cutting plane indicated by the line AA' in the illustrated layout.

[0075] exist FIG. 10A to FIG. 10CIn the embodiment of the present invention, the inverter circuit is configured to be powered by a front power rail 30F and a back power rail 30B. Each of the front power rail 30F and the back power rail 30B extends in the Y direction. Each of the front power rail 30F and the back power rail 30B extends in the Y direction. The front horizontal wires 1042F[1] to 1042F[2] and 1044F extending in the X direction are made in a first front conductive layer (e.g., metal layer M0), and the back horizontal wires 1042B extending in the X direction are made in a first back conductive layer (e.g., metal layer BM0). The front power rail 30F is made in a second front conductive layer (e.g., metal layer M1), and the back power rail 30B is made in a second back conductive layer (e.g., metal layer BM1). The front signal lines 1074F and 1076F extending in the Y direction are also fabricated in the second front conductive layer (eg, metal layer M1). The second front conductive layer is located above the first front conductive layer, and the second back conductive layer is located below the first back conductive layer.

[0076] The inverter circuit includes a PMOS transistor T1p in a p-type active region semiconductor structure 50p and an NMOS transistor T1n in an n-type active region semiconductor structure 50n. The source terminal S(T1p) of the PMOS transistor T1p is connected to the rear horizontal conductive line 1042B through a rear via connector VDb, and the rear horizontal conductive line 1042B is also connected to the rear power rail 30B through a rear via connector VIA0b. The source terminal S(T1n) of the NMOS transistor T1n is connected to the front horizontal conductive line 1042F[1] through a front via connector VD, and the front horizontal conductive line 1042F[1] is also connected to the front power rail 30F through a front via connector VIA0. The drain terminal D(T1p) of the PMOS transistor T1p and the drain terminal D(T1n) of the NMOS transistor T1n are connected together through a conductive segment intermediate connector VMD.

[0077] exist FIG. 10A to FIG. 10C, the inverter circuit is located in a circuit cell bounded by a vertical cell boundary aligned with dummy gate conductors 151 and 159. Gate conductor 150 is connected to both the gate terminal of PMOS transistor T1p and the gate terminal of NMOS transistor T1n. Gate conductor 150 is connected to front horizontal conductor 1044F through front via connector VG, and front horizontal conductor 1044F is also connected to front signal line 1074F through front via connector VIA0. Drain terminal D(T1n) of NMOS transistor T1n is connected to front horizontal conductor 1042F[2] through front via connector VD, and front horizontal conductor 1042F[2] is also connected to front signal line 1076F through front via connector VIA0. Front signal line 1074F is configured to carry an input signal of the inverter circuit, and front signal line 1076F is configured to carry an output signal of the inverter circuit.

[0078] exist FIG. 10A to FIG. 10C In the embodiment, the active region semiconductor structure stack is formed by a p-type active region semiconductor structure 50p and an n-type active region semiconductor structure 50n. FIG. 10A to FIG. 10C The active region semiconductor structure stack in the inverter circuit shown is different from FIG. 2A to FIG. 2B and FIG. 3A to FIG. 3C The active region semiconductor structure stack in the inverter circuit shown. FIG. 10A to FIG. 10C In FIG. 5 , the n-type active region semiconductor structure 50n is located above the p-type active region semiconductor structure 50p. FIG. 2A to FIG. 2B and FIG. 3A to FIG. 3C In comparison, the n-type active region semiconductor structure 50n is located below the p-type active region semiconductor structure 50p. FIG. 10A to FIG. 10C In FIG. 5 , compared with the p-type active region semiconductor structure 50 p, the first front side conductive layer is closer to the n-type active region semiconductor structure 50 n. FIG. 2A to FIG. 2B and FIG. 3A to FIG. 3C In comparison, the first front side conductive layer is closer to the p-type active region semiconductor structure 50p than to the n-type active region semiconductor structure 50n.

[0079] In by FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14B and FIG. 15A to FIG. 15B In the circuit cell indicated by the layout diagram in , each active region semiconductor structure stack includes an n-type active region semiconductor structure located above a p-type active region semiconductor structure. In an alternative embodiment, each active region semiconductor structure stack includes an n-type active region semiconductor structure located below a p-type active region semiconductor structure. Various variations of circuit cells based on alternative embodiments of active region semiconductor structure stacks are within the intended scope of the present invention.

[0080] FIG. 11A to FIG. 11B is a layout diagram of an NAND circuit according to some embodiments. The NAND circuit is configured to be powered by a front power rail 30F and a back power rail 30B. Each of the front power rail 30F and the back power rail 30B extends in the Y direction. The front horizontal wires 1142F[1] to the front horizontal wires 1142F[2] and the front horizontal wires 1144F[1] to the front horizontal wires 1144F[2] extending in the X direction are made in a first front conductive layer (e.g., metal layer M0), and the back horizontal wires 1142B and 1144B extending in the X direction are made in a first back conductive layer (e.g., metal layer BM0). The front power rail 30F is made in a second front conductive layer (e.g., metal layer M1), and the back power rail 30B is made in a second back conductive layer (e.g., metal layer BM1). Front signal lines 1174F, 1176F and 1178F extending in the Y direction are also fabricated in the second front conductive layer (eg, metal layer M1). The second front conductive layer is located above the first front conductive layer, and the second back conductive layer is located below the first back conductive layer.

[0081] exist FIG. 11A to FIG. 11B , the NAND circuit is located in a circuit cell bounded by a vertical cell boundary aligned with dummy gate conductors 151 and 159. Gate conductor gA1 is connected to both the gate terminal of PMOS transistor TA1p and the gate terminal of NMOS transistor TA1n. Gate conductor gA2 is connected to both the gate terminal of PMOS transistor TA2p and the gate terminal of NMOS transistor TA2n. PMOS transistors TA1p and TA2p are located in a p-type active region semiconductor structure 50p, and NMOS transistors TA1n and TA2n are located in an n-type active region semiconductor structure 50n.

[0082] exist Fig. 11B , the joint source terminal S(A1p, A2p) of the PMOS transistors TA1p and TA2p is connected to the rear horizontal conductor 1144B, and the rear horizontal conductor 1144B is connected to the rear power rail 30B through the rear through-hole connection VIA0b located between the second rear conductive layer and the first rear conductive layer. The drain terminal D(A1p) of the PMOS transistor TA1p and the drain terminal D(A2p) of the PMOS transistor TA2p are connected to the rear horizontal conductor 1142B. The drain terminal D(A1p) of the PMOS transistor TA1p is also connected to the NMOS transistor TA1n (at Fig.11A The drain terminal D(A1n) of the device is shown in FIG.

[0083] exist Fig.11A, the source terminal S(A1n) of the NMOS transistor TA1n and the drain terminal D(A2n) of the NMOS transistor TA2n are connected together in the n-type active region semiconductor structure 50n at the region between the gate conductors gA1 and gA2. The source terminal S(A2n) of the NMOS transistor TA2n is connected to the front side power rail 30F through the front side via connector VD.

[0084] The front power rail 30F is connected to the front horizontal conductor 1144F[1] through the front via connector VIA0, and the back power rail 30B is connected to the back horizontal conductor 1144B through the back via connector VIA0b. The gate conductor gA1 is connected to the front horizontal conductor 1144F[2], which is also connected to the front signal line 1176F. The gate conductor gA2 is connected to the front horizontal conductor 1142F[1], which is also connected to the front signal line 1174F. The drain terminal D(A1n) of the NMOS transistor TA1n is connected to the front horizontal conductor 1142F[2], which is also connected to the front signal line 1178F. Front side signal line 1176F is configured to carry a first input signal "A1" of the NAND circuit, front side signal line 1174F is configured to carry a second input signal "A2" of the NAND circuit, and front side signal line 1178F is configured to carry an output signal "Z" of the NAND circuit.

[0085] FIG. 12A to FIG. 12B1 is a layout diagram of an AND-OR-Inverter (AOI) circuit according to some embodiments. The AOI circuit is configured to be powered by front-side power rails 30F[1] to 30F[2] and back-side power rails 30B[1] to 30B[2]. Each of the front-side power rails 30F[1] to 30F[2] and back-side power rails 30B[1] to 30B[2] extends in the Y direction. The front-side horizontal conductive wires 1242F[1] to 1242F[4] and 1244F[1] to 1244F[3] extending in the X direction are fabricated in a first front-side conductive layer (e.g., metal layer M0), and the back-side horizontal conductive wires 1242B and 1244B[1] to 1244B[2] extending in the X direction are fabricated in a first back-side conductive layer (e.g., metal layer BM0). The front power rails 30F[1] to 30F[2] are fabricated in a second front conductive layer (e.g., metal layer M1), and the back power rails 30B[1] to 30B[2] are fabricated in a second back conductive layer (e.g., metal layer BM1). The front signal lines 1272F, 1274F, 1275F, 1276F, and 1278F extending in the Y direction are also fabricated in the second front conductive layer (e.g., metal layer M1). The second front conductive layer is located above the first front conductive layer, and the second back conductive layer is located below the first back conductive layer.

[0086] exist FIG. 12A to FIG. 12B , the AOI circuit is located in a circuit cell bounded by a vertical cell boundary aligned with dummy gate conductors 151 and 159. The AOI circuit includes gate conductors gA1, gA2, gB1, and gB2 extending in the Y direction and another dummy gate conductor 1255 located between gate conductors gB1 and gA1. Gate conductor gA1 is connected to both the gate terminal of PMOS transistor TA1p and the gate terminal of NMOS transistor TA1n. Gate conductor gA2 is connected to both the gate terminal of PMOS transistor TA2p and the gate terminal of NMOS transistor TA2n. Gate conductor gB1 is connected to both the gate terminal of PMOS transistor TB1p and the gate terminal of NMOS transistor TB1n. Gate conductor gB2 is connected to both the gate terminal of PMOS transistor TB2p and the gate terminal of NMOS transistor TB2n. The PMOS transistors TA1p, TA2p, TB1p and TB2p are located in the p-type active region semiconductor structure 50p, and the NMOS transistors TA1n, TA2n, TB1n and TB2n are located in the n-type active region semiconductor structure 50n.

[0087] exist Fig. 12B, the joint source terminal S(B1p, B2p) of the PMOS transistors TB1p and TB2p is connected to the back side horizontal conductor 1244B[1], which is also connected to the back side power rail 30B[1] (through the back side through-hole connection VIA0b located between the first back side conductive layer and the second back side conductive layer). The drain terminal D(B1p) of the PMOS transistor TB1p and the drain terminal D(B2p) of the PMOS transistor TB2p are connected to the back side horizontal conductor 1242B. The back side horizontal conductor 1242B is also connected to the joint source terminal S(A1p, A2p) of the PMOS transistors TA1p and TA2p. The drain terminal D(A1p) of the PMOS transistor TA1p and the drain terminal D(A2p) of the PMOS transistor TA2p are connected to the back side horizontal conductor 1244B[2]. The drain terminal D(A1p) of the PMOS transistor TA1p is also connected to the NMOS transistor TA1n (at Fig. 12A The drain terminal D(A1n) of the device is shown in FIG.

[0088] exist Fig. 12A , the drain terminal D(A1n) of the NMOS transistor TA1n is connected to the front horizontal conductor 1244F[2], and the front horizontal conductor 1244F[2] is also connected to the drain terminal D(B1n) of the NMOS transistor TB1n. The source terminal S(A1n) of the NMOS transistor TA1n and the drain terminal D(A2n) of the NMOS transistor TA2n are linked together in the n-type active region semiconductor structure 50n. The source terminal S(A2n) of the NMOS transistor TA2n is connected to the front horizontal conductor 1244F[3] through the front through-hole connector VD, and the front horizontal conductor 1244F[3] is connected to the front power rail 30F[2] through the front through-hole connector VIA0 located between the first front conductive layer and the second front conductive layer.

[0089] The source terminal S(B1n) of the NMOS transistor TB1n and the drain terminal D(B2n) of the NMOS transistor TB2n are connected together in the n-type active region semiconductor structure 50n. The source terminal S(B2n) of the NMOS transistor TB2n is connected to the front horizontal conductive line 1242F[1] through the front via connector VD, and the front horizontal conductive line 1242F[1] is connected to the front power rail 30F[1] through the front via connector VIA0 located between the first front conductive layer and the second front conductive layer.

[0090] The gate conductor gA1 is connected to the front signal line 1242F[3], which is also connected to the front signal line 1276F. The gate conductor gA2 is connected to the front signal line 1242F[4], which is also connected to the front signal line 1278F. The gate conductor gB1 is connected to the front signal line 1242F[2], which is also connected to the front signal line 1274F. The gate conductor gB2 is connected to the front signal line 1244F[1], which is also connected to the front signal line 1272F. The drain terminals of the NMOS transistors TA1n and TB1n are connected to the front signal line 1244F[2], which is also connected to the front signal line 1275F. Front side signal lines 1276F, 1278F, 1274F and 1272F are configured to carry input signals "A1", "A2", "B1" and "B2" of the AOI circuit, respectively. Front side signal line 1275F is configured to carry output signal "Z" of the AOI circuit.

[0091] FIG. 13A to FIG. 13B is a layout diagram of an inverter circuit according to some embodiments. FIG. 13C to FIG. 13D According to some embodiments FIG. 13A to FIG. 13B The inverter circuit is shown in cross-sectional views in cutting planes AA' and BB', respectively. The inverter circuit is configured to be powered by a front power rail 30F and a rear power rail 30B. Each of the front power rail 30F and the rear power rail 30B extends in the Y direction. The front power rail 30F is made in a first front conductive layer (e.g., metal layer M0), and the rear power rail 30B is made in a first rear conductive layer (e.g., metal layer BM0).

[0092] The front signal lines 1374F and 1376F extending in the Y direction are also made in the first front conductive layer (e.g., metal layer M0). The rear signal line 1372B extending in the Y direction is also made in the first rear conductive layer (e.g., metal layer BM0). The front horizontal wires 1342F and 1344F extending in the X direction are made in the second front conductive layer (e.g., metal layer M1), and the rear horizontal wires 1342B extending in the X direction are made in the second rear conductive layer (e.g., metal layer BM1). The second front conductive layer is located above the first front conductive layer, and the second rear conductive layer is located below the first rear conductive layer.

[0093] exist FIG. 13A to FIG. 13B, the inverter circuit is located in a circuit cell bounded by a vertical cell boundary aligned with dummy gate conductors 151 and 159. Gate conductor 150 is connected to both the gate terminal of PMOS transistor T1p and the gate terminal of NMOS transistor T1n. PMOS transistor T1p is located in p-type active region semiconductor structure 50p, and NMOS transistor T1n is located in n-type active region semiconductor structure 50n. P-type active region semiconductor structure 50p is located below n-type active region semiconductor structure 50n, thereby forming a stack of active region semiconductor structures.

[0094] like Fig. 13B and FIG. 13C to FIG. 13D As shown in , the source terminal S(T1p) of the PMOS transistor T1p is connected to the backside signal line 1372B, which is also connected to the backside horizontal conductor 1342B through the backside through-hole connection VIA0b, and the backside horizontal conductor 1342B is connected to the backside power rail 30B through another backside through-hole connection VIA0b. Therefore, the source terminal of the PMOS transistor T1p is configured to receive the high supply voltage VDD from the backside power rail 30B. The drain terminal D(T1p) of the PMOS transistor T1p is connected to the NMOS transistor TA1n (which is connected to the backside power rail 30B) through the conductive segment intermediate connection VMD. Fig.13A The drain terminal D(T1n) of Fig.13A , the source terminal S(T1n) of the NMOS transistor T1n is connected to the front side power rail 30F through the front side via connector VD. Therefore, the source terminal S(T1n) of the NMOS transistor T1n is configured to receive the low supply voltage VSS from the front side power rail 30F.

[0095] like Fig.13A and FIG. 13C to FIG. 13D As shown in , the gate conductor 150 is connected to the front signal line 1374F, which is also connected to the front horizontal wire 1342F. The drain terminal D(A1n) of the NMOS transistor T1n is connected to the front signal line 1376F, which is also connected to the front horizontal wire 1344F. The front horizontal wire 1342F is configured to carry the input signal "I" of the inverter circuit accordingly. The front horizontal wire 1344F is configured to carry the output signal "Z" of the inverter circuit.

[0096] FIG. 14A to FIG. 14Bis a layout diagram of an inverting and circuit according to some embodiments. The inverting and circuit is configured to be powered by a front power rail 30F and a back power rail 30B. Each of the front power rail 30F and the back power rail 30B extends in the Y direction. The front power rail 30F is made in a first front conductive layer (e.g., metal layer M0), and the back power rail 30B is made in a first back conductive layer (e.g., metal layer BM0). The front signal lines 1474F[1] to 1474F[2] and 1476F[1] to 1476F[2] extending in the Y direction are also made in the first front conductive layer (e.g., metal layer M0). The back signal lines 1472B[1] to 1472B[2] extending in the Y direction are also made in the first back conductive layer (e.g., metal layer BM0). The front horizontal conductive lines 1442F, 1444F, 1446F, and 1448F extending in the X direction are fabricated in a second front conductive layer (e.g., metal layer M1), and the rear horizontal conductive lines 1442B and 1446B extending in the X direction are fabricated in a second rear conductive layer (e.g., metal layer BM1). The second front conductive layer is located above the first front conductive layer, and the second rear conductive layer is located below the first rear conductive layer.

[0097] exist FIG. 14A to FIG. 14B , the NAND circuit is located in a circuit cell bounded by a vertical cell boundary aligned with dummy gate conductors 151[1] to 151[2] and 159[1] to 159[2]. Gate conductor gA1 is connected to a gate terminal of a PMOS transistor TA1p and a gate terminal of an NMOS transistor TA1n. Gate conductor gA2 is connected to both a gate terminal of a PMOS transistor TA2p and a gate terminal of an NMOS transistor TA2n. The PMOS transistor TA1p is located in a first p-type active region semiconductor structure 50p[1], and the PMOS transistor TA2p is located in a second p-type active region semiconductor structure 50p[2]. The NMOS transistor TA1n is located in a first n-type active region semiconductor structure 50n[1], and the NMOS transistor TA2n is located in a second n-type active region semiconductor structure 50n[2]. The first p-type active region semiconductor structure 50p[1] is located below the first n-type active region semiconductor structure 50n[1], thereby forming a first active region semiconductor structure stack. The second p-type active region semiconductor structure 50p[2] is located below the second n-type active region semiconductor structure 50n[2], thereby forming a second active region semiconductor structure stack.

[0098] exist Fig. 14B, the source terminal S(A1p) of the PMOS transistor TA1p is connected to the backside signal line 1472B[1], which is also connected to the backside horizontal wire 1446B. The source terminal S(A2p) of the PMOS transistor TA2p is connected to the backside signal line 1472B[2], which is also connected to the backside horizontal wire 1442B. In addition, each of the backside horizontal wire 1446B and the backside horizontal wire 1442B is connected to the backside power rail 30B through a corresponding backside through-hole connector VIA0b. Therefore, the source terminals of the PMOS transistors TA2p and TB2p are configured to receive the high supply voltage VDD from the backside power rail 30B. The drain terminals of the PMOS transistors TA2p and TB2p are connected together to a joint drain terminal D(A1p, A2p), which is also connected to a drain terminal D(A1n) of the NMOS transistor TA1n through a conductive segment intermediate connector VMD.

[0099] exist Fig.14A , the source terminal S(A1n) of the NMOS transistor TA1n and the drain terminal D(A2n) of the NMOS transistor TA2n are connected together by the conductive section 1432n. The source terminal S(A2n) of the NMOS transistor TA2n is connected to the front side signal line 1476F[2], and the front side signal line 1476F[2] is also connected to the front side horizontal conductor 1444F through the front side via connector VIA0. Then, the front side horizontal conductor 1444F is connected to the front side power rail 30F through another front side via connector VIA0. Therefore, the source terminal S(A2n) of the NMOS transistor TA2n is configured to receive the low supply voltage VSS from the front side power rail 30F.

[0100] exist Fig.14A , the gate conductor gA1 is connected to the front signal line 1474F[1], which is also connected to the front horizontal wire 1446F. The gate conductor gA2 is connected to the front signal line 1474F[2], which is also connected to the front horizontal wire 1442F. The drain terminal D(A1n) of the NMOS transistor TA1n is connected to the front signal line 1476F[1], which is also connected to the front horizontal wire 1448F. The front horizontal wires 1446F and 1442F are configured to carry the input signals "A1" and "A2" of the NAND circuit respectively. The front horizontal wire 1448F is configured to carry the output signal "Z" of the NAND circuit.

[0101] FIG. 15A to FIG. 15Bis a layout diagram of an AOI circuit according to some embodiments. The AOI circuit is configured to be powered by front power rails 30F[1] to 30F[2] and back power rails 30B. Each of the front power rails 30F[1] to 30F[2] and back power rails 30B extends in the Y direction. The front power rails 30F[1] to 30F[2] are fabricated in a first front conductive layer (e.g., metal layer M0), and the back power rails 30B are fabricated in a first back conductive layer (e.g., metal layer BM0). The front signal lines 1572F[1] to 1572F[2], the front signal lines 1574F[1] to 1574F[2], the front signal lines 1576F[1] to 1576F[2], and the front signal lines 1578F[1] to 1578F[2] extending in the Y direction are also fabricated in the first front conductive layer (e.g., metal layer M0). The rear signal lines 1572B and 1578B extending in the Y direction are also fabricated in the first rear conductive layer (e.g., metal layer BM0). The front horizontal wires 1542F[1] to 1542F[2], the front horizontal wires 1544F, the front horizontal wires 1546F[1] to 1546F[2], and the front horizontal wires 1548F extending in the X direction are fabricated in a second front conductive layer (e.g., metal layer M1), and the rear horizontal wires 1542B extending in the X direction are fabricated in a second rear conductive layer (e.g., metal layer BM1). The second front conductive layer is located above the first front conductive layer, and the second rear conductive layer is located below the first rear conductive layer.

[0102] exist FIG. 15A to FIG. 15B , the AOI circuit is located in a circuit cell bounded by a vertical cell boundary aligned with dummy gate conductors 151[1] to 151[2] and 159[1] to 159[2]. The AOI circuit includes a gate conductor gA1, a gate conductor gA2, a gate conductor gB1, and a gate conductor gB2 extending in the Y direction, and a dummy gate conductor 1555 located between some of the gate conductors. The gate conductor gA1 is connected to both the gate terminal of the PMOS transistor TA1p and the gate terminal of the NMOS transistor TA1n. The gate conductor gA2 is connected to both the gate terminal of the PMOS transistor TA2p and the gate terminal of the NMOS transistor TA2n. The gate conductor gB1 is connected to both the gate terminal of the PMOS transistor TB1p and the gate terminal of the NMOS transistor TB1n. The gate conductor gB2 is connected to both the gate terminal of the PMOS transistor TB2p and the gate terminal of the NMOS transistor TB2n.

[0103] The PMOS transistors TA1p and TB1p are located in the first p-type active region semiconductor structure 50p[1], and the PMOS transistors TA2p and TB2p are located in the second p-type active region semiconductor structure 50p[2]. The NMOS transistors TA1n and TB1n are located in the first n-type active region semiconductor structure 50n[1], and the NMOS transistors TA2n and TB2n are located in the second n-type active region semiconductor structure 50n[2]. The first p-type active region semiconductor structure 50p[1] is located below the first n-type active region semiconductor structure 50n[1], thereby forming a first active region semiconductor structure stack. The second p-type active region semiconductor structure 50p[2] is located below the second n-type active region semiconductor structure 50n[2], thereby forming a second active region semiconductor structure stack.

[0104] exist Fig. 15B , the joint source terminal S(B1p, B2p) of the PMOS transistors TB1p and TB2p is connected to the backside power rail 30B through the backside through-hole connection VDb. The joint drain terminal D(B1p, B2p) of the PMOS transistors TB1p and TB2p is connected to the backside signal line 1578B, which is also connected to the backside horizontal wire 1542B. The backside horizontal wire 1542B is connected to the backside signal line 1572B, which is also connected to the joint source terminal S(A1p, A2p) of the PMOS transistors TA1p and TA2p. In addition, the joint drain terminal D(A1p, A2p) of the PMOS transistors TA1p and TA2p is connected to the drain terminal D(A1n) of the NMOS transistor TA1n through the conductive segment intermediate connection VMD.

[0105] exist Fig.15A, the drain terminal D(A1n) of the NMOS transistor TA1n is connected to the front side signal line 1574F[1], which is also connected to the front side horizontal wire 1548F. The front side horizontal wire 1548F is connected to the front side signal line 1576F[1], which is also connected to the drain terminal D(B1n) of the NMOS transistor TB1n. The source terminal S(A1n) of the NMOS transistor TA1n and the drain terminal D(A2n) of the NMOS transistor TA2n are connected together by the conductive segment 1532n. The source terminal S(B1n) of the NMOS transistor TB1n and the drain terminal D(B2n) of the NMOS transistor TB2n are connected together by the conductive segment 1538n. The source terminal S(A2n) of the NMOS transistor TA2n is connected to the front side signal line 1574F[2], which is also connected to the front side horizontal conductor 1544F. The source terminal S(B2n) of the NMOS transistor TB2n is connected to the front side signal line 1576F[2], which is also connected to the front side horizontal conductor 1544F. In addition, the front side horizontal conductor 1544F is connected to the front side power rail 30F[2]. Therefore, the source terminals of the NMOS transistors TA2n and TB2n are configured to receive the low supply voltage VSS from the front side power rail 30F[2].

[0106] The gate conductor gA1 is connected to the front signal line 1572F[1], which is also connected to the front signal line 1546F[1]. The gate conductor gA2 is connected to the front signal line 1572F[2], which is also connected to the front horizontal wire 1542F[1]. The gate conductor gB1 is connected to the front signal line 1578F[1], which is also connected to the front horizontal wire 1546F[2]. The gate conductor gB2 is connected to the front signal line 1578F[2], which is also connected to the front horizontal wire 1542F[2]. Front horizontal conductors 1546F[1], 1542F[1], 1546F[2], and 1542F[2] are configured to carry input signals "A1", "A2", "B1", and "B2" of the AOI circuit, respectively. Front horizontal conductor 1548F is configured to carry output signal "Z" of the AOI circuit.

[0107] FIG. 16A to FIG. 16CSchematic diagrams of various designs of power rails in three metal layers in the front side or back side of an integrated circuit according to some embodiments. A power grid for powering each integrated circuit includes power rails in a first metal layer, a second metal layer, and a third metal layer. The power rail in the first metal layer (e.g., metal layer M0) extends in the Y direction. The power rail in the second metal layer (e.g., metal layer M1) extends in the X direction. The power rail in the third metal layer (e.g., metal layer M2) extends in the Y direction. The second metal layer is located above the first metal layer. The third metal layer is located above the second metal layer.

[0108] exist FIG. 16A to FIG. 16C In the example provided, three options for implementing the power rails in the first metal layer (e.g., metal layer M0) are shown. Fig.16A In the first option shown in , the power rail 30 extending in the Y direction occupies only one vertical routing track. Fig. 16B In the second option shown in , the power rail 30M extending in the Y direction occupies two vertical routing tracks. Fig. 16C In the third option shown in FIG. , the power rail 30W extending in the Y direction occupies three vertical routing tracks.

[0109] For each option of implementing the power rail in the first metal layer (e.g., metal layer M0), two options of implementing the power rail in the second metal layer (e.g., metal layer M1) are illustrated. In the first option, the power rail 32W in the second metal layer (e.g., metal layer M1) extending along the X direction is implemented at the horizontal cell boundary 102. In the second option, the power rail 32 in the second metal layer (e.g., metal layer M1) extending along the X direction is implemented between the two horizontal cell boundaries 102 and 104. The width of the power rail 32W at the horizontal cell boundary is wider than the width of the power rail 32 between the two horizontal cell boundaries, which makes the power rail 32W have a smaller IR drop than the power rail 32.

[0110] For each option of implementing the power rail in the first metal layer (e.g., metal layer M0) and each option of implementing the power rail in the second metal layer (e.g., metal layer M1), two options of implementing the power rail in the third metal layer (e.g., metal layer M2) extending in the Y direction are illustrated. In the first option, the power rail 34 in the third metal layer (e.g., metal layer M2) extending in the Y direction is implemented between the two vertical cell boundaries 101 and 109. In the second option, the power rail 34W in the third metal layer (e.g., metal layer M2) extending in the Y direction is implemented at the vertical cell boundary 101. The width of the power rail 34W at the vertical cell boundary is wider than the width of the power rail 34 between the two vertical cell boundaries, which makes the power rail 34W have a smaller IR drop than the power rail 34.

[0111] exist Fig.16A , the power rails in the first metal layer (e.g., metal layer M0) are implemented for the first option, and for each of the options for implementing the power rails in the second metal layer (e.g., metal layer M1), two options for implementing the power rails in the third metal layer (e.g., metal layer M2) are shown. Fig. 16B , the power rails in the first metal layer (e.g., metal layer M0) are implemented for the second option, and for each of the two options for implementing the power rails in the second metal layer (e.g., metal layer M1), two options for implementing the power rails in the third metal layer (e.g., metal layer M2) are shown. Fig. 16C , a power rail in a first metal layer (e.g., metal layer M0) is implemented for the third option, and for each of the options for implementing a power rail in a second metal layer (e.g., metal layer M1), two options for implementing a power rail in a third metal layer (e.g., metal layer M2) are illustrated.

[0112] Fig.17 is a flow chart of a method 1700 of manufacturing an integrated circuit (IC) having a CFET device according to some embodiments. It should be understood that Fig.17 Additional operations may be performed before, during, and / or after the method 1700 depicted in the drawings, and some other processes may be only briefly described herein.

[0113] In operation 1710 of method 1700, a first type active region semiconductor structure is formed on a substrate. Then, in operation 1712 of method 1700, a first gate conductor is formed, and the first gate conductor intersects the first type active region semiconductor structure. As a non-limiting example, in Figure 1 and FIG. 3A to FIG. 3CIn the illustrated embodiment, in operation 1710, an n-type active region semiconductor structure 50n is formed on a substrate. In operation 1712, a lower portion of a gate conductor 150 is formed, and the lower portion of the gate conductor 150 intersects the n-type active region semiconductor structure 50n. As another non-limiting example, in the example FIG. 13A to FIG. 13D In the embodiment shown in FIG. 1 , in operation 1712 , a lower portion of the gate conductor 150 is formed, and the lower portion of the gate conductor 150 intersects the n-type active region semiconductor structure 50 n .

[0114] In addition to operation 1712, another operation after operation 1710 is operation 1714. In operation 1714, a first conductive segment is formed, and the first conductive segment intersects the first type active region semiconductor structure. As a non-limiting example, in the example Figure 1 and FIG. 3A to FIG. 3C In the embodiment shown in , the conductive segment 132n is fabricated, and the conductive segment 132n (as a source conductive segment) intersects with the n-type active region semiconductor structure 50n and forms the source terminal of the NMOS transistor T1n. In the process flow of method 1700, both operations 1712 and 1714 are performed after operation 1710. In some embodiments, operation 1712 is performed before operation 1714. In some alternative embodiments, operation 1712 is performed after operation 1714. After operations 1710, 1712, and 1714, the process flow continues to 1720.

[0115] In operation 1720 of method 1700, a dielectric material layer is deposited, and the dielectric material layer covers at least the first type active region semiconductor structure, and in operation 1730 of method 1700, a second type active region semiconductor structure is formed on top of the dielectric material layer. As a non-limiting example, in Figure 1 and FIG. 3A to FIG. 3C In the embodiment shown in , a p-type active region semiconductor structure 50p is formed on top of the dielectric material layer located above the n-type active region semiconductor structure 50n. Then, in operation 1732 of method 1700, a second gate conductor is formed, and the second gate conductor intersects the second type active region semiconductor structure. As a non-limiting example, in Figure 1 and FIG. 3A to FIG. 3C In the embodiment shown in FIG. 5 , an upper portion of the gate conductor 150 is formed and intersects the p-type active region semiconductor structure 50 p .

[0116] In some embodiments, in operations 1712 and 1732, the lower portion and the upper portion of the gate conductor 150 are correspondingly formed. In some embodiments, the integrated gate conductor 150 is formed by the lower portion and the upper portion of the gate conductor. Specifically, before forming the upper portion of the gate conductor 150, a gate intermediate connector is formed that passes through the dielectric material layer located above the n-type active region semiconductor structure 50n, and the gate intermediate connector directly connects the lower portion of the gate conductor 150 with the upper portion of the gate conductor 150 to form the integrated gate conductor 150. In some alternative embodiments, the second gate conductor formed in operation 1732 and the first gate conductor formed in operation 1712 are not directly connected to the gate intermediate connector. For example, the gate conductor 150n produced in operation 1712 and the gate conductor 150p produced in operation 1732 are respectively formed as the gate terminal of the NMOS transistor and the gate terminal of the PMOS transistor. When the NMOS transistor and the PMOS transistor are circuit cells in which the gate terminal of the NMOS transistor and the gate terminal of the PMOS transistor are not directly connected, the gate conductor 150n and the gate conductor 150p are therefore not directly connected.

[0117] In operation 1734, a second conductive segment is formed, and the second conductive segment intersects the second type active region semiconductor structure. As a non-limiting example, in Figure 1 and FIG. 3A to FIG. 3C In the embodiment shown in , a conductive segment 132p is fabricated, and the conductive segment 132p (as a source conductive segment) intersects with the p-type active region semiconductor structure 50p and forms a source terminal of the PMOS transistor T1p. In the process flow of method 1700, both operations 1732 and 1734 are performed after operation 1730. In some embodiments, operation 1732 is performed before operation 1734. In some alternative embodiments, operation 1732 is performed after operation 1734. After operations 1730, 1732, and 1734, the process flow continues to 1740.

[0118] In operation 1740 of method 1700, a first insulating material is deposited, and the first insulating material covers the second gate conductor and the second conductive segment. After operation 1740, in operation 1750 of method 1700, a front side metal layer is deposited on the first insulating material. Then, in operation 1755 of method 1700, the front side metal layer is patterned to form a front side power rail and a front side signal line. Each of the front side power rail and the front side signal line extends in a second direction perpendicular to the first direction. The front side power rail is conductively connected to the second conductive segment through a front side through-hole connector. As a non-limiting example, in Figure 1 and FIG. 3A to FIG. 3CIn the embodiment shown in , the front side power rail 30F and the front side signal lines 174F and 176F are made in the front side metal layer overlying the insulating material covering the gate conductor 150 and the conductive segment 132p. The front side power rail 30F and the conductive segment 132p are directly connected to the front side via connector VD.

[0119] After operations 1740, 1750, and 1755, the wafer containing the substrate is flipped in operation 1760. Then, the process flow continues to 1770. In operation 1770 of method 1700, a backside metal layer is formed on the back side of the substrate. After operation 1770, in operation 1775 of method 1700, the backside metal layer is patterned to form a backside power rail and a backside signal line. The backside power rail is conductively connected to the first conductive segment through a backside through-hole connector. As a non-limiting example, in the example Figure 1 and FIG. 3A to FIG. 3C In the embodiment shown in , the backside power rail 30B and the backside signal lines 174B and 176B are made in the backside metal layer at the backside of the substrate. The backside power rail 30B and the conductive segment 132n are directly connected to the backside via connector VDb.

[0120] Fig.18 is a block diagram of an electronic design automation (EDA) system 1800 according to some embodiments.

[0121] In some embodiments, the EDA system 1800 includes an automatic placement and routing (APR) system. The method of designing a layout diagram representing a wire routing arrangement according to one or more embodiments described herein may be implemented using the EDA system 1800, for example, according to some embodiments.

[0122] In some embodiments, EDA system 1800 is a general purpose computing device including a hardware processor 1802 and a non-transitory computer-readable storage medium 1804. Storage medium 1804 is encoded with (i.e., stores) computer program code 1806 (i.e., a set of executable instructions), among other forms. Execution of instructions 1806 by hardware processor 1802 represents (at least in part) an EDA tool for implementing a portion or all of the methods described herein (hereinafter referred to as described processes and / or methods) according to one or more embodiments.

[0123] The processor 1802 is electrically coupled to the computer-readable storage medium 1804 via a bus 1808. The processor 1802 is also electrically coupled to an input / output (I / O) interface 1810 via the bus 1808. A network interface 1812 is also electrically connected to the processor 1802 via the bus 1808. The network interface 1812 is connected to a network 1814 so that the processor 1802 and the computer-readable storage medium 1804 can be connected to external components via the network 1814. The processor 1802 is configured to execute computer program code 1806 encoded in the computer-readable storage medium 1804 so that the system 1800 can be used to implement part or all of the described processes and / or methods. In one or more embodiments, the processor 1802 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0124] In one or more embodiments, the computer-readable storage medium 1804 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1804 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1804 includes a compact disk-readonly memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0125] In one or more embodiments, the storage medium 1804 stores computer program code 1806 configured to enable the system 1800 to be used to implement part or all of the described processes and / or methods (wherein such execution (at least in part) represents an EDA tool). In one or more embodiments, the storage medium 1804 also stores information that facilitates the implementation of part or all of the described processes and / or methods. In one or more embodiments, the storage medium 1804 stores a library 1807 of standard cells, including such standard cells as disclosed herein. In one or more embodiments, the storage medium 1804 stores one or more layout drawings 1809 corresponding to one or more layouts disclosed herein.

[0126] The EDA system 1800 includes an I / O interface 1810. The I / O interface 1810 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1810 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 1802.

[0127] The EDA system 1800 also includes a network interface 1812 coupled to the processor 1802. The network interface 1812 enables the system 1800 to communicate with a network 1814 connected to one or more other computer systems. The network interface 1812 includes: a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), worldwide interoperability of microwave access (WIMAX), general packet radio service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers (IEEE)-1364. In one or more embodiments, part or all of the described process and / or method is implemented in two or more systems 1800.

[0128] The system 1800 is configured to receive information via an I / O interface 1810. The information received via the I / O interface 1810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 1802. The information is transferred to the processor 1802 via a bus 1808. The EDA system 1800 is configured to receive information related to a user interface (UI) via the I / O interface 1810. The information is stored in a computer-readable storage medium 1804 as a UI 1842.

[0129] In some embodiments, part or all of the described processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the described processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the described processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the described processes and / or methods are implemented as a software application used by EDA system 1800. In some embodiments, the system 1800 is implemented using, for example, a software application available from CADENCE DESIGN SYSTEMS, Inc. etc. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0130] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in memory or memory units, such as optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), and similar media.

[0131] Fig.19 1 is a block diagram of an integrated circuit (IC) manufacturing system 1900 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1900 is used to fabricate at least one of the following: (A) one or more semiconductor masks; or (B) at least one component in a layer of a semiconductor integrated circuit.

[0132] exist Fig.19In the present invention, the IC manufacturing system 1900 includes entities such as a design house 1920, a mask house 1930, and an IC manufacturer / fabricator (fab) 1950, which interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1960. The entities in the system 1900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design house 1920, the mask house 1930, and the IC fab 1950 are owned by a single larger company. In some embodiments, two or more of the design facility 1920, the mask facility 1930, and the IC fabrication facility 1950 are simultaneously present in a shared facility and use shared resources.

[0133] The design organization (or design team) 1920 generates an IC design layout 1922. The IC design layout 1922 includes various geometric patterns designed for the IC device 1960. The geometric patterns correspond to the patterns of the metal layers, oxide layers, or semiconductor layers that constitute the various components of the IC device 1960 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1922 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interconnects between layers, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer), and various material layers disposed on the semiconductor substrate. The design organization 1920 implements an appropriate design program to form the IC design layout 1922. The design program includes one or more of a logical design, a physical design, or placement and routing. The IC design layout 1922 exists in one or more data files having information of the geometric patterns. For example, the IC design layout 1922 may be expressed in a GDSII file format or a Design Framework II (DFII) file format.

[0134] The mask mechanism 1930 includes data preparation 1932 and mask fabrication 1944. The mask mechanism 1930 uses the IC design layout 1922 to fabricate one or more masks 1945 of the various layers to be used to fabricate the IC device 1960 according to the IC design layout 1922. The mask mechanism 1930 performs mask data preparation 1932, wherein the IC design layout 1922 is translated into a representative data file (RDF). The mask data preparation 1932 provides the RDF to the mask fabrication 1944. The mask fabrication 1944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1945 or a semiconductor wafer 1953. The design layout 1922 is adjusted by mask data preparation 1932 to comply with the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 1950. Fig.19 In FIG. 1 , mask data preparation 1932 and mask production 1944 are shown as separate components. In some embodiments, mask data preparation 1932 and mask production 1944 may be collectively referred to as mask data preparation.

[0135] In some embodiments, mask data preparation 1932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 1922. In some embodiments, mask data preparation 1932 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) that treats OPC as an inverse imaging problem is also used.

[0136] In some embodiments, mask data preparation 1932 includes a mask rule checker (MRC) that checks the IC design layout 1922 that has gone through each process in OPC with a set of mask creation rules containing certain geometric constraints and / or connectivity constraints to ensure that there is sufficient margin to take into account variability in semiconductor manufacturing processes and achieve similar effects. In some embodiments, MRC modifies the IC design layout 1922 to compensate for the effects of lithography implementation during mask fabrication 1944, which can undo a portion of the modifications performed by OPC to satisfy the mask creation rules.

[0137] In some embodiments, mask data preparation 1932 includes lithography process checking (LPC), which simulates the process to be performed by IC fabrication plant 1950 to fabricate IC device 1960. LPC simulates this process based on IC design layout 1922 to create a simulated fabricated device (e.g., IC device 1960). Process parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with tools used to fabricate ICs, and / or other aspects of the fabrication process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated fabricated device has been created by LPC, if the shape of the simulated device is not close enough to satisfy the design rules, OPC and / or MRC are repeated to further refine IC design layout 1922.

[0138] It should be understood that the above description of mask data preparation 1932 has been simplified for clarity. In some embodiments, data preparation 1932 includes additional features such as logic operations (LOP) to modify IC design layout 1922 according to manufacturing rules. In addition, the processes applied to IC design layout 1922 during data preparation 1932 can be performed in a variety of different orders.

[0139] After the mask data preparation 1932 and during the mask fabrication 1944, a mask 1945 or a group of masks 1945 is fabricated based on the modified IC design layout 1922. In some embodiments, the mask fabrication 1944 includes performing one or more lithographic exposures based on the IC design layout 1922. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanism is used to form a pattern on the mask (photomask or reticle) 1945 based on the modified IC design layout 1922. The mask 1945 can be formed by various techniques. In some embodiments, the mask 1945 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of the mask 1945 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, the mask 1945 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1945, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask fabrication 1944 is used in various processes. For example, such a mask is used in an ion implantation process for forming various doped regions in the semiconductor wafer 1953, an etching process for forming various etched regions in the semiconductor wafer 1953, and / or other suitable processes.

[0140] IC fabrication plant 1950 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC fabrication plant 1950 is a semiconductor foundry. For example, there may be a fabrication facility that provides front-end fabrication (front-end-of-line, FEOL) fabrication) for multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end-of-line, BEOL) fabrication for interconnects and packaging of IC products, and a third fabrication facility may provide other services for the foundry enterprise.

[0141] IC fabrication facility 1950 includes fabrication tool 1952 configured to perform various fabrication operations on semiconductor wafer 1953, thereby fabricating IC device 1960 according to mask (e.g., mask 1945). In various embodiments, fabrication tool 1952 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or a low pressure chemical vapor deposition (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0142] IC fabrication plant 1950 uses mask 1945 fabricated by mask mechanism 1930 to fabricate IC device 1960. Therefore, IC fabrication plant 1950 at least indirectly uses IC design layout 1922 to fabricate IC device 1960. In some embodiments, semiconductor wafer 1953 is fabricated by IC fabrication plant 1950 using mask 1945 to form IC device 1960. In some embodiments, IC fabrication includes performing one or more photolithography exposures based at least indirectly on IC design layout 1922. Semiconductor wafer 1953 includes a silicon substrate or other appropriate substrate with a material layer formed thereon. Semiconductor wafer 1953 also includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar components (formed at subsequent manufacturing steps).

[0143] One aspect of the utility model is related to an integrated circuit device. The integrated circuit device includes: a first type active region semiconductor structure extending in a first direction; a first conductive segment extending in a second direction perpendicular to the first direction; a second type active region semiconductor structure extending in the first direction; and a second conductive segment extending in the second direction. The first conductive segment intersects with the first type active region semiconductor structure at the source region of the first type transistor. The second type active region semiconductor structure is stacked with the first type active region semiconductor structure and offset from the first type active region semiconductor structure along a third direction perpendicular to both the first direction and the second direction. The second conductive segment intersects with the second type active region semiconductor structure at the source region of the second type transistor. The integrated circuit device also includes a front conductive layer and a rear conductive layer each oriented toward the third direction. The front conductive layer is positioned above the first type active region semiconductor structure and the second type active region semiconductor structure. The rear conductive layer is positioned below the first type active region semiconductor structure and the second type active region semiconductor structure. The integrated circuit device further includes: a front power rail extending in the front conductive layer in the second direction; and a rear power rail extending in the rear conductive layer in the second direction. The front power rail is configured to maintain a first supply voltage. The rear power rail extending in the second direction is configured to maintain a second supply voltage. The integrated circuit device further includes: a first through-hole connector directly connected between the first conductive segment and the front power rail; and a second through-hole connector directly connected between the second conductive segment and the rear power rail.

[0144] In some embodiments, the integrated circuit device further comprises: a first gate conductor extending in a second direction perpendicular to the first direction, intersecting the first type active region semiconductor structure at the channel region of the first type transistor; and a second gate conductor extending in the second direction, intersecting the second type active region semiconductor structure at the channel region of the second type transistor. In some embodiments, the integrated circuit device further comprises: a front signal line extending in the second direction in the front conductive layer; a back signal line extending in the second direction in the back conductive layer; and a drain conductive segment extending in the second direction, intersecting one or both of the first type active region semiconductor structure and the second type active region semiconductor structure, and conductively connected to the front signal line or the back signal line through a third through-hole connection. In some embodiments, the first type active region semiconductor structure is located below the second type active region semiconductor structure. In some embodiments, the first type active region semiconductor structure is located above the second type active region semiconductor structure. In some embodiments, each of the first type active region semiconductor structure and the second type active region semiconductor structure includes at least one nanosheet. In some embodiments, each of the first type active region semiconductor structure and the second type active region semiconductor structure includes at least one nanowire. In some embodiments, the first gate conductor is connected to the second gate conductor to form a third gate conductor. In some embodiments, the first gate conductor is separated from the second gate conductor along a third direction by a gate intermediate connector passing through the dielectric material layer.

[0145] Another aspect of the utility model relates to an integrated circuit device. The integrated circuit device includes a first type active region semiconductor structure and a second type active region semiconductor structure stacked with the first type active region semiconductor structure. Each of the first type active region semiconductor structure and the second type active region semiconductor structure extends in a first direction. The integrated circuit device also includes a front conductive layer and a back conductive layer. The front conductive layer is located above the first type active region semiconductor structure and the second type active region semiconductor structure. The back conductive layer is located below the first type active region semiconductor structure and the second type active region semiconductor structure. The integrated circuit device also includes: a plurality of gate conductors extending in a second direction perpendicular to the first direction; and a plurality of conductive segments extending in the second direction. Each of the plurality of gate conductors intersects with one or both of the first type active region semiconductor structure and the second type active region semiconductor structure, and is configured as a gate terminal of at least one transistor. Adjacent gate conductors of the plurality of gate conductors are separated by a pitch distance of a contact poly pitch (“CPP”). Each of the plurality of conductive segments intersects one or both of the first type active region semiconductor structure and the second type active region semiconductor structure and is constructed as a source terminal or a drain terminal of at least one transistor. The integrated circuit device also includes: a plurality of front power rails extending in the second direction in the front conductive layer; and a plurality of back power rails extending in the second direction in the back conductive layer. The front power rails are configured to maintain a first supply voltage, and the back power rails are configured to maintain a second supply voltage. The integrated circuit device also includes: a plurality of front signal lines located between adjacent front power rails; and a plurality of back signal lines located between adjacent back power rails. Each front signal line extends in the second direction in the front conductive layer and occupies a front conductor track selected from a plurality of equally spaced front conductor tracks. Each back signal line extends in the second direction in the back conductive layer and occupies a back conductor track selected from a plurality of equally spaced back conductor tracks.

[0146] In some embodiments, each of the plurality of front power rails occupies at least two conductor tracks selected from the plurality of front conductor tracks. In some embodiments, each of the plurality of rear power rails occupies at least three conductor tracks selected from the plurality of rear conductor tracks. In some embodiments, adjacent front power rails of the plurality of front power rails are separated by a pitch distance of at least four contact polycrystalline pitches. In some embodiments, adjacent rear power rails of the plurality of rear power rails are separated by a pitch distance of at least four contact polycrystalline pitches. In some embodiments, the plurality of front power rails extend in a second direction across a plurality of columns formed by circuit cells arranged along a first direction. In some embodiments, the plurality of rear power rails extend in a second direction across a plurality of columns formed by circuit cells arranged along a first direction. In some embodiments, the plurality of conductive segments include a first conductive segment conductively connected to the front power rail by a first through-hole connector, and wherein the plurality of conductive segments include a second conductive segment conductively connected to the rear power rail by a second through-hole connector. In some embodiments, the through-hole connector is directly connected between the front power rail and one of the plurality of conductive segments. In some embodiments, the through-hole connector is directly connected between the back power rail and one of the plurality of conductive segments.

[0147] Another aspect of the utility model is related to a method for manufacturing an integrated circuit device. The method includes: manufacturing a first type active region semiconductor structure extending in a first direction on a substrate; manufacturing a first conductive segment intersecting the first type active region semiconductor structure at a first source region of a first type transistor; manufacturing a second type active region semiconductor structure extending in the first direction on top of a dielectric material layer; and manufacturing a second conductive segment intersecting the second type active region semiconductor structure at a second source region of a second type transistor. The second type active region semiconductor structure is stacked with the first type active region semiconductor structure. The method also includes: depositing a front side metal layer on a first insulating material and patterning the front side metal layer to form a front side power rail; and forming a rear side metal layer on a rear side of the substrate and patterning the rear side metal layer to form a rear side power rail extending in a second direction. The front side power rail extending in the second direction is conductively connected to the second conductive segment through a front side through-hole connector. The rear side power rail extending in the second direction is conductively connected to the first conductive segment through a rear side through-hole connector. The second direction is perpendicular to the first direction.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated circuit device, characterized in that: include: A first type active region semiconductor structure extending in a first direction; A first conductive segment extending in a second direction perpendicular to the first direction and intersecting the first type active region semiconductor structure at a source region of a first type transistor; A second type active region semiconductor structure extending in the first direction, stacked with the first type active region semiconductor structure, and offset from the first type active region semiconductor structure along a third direction perpendicular to both the first direction and the second direction; A second conductive segment extending in the second direction and intersecting the second type active region semiconductor structure at a source region of the second type transistor; A front conductive layer oriented toward the third direction and positioned above the first type active region semiconductor structure and the second type active region semiconductor structure; a backside conductive layer oriented toward the third direction and positioned below the first type active region semiconductor structure and the second type active region semiconductor structure; a front side power rail extending in the front side conductive layer in the second direction and configured to maintain a first supply voltage; a backside power rail extending in the backside conductive layer in the second direction and configured to maintain a second supply voltage; a first through-hole connector directly connected between the first conductive segment and the front power rail; as well as A second through-hole connector is directly connected between the second conductive segment and the rear power rail.

2. The integrated circuit device according to claim 1, wherein: Also includes: a first gate conductor extending in the second direction perpendicular to the first direction and intersecting the first type active region semiconductor structure at a channel region of the first type transistor; as well as The second gate conductor extends in the second direction and intersects the second-type active region semiconductor structure at the channel region of the second-type transistor.

3. The integrated circuit device according to claim 2, characterized in that The first gate conductor is connected to the second gate conductor to form a third gate conductor.

4. The integrated circuit device according to claim 2, wherein: The first gate conductor is separated from the second gate conductor along the third direction by a gate intermediate connector passing through the dielectric material layer.

5. An integrated circuit device, characterized in that: include: A first type active region semiconductor structure extending in a first direction; A second type active region semiconductor structure extending in the first direction and stacked with the first type active region semiconductor structure; A front conductive layer located above the first-type active region semiconductor structure and the second-type active region semiconductor structure; A rear conductive layer located below the first-type active region semiconductor structure and the second-type active region semiconductor structure; a plurality of gate conductors extending in a second direction perpendicular to the first direction, each of the plurality of gate conductors intersecting one or both of the first type active region semiconductor structure and the second type active region semiconductor structure and configured as a gate terminal of at least one transistor, wherein adjacent gate conductors of the plurality of gate conductors are separated by a pitch distance of one contact poly pitch; a plurality of conductive segments extending in the second direction, each of the plurality of conductive segments intersecting one or both of the first type active region semiconductor structure and the second type active region semiconductor structure and configured as a source terminal or a drain terminal of at least one transistor; a plurality of front side power rails extending in the front side conductive layer in the second direction, wherein a front side power rail of the plurality of front side power rails is configured to maintain a first supply voltage; a plurality of backside power rails extending in the backside conductive layer in the second direction, wherein backside power rails of the plurality of backside power rails are configured to maintain a second supply voltage; a plurality of front side signal lines located between adjacent ones of the plurality of front side power rails, wherein each of the plurality of front side signal lines extends in the second direction in the front side conductive layer and occupies a front side conductor track selected from a plurality of equally spaced front side conductor tracks; as well as A plurality of backside signal lines are located between adjacent backside power rails of the plurality of backside power rails, wherein each backside signal line of the plurality of backside signal lines extends in the second direction in the backside conductive layer and occupies a backside conductor track selected from a plurality of backside conductor tracks that are equally spaced apart.

6. The integrated circuit device according to claim 5, characterized in that Adjacent ones of the plurality of front side power rails are separated by a pitch distance of at least four contact poly pitches.

7. The integrated circuit device according to claim 5, characterized in that Adjacent ones of the plurality of backside power rails are separated by a pitch distance of at least four contact poly pitches.

8. The integrated circuit device according to claim 5, characterized in that The plurality of front-side power rails extend in the second direction across a plurality of columns of circuit cells arranged along the first direction.

9. The integrated circuit device according to claim 5, characterized in that The plurality of backside power rails extend in the second direction across a plurality of columns of circuit cells arranged along the first direction.

10. The integrated circuit device according to claim 5, characterized in that The plurality of conductive segments include a first conductive segment conductively connected to the front side power rail through a first through-via connection, and wherein the plurality of conductive segments include a second conductive segment conductively connected to the back side power rail through a second through-via connection.

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