Enhanced GaN HEMT device

Abstract

The utility model relates to the technical field of power semiconductor device structures, in particular to an enhanced GaN HEMT (High Electron Mobility Transistor) device. The enhanced GaN HEMT device sequentially comprises a substrate, an epitaxial layer, a barrier layer and a SiN / SiO2 laminated layer manufactured on the barrier layer from bottom to top, a window is formed in the SiN / SiO2 laminated layer, and a grid electrode is manufactured at the window. The GaN HEMT device provided by the utility model solves the problem of low threshold voltage of the current HEMT, avoids the problem of threshold reliability caused by etching damage of the barrier layer in the device process, and ensures very high electron mobility under the grid and the switching speed of the device because the 2DEG channel under the grid is reserved.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductor device structures, in particular to an enhanced GaN HEMT device. Background Art

[0002] At present, the main technical means to realize normally-off GaN HEMT power electronic devices are: cascode structure, fluorine ion implantation technology, P-type gate cap layer technology, and recessed gate structure. The normally-off GaN HEMT device realized by the circuit cascade structure has problems such as high cost, circuit series parasitic effects and limited operating temperature. It is currently considered to be one of the transitional solutions for realizing normally-off GaN HEMT devices. Fluorine ion implantation technology uses F-based plasma to treat the AlGaN barrier layer in the area below the gate. The F entering the AlGaN barrier layer will capture electrons to form negatively charged F ions, which will deplete the two-dimensional electron gas channel and realize the device enhancement mode. However, F ion implantation technology will inevitably introduce material damage, and the reliability of the device needs further study. A P-type GaN layer is inserted between the AlGaN / GaN heterojunction and the gate metal. The P-type GaN cap layer can pull up the energy band of the AlGaN barrier layer and thus deplete the two-dimensional electron gas at the heterojunction interface. However, the P-type GaN cap layer technology has the problems of small gate swing and limited gate drive capability. The recessed gate structure reduces the thickness of the barrier layer under the gate, reduces the strength of the piezoelectric polarization at the AlGaN / GaN heterojunction interface, and reduces the concentration of the two-dimensional electron gas, thereby achieving an enhanced device operating mode. However, trench etching damage can lead to problems such as threshold voltage drift.

[0003] Therefore, it is of great significance to develop and design more new HEMT cell structures to improve device performance and reliability. Utility Model Content

[0004] Based on the above description, the utility model provides an enhanced GaN HEMT to solve the problem of low threshold voltage of current HEMT.

[0005] The utility model solves the above technical problems with the following technical solutions: an enhanced GaN HEMT device, which comprises, from bottom to top, a substrate, an epitaxial layer, a barrier layer and a SiN / SiO2 stack made on the barrier layer, wherein a window is opened on the SiN / SiO2 stack, and a gate is made at the window.

[0006] As a preferred implementation, the barrier layer is an ultra-thin barrier layer with a thickness of 2-6 nm.

[0007] As a preferred implementation, the gate is made of p-GaN through secondary epitaxy.

[0008] As a preferred implementation, the gate is p-NiO that is deposited and then oxidized.

[0009] Furthermore, the substrate is a Si substrate, a SiC substrate, or a sapphire substrate.

[0010] Furthermore, the epitaxial layer is a GaN epitaxial layer.

[0011] Furthermore, the barrier layer is an AlGaN layer, an InAlN layer, or an AlN layer.

[0012] As a preferred implementation, a buffer layer is also formed between the epitaxial layer and the substrate.

[0013] Furthermore, a source electrode and a drain electrode are formed on both sides of the gate electrode, and the source electrode and the drain electrode are formed on the barrier layer after opening windows on the SiN / SiO2 stack.

[0014] Compared with the prior art, the core advantages of the technical solution of the present application are: solving the problem of low threshold voltage of the current HEMT, while avoiding the threshold reliability problem caused by barrier layer etching damage in the device process, and because the 2DEG channel under the gate is retained, a very high electron mobility under the gate is guaranteed, thereby ensuring the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A longitudinal cross-sectional view of an enhanced GaN HEMT device provided by an embodiment of the utility model;

[0016] Figure 2 This is a process flow chart of an enhanced GaN HEMT device provided in Example 1 of the utility model;

[0017] Figure 3 This is a process flow chart of an enhancement mode GaN HEMT device provided in Example 2 of the present utility model.

[0018] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0019] 1 substrate, 2 buffer layer, 3 epitaxial layer, 4 barrier layer, 5 SiN / SiO2 stack, 6 gate. DETAILED DESCRIPTION

[0020] like Figure 1 As shown, an enhanced GaN HEMT device includes, from bottom to top, a substrate 1, an epitaxial layer 3, a barrier layer 4, and a SiN / SiO2 stack 5 formed on the barrier layer 4. A window is opened on the SiN / SiO2 stack 5, and a gate 6 is formed at the window.

[0021] The improvement of the above device is that a SiN / SiO2 stack 5 is made on the barrier layer 4, and then a window is opened on the SiN / SiO2 stack 5, and a gate 6 is made at the window position, that is, the gate 6 is located in the window opened in the SiN / SiO2 stack 5 and on the surface of the barrier layer 4.

[0022] In the present invention, the passivation layer SiN is generally a silicon-rich layer with a thickness between 10 and 500 nm. The preparation method can be low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PEVCD). The precursor can be DCS or SiH4 reacts with NH3 to generate SiN. The silicon-rich SiN deposition is achieved by adjusting the gas ratio. The deposition method of SiO2 can be the same as that of SiN.

[0023] The present invention forms a passivation layer of SiN / SiO2 stacked structure on the barrier layer 4, and SiN is used to increase the concentration of 2DEG between the source and drain by more than 10 13 cm -2 , SiO2 is used as a mask to form the gate material only in the gate area, further depleting the channel electrons. This solution can avoid the threshold instability problem caused by traditional groove etching, and because the gate material further depletes the ultra-thin barrier layer, it can further effectively increase the threshold voltage of the HEMT. At the same time, because the 2DEG channel under the gate is retained, the channel carrier migration rate can be greatly improved.

[0024] In the present invention, the barrier layer is an ultra-thin barrier layer with a thickness of 2-6 nm. The gate can be p-GaN made by secondary epitaxy or p-NiO made by oxidation after deposition.

[0025] In the present invention, the substrate 1 is a Si substrate, a SiC substrate or a sapphire substrate, the epitaxial layer 3 is a GaN epitaxial layer, and the barrier layer is an AlGaN layer, an InAlN layer or an AlN layer.

[0026] It is understandable that a buffer layer 2 can be made between the epitaxial layer and the substrate, and a source and a drain are made on both sides of the gate 6. The source and the drain can also be made on the barrier layer by opening windows on the SiN / SiO2 stack.

[0027] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0029] Example 1

[0030] This embodiment provides an enhanced GaN HEMT device and a method for manufacturing the same. Figure 2 , specifically including the following steps:

[0031] (1) Prepare HEMT epitaxial layer and ultra-thin barrier layer on Si or SiC or sapphire substrate, the thickness of ultra-thin barrier layer is 2~6nm;

[0032] (2) Using Si-rich SiN / SiO2 stack for passivation treatment, the 2DEG concentration of HEMT after SiN passivation can reach >10 13 cm -2 ;

[0033] (3) The gate is made by secondary epitaxial p-GaN. The SiN / SiO2 stack is opened at the gate position to create a window for secondary epitaxial growth of p-GaN. The secondary epitaxial p-GaN further pulls up the barrier of the ultra-thin AlGaN and further depletes the 2DEG under the thin barrier layer.

[0034] (4) Make source and drain ohmic contacts and gate metal to complete the fabrication of the HEMT device.

[0035] The completed device structure can be found in Figure 2 .

[0036] Example 2

[0037] This embodiment provides an enhanced GaN HEMT device and a method for manufacturing the same. Figure 3 , specifically including the following steps:

[0038] (1) Prepare HEMT epitaxial layer and ultra-thin barrier layer on Si or SiC or sapphire substrate, the thickness of ultra-thin barrier layer is 2~6nm;

[0039] (2) Using Si-rich SiN / SiO2 stack for passivation treatment, the 2DEG concentration of HEMT after SiN passivation can reach >10 13 cm -2 ;

[0040] (3) A window is opened in the SiN / SiO2 stack at the gate position, and then Ni is deposited at the window, and then oxidized to NiO to obtain p-NiO;

[0041] (4) Make source and drain ohmic contacts and gate metal to complete the fabrication of the HEMT device.

[0042] The completed device structure can be found in Figure 3 .

[0043] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0044] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same drawings throughout the embodiments of the specification mark the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on another element or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An enhancement mode GaN HEMT device, characterized in that: From bottom to top, it includes a substrate, an epitaxial layer, a barrier layer, and a SiN / SiO2 stacked layer formed on the barrier layer. A window is opened on the SiN / SiO2 stacked layer, and a gate is formed at the window.

2. The enhancement mode GaN HEMT device according to claim 1, characterized in that: The barrier layer is an ultra-thin barrier layer, and its thickness is 2-6 nm.

3. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: The gate is p-GaN produced by secondary epitaxy.

4. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: The gate is p-NiO which is oxidized after deposition.

5. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: The substrate is a Si substrate, a SiC substrate or a sapphire substrate.

6. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: The epitaxial layer is a GaN epitaxial layer.

7. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: The barrier layer is an AlGaN layer, an InAlN layer, or an AlN layer.

8. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: A buffer layer is also formed between the epitaxial layer and the substrate.

9. The enhancement mode GaN HEMT device according to claim 1 or 2, characterized in that: A source electrode and a drain electrode are formed on both sides of the gate electrode, and the source electrode and the drain electrode are formed on the barrier layer after opening windows on the SiN / SiO2 stack.

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