High-voltage interlocking compatible circuit

Abstract

A high-voltage interlocking compatible circuit comprises a high-voltage connector, a low-voltage connector, a first optical coupler, a second optical coupler and an MCU. The anode of the first optical coupler is connected with a first electric signal, and the cathode is grounded; a collector electrode of the first optical coupler is connected with a plug-in positive electrode of the low-voltage connector, an emitting electrode of the first optical coupler is connected with a plug-in positive electrode of the high-voltage connector, and a plug-in negative electrode of the low-voltage connector is connected with a plug-in negative electrode of the high-voltage connector; the positive electrode of the second optical coupler is connected with the negative electrode of the plug-in of the low-voltage connector, and the negative electrode is grounded; the collector electrode of the second optical coupler outputs a second electric signal, and the emitter electrode of the second optical coupler is grounded. According to the utility model, hardware interlocking and software interlocking reporting requirements can be simultaneously realized in circuit design. According to the scheme, the compatibility of a hardware circuit of a product is greatly improved, and the design cost of the product can be remarkably reduced.

Description

Technical Field

[0001] The utility model relates to the field of interlocking circuits, in particular to a high-voltage interlocking compatible circuit. Background Art

[0002] The hardware interlocking and software interlocking reporting requirements of traditional PTC cannot be implemented on the same product, resulting in low software and hardware utilization and high design costs.

[0003] Therefore, there is an urgent need for a low-cost, highly compatible, and safe high-voltage interlock compatible design solution. Utility Model Content

[0004] In view of the technical defects and technical drawbacks existing in the prior art, the embodiment of the utility model provides a high-voltage interlock compatible circuit that overcomes the above problems or at least partially solves the above problems. The specific scheme is as follows:

[0005] A high-voltage interlock compatible circuit comprises: a high-voltage connector, a low-voltage connector, a first optical coupler, a second optical coupler and an MCU; the positive electrode of the first optical coupler is connected to a first electrical signal, and the negative electrode is grounded; the collector of the first optical coupler is connected to the positive electrode of a plug-in of the low-voltage connector, the emitter of the first optical coupler is connected to the positive electrode of a plug-in of the high-voltage connector, and the negative electrode of the plug-in of the low-voltage connector is connected to the negative electrode of the plug-in of the high-voltage connector; the positive electrode of the second optical coupler is connected to the negative electrode of the plug-in of the low-voltage connector, and the negative electrode is grounded; the collector of the second optical coupler outputs a second electrical signal, and the emitter of the second optical coupler is grounded.

[0006] Furthermore, the circuit also includes an MCU, the positive electrode of the first optical coupler is connected to the electrical signal output terminal of the MCU, and the collector of the second optical coupler is connected to the electrical signal input terminal of the MCU.

[0007] Furthermore, it is characterized in that the circuit includes a first pull-up resistor, and the positive electrode of the first optical coupler is connected to the first electrical signal through the first pull-up resistor.

[0008] Furthermore, the circuit further comprises a second pull-up resistor, and the collector of the second optical coupler is further connected to a third electrical signal through the second pull-up resistor.

[0009] Furthermore, the circuit also includes a third pull-up resistor, and the positive electrode of the plug-in of the low-voltage connector is also connected to a fourth electrical signal through the third pull-up resistor.

[0010] Furthermore, the circuit also includes a first matching capacitor and a second matching capacitor, the first matching capacitor and the second matching capacitor are connected in series to form a capacitor matching circuit, the two ends of the capacitor matching circuit are respectively connected to the positive electrode and the negative electrode of the high-voltage connector plug-in, and the node between the first matching capacitor and the second matching capacitor is grounded.

[0011] Furthermore, the circuit also includes a first matching resistor and a second matching resistor, the first matching resistor and the second matching resistor are connected in series to form a resistance matching circuit, the two ends of the resistance matching circuit are respectively connected to the positive electrode and the negative electrode of the high-voltage connector plug-in, and the node between the first matching resistor and the second matching resistor is grounded.

[0012] Furthermore, both the positive and negative electrodes of the plug-in of the high-voltage connector are connected to a 0-ohm resistor.

[0013] The utility model has the following beneficial effects:

[0014] The utility model can realize the reporting requirements of hardware interlocking and software interlocking at the same time in circuit design. This solution greatly improves the compatibility of product hardware circuits and can significantly reduce the design cost of products. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A circuit schematic diagram of a high-voltage interlock compatible circuit provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the utility model, not all embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0018] In the description of the present utility model, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; in the description of the present utility model, unless otherwise specified, "multiple" and "several" mean two or more.

[0019] See also Figure 1As shown, a high-voltage interlock compatible circuit provided by an embodiment of the utility model includes a high-voltage connector P2, a low-voltage connector P1, a first optocoupler IC1, a second optocoupler IC2 and an MCU; the positive electrode of the first optocoupler IC1 is connected to a first electrical signal, and the negative electrode is grounded, wherein the first electrical signal is a 5V electrical signal by default; the collector of the first optocoupler IC1 is connected to the positive electrode of the plug-in of the low-voltage connector P1, the emitter of the first optocoupler IC1 is connected to the positive electrode of the plug-in of the high-voltage connector, and the negative electrode of the plug-in of the low-voltage connector P1 is connected to the negative electrode of the plug-in of the high-voltage connector P2; the positive electrode of the second optocoupler IC2 is connected to the negative electrode of the plug-in of the low-voltage connector P1, and the negative electrode is grounded; the collector of the second optocoupler IC2 outputs a second electrical signal, and the emitter of the second optocoupler IC2 is grounded.

[0020] Wherein, the circuit also includes an MCU, the positive electrode of the first optocoupler IC1 is connected to the electrical signal output end of the MCU, and the first electrical signal is provided to the positive electrode of the first optocoupler IC1 through the MCU, and the collector of the second optocoupler IC2 is connected to the electrical signal input end of the MCU, that is, the electrical signal of the collector of the second optocoupler IC2 is received by the MCU.

[0021] The high voltage interlock compatible circuit provided by the utility model has the following working principle:

[0022] When the high-voltage connector P2 is powered on, the first optical coupler IC1 is driven by default in the initial state, so that the high-voltage connector plug-in is directly connected to the corresponding low-voltage connector plug-in PIN pin. At the same time, the MCU determines the level state of the second electrical signal YX-ST output by the collector of the second optical coupler. By default, YX-ST is pulled up to a high level. At this time, the level at YX-ST is pulled down due to the direct connection between the high-voltage and low-voltage connector plug-in PIN pins. The MCU collects the level state of YX-ST and compares it with the interlocking state required by the customer. Here, the hard-line interlocking requirement is 0 and the software interlocking reporting requirement is 1 as an example. When the customer requires It is hard-wire interlock, that is, the demand is 0. At this time, the interlocking form of the initial state is the same as the demand, and the product maintains hard-wire interlock; when the customer demand is reported as software interlock, that is, the demand is 1, the initial interlocking form is different from the demand. At this time, the first electrical signal Interlock_ST of the positive pole of the first optocoupler output by the MCU is at a low level, and the first optocoupler IC1 loses power and does not work, causing the high-voltage connector plug-in and the corresponding low-voltage connector plug-in PIN pin to be not directly connected. At this moment, YX-ST becomes a high level, and the MCU confirms the interlocking state at this time again, and reports the software interlock on the interlocking state bit of the matrix protocol.

[0023] Wherein, the circuit also includes a first pull-up resistor R2, a second pull-up resistor R12 and a third pull-up resistor R11, the positive electrode of the first optical coupler IC1 is connected to the first electrical signal through the first pull-up resistor R2, the collector of the second optical coupler IC2 is also connected to the third electrical signal through the second pull-up resistor R12, and the positive electrode of the plug-in of the low-voltage connector is also connected to the fourth electrical signal through the third pull-up resistor R11.

[0024] In the above embodiment, the first electrical signal, the third electrical signal and the fourth electrical signal are 5V electrical signals by default.

[0025] Among them, the circuit also includes a first matching capacitor C1 and a second matching capacitor C2, the first matching capacitor C1 and the second matching capacitor C2 are connected in series to form a capacitor matching circuit, the two ends of the capacitor matching circuit are respectively connected to the positive electrode and the negative electrode of the high-voltage connector plug-in, and the node between the first matching capacitor C1 and the second matching capacitor C2 is grounded.

[0026] Among them, the circuit also includes a first matching resistor R6 and a second matching resistor R8, the first matching resistor R6 and the second matching resistor R8 are connected in series to form a resistance matching circuit, the two ends of the resistance matching circuit are respectively connected to the positive electrode and the negative electrode of the high-voltage connector plug-in, and the node between the first matching resistor R6 and the second matching resistor R8 is grounded.

[0027] Wherein, the positive and negative electrodes of the plug-in of the high-voltage connector are both connected with a 0-ohm resistor.

[0028] like Figure 1 As shown, the high-voltage connector in the embodiment of the utility model is a MHDR2X2 component, the second pin of the MHDR2X2 is the positive electrode of the high-voltage connector plug-in, the fourth pin of the MHDR2X2 is the negative electrode of the high-voltage connector plug-in, and the low-voltage connector is a MHDR2X4 component, the second pin of the MHDR2X4 is the positive electrode of the high-voltage connector plug-in, and the fourth pin of the MHDR2X4 is the negative electrode of the high-voltage connector plug-in.

[0029] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high voltage interlock compatible circuit, characterized in that: The circuit comprises: a high-voltage connector, a low-voltage connector, a first optical coupler, a second optical coupler and an MCU; the positive electrode of the first optical coupler is connected to a first electrical signal, and the negative electrode is grounded; the collector of the first optical coupler is connected to the positive electrode of a plug-in of the low-voltage connector, the emitter of the first optical coupler is connected to the positive electrode of a plug-in of the high-voltage connector, and the negative electrode of the plug-in of the low-voltage connector is connected to the negative electrode of the plug-in of the high-voltage connector; the positive electrode of the second optical coupler is connected to the negative electrode of the plug-in of the low-voltage connector, and the negative electrode is grounded; the collector of the second optical coupler outputs a second electrical signal, and the emitter of the second optical coupler is grounded.

2. The high voltage interlock compatible circuit according to claim 1, characterized in that: The circuit further includes an MCU, the positive electrode of the first optical coupler is connected to the electrical signal output terminal of the MCU, and the collector of the second optical coupler is connected to the electrical signal input terminal of the MCU.

3. The high voltage interlock compatible circuit according to claim 1, characterized in that: The circuit includes a first pull-up resistor, and the positive electrode of the first optical coupler is connected to a first electrical signal through the first pull-up resistor.

4. The high voltage interlock compatible circuit according to claim 1, characterized in that: The circuit further includes a second pull-up resistor, and the collector of the second optical coupler is further connected to a third electrical signal through the second pull-up resistor.

5. The high voltage interlock compatible circuit according to claim 1, characterized in that: The circuit also includes a third pull-up resistor, and the positive electrode of the plug-in of the low-voltage connector is also connected to a fourth electrical signal through the third pull-up resistor.

6. The high voltage interlock compatible circuit according to claim 1, characterized in that: The circuit also includes a first matching capacitor and a second matching capacitor, the first matching capacitor and the second matching capacitor are connected in series to form a capacitor matching circuit, the two ends of the capacitor matching circuit are respectively connected to the positive electrode and the negative electrode of the high-voltage connector plug-in, and the node between the first matching capacitor and the second matching capacitor is grounded.

7. The high voltage interlock compatible circuit according to claim 1, characterized in that: The circuit also includes a first matching resistor and a second matching resistor, the first matching resistor and the second matching resistor are connected in series to form a resistance matching circuit, the two ends of the resistance matching circuit are respectively connected to the positive electrode and the negative electrode of the high-voltage connector plug-in, and the node between the first matching resistor and the second matching resistor is grounded.

8. The high voltage interlock compatible circuit according to claim 1, characterized in that: The positive and negative electrodes of the plug-in of the high-voltage connector are both connected to a 0-ohm resistor.

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