Integrated chip

Abstract

The utility model provides an integrated chip (IC) which comprises a processing substrate. The processing substrate is provided with a substrate. The semiconductor layer comprises a grating coupler area and an edge coupler area; processing the insulating layer between the substrate and the semiconductor layer; the grating coupler is located in the grating coupler area and comprises a plurality of grooves arranged in the semiconductor layer; the edge coupler is located in an edge coupler region of the semiconductor layer and includes a bottom structure having an end portion proximate to an edge of the insulating layer and a tapered sidewall extending laterally from the end portion; an upper structure extending over the bottom structure, the upper structure having an end proximate an edge of the insulating layer, and tapered sidewalls extending laterally from the end between the tapered sidewalls of the bottom structure; wherein the process substrate extends continuously from directly below the plurality of trenches to directly below the superstructure.

Description

Technical Field

[0001] The utility model relates to an integrated chip. Background Art

[0002] Optical couplers, such as grating couplers and edge couplers, are often used as components in photonic integrated circuits (PICs), which integrate multiple photonic functions. Optical couplers are used to confine and guide light from optical fibers to integrated chips with minimal attenuation. Grating couplers are more compact than edge couplers and allow for greater variation in coupling positions. Edge couplers have higher coupling efficiency and wider bandwidth than grating couplers. Utility Model Content

[0003] The utility model provides an integrated chip (IC), comprising: a processing substrate; a semiconductor layer, comprising a grating coupler region and an edge coupler region; an insulating layer, located between the processing substrate and the semiconductor layer; a grating coupler, located in the grating coupler region, comprising a plurality of grooves arranged in the semiconductor layer; and an edge coupler, located in the edge coupler region of the semiconductor layer, comprising: a bottom structure, having a first end close to the edge of the insulating layer, and a tapered sidewall extending laterally from the first end; and an upper structure, extending above the bottom structure, the upper structure having a first end close to the edge of the insulating layer, and a tapered sidewall extending laterally from the first end between the tapered sidewalls of the bottom structure, wherein the first end of the upper structure is at a first distance from the edge of the insulating layer, and the first end of the bottom structure is at a second distance from the edge of the insulating layer, and the second distance is different from the first distance, and wherein the processing substrate continuously extends from directly below the plurality of grooves to directly below the upper structure.

[0004] The utility model provides an integrated chip (IC), comprising: an insulating layer; a semiconductor layer, located on the insulating layer; a grating coupler, comprising a plurality of grooves arranged in the semiconductor layer; and an edge coupler, comprising: a bottom structure, extending above the insulating layer, the bottom structure having a first end close to the edge of the insulating layer, and a tapered sidewall extending laterally from the first end; an upper structure, extending above the bottom structure, the upper structure having a first end close to the edge of the insulating layer, and a tapered sidewall extending laterally from the first end; and an intermediate structure, extending above the bottom structure and below the upper structure, the intermediate structure having a first end close to the edge of the insulating layer, and a tapered sidewall extending laterally from the first end, wherein the bottom surfaces of the plurality of grooves are flush with the top surfaces of the intermediate structure and the bottom structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1A , 1B 1C show cross-sectional, top, and perspective views of some embodiments of PICs including grating couplers and edge couplers according to the present disclosure.

[0007] Figures 2A-2D , 3A-3C, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A-14C and 15A-15C illustrate a series of incremental manufacturing steps as a series of top views, cross-sectional views and perspective views.

[0008] Fig.16A and 16B Top and cross-sectional views of some embodiments of a PIC including a grating coupler and an edge coupler having a bottom structure and an upper structure are shown.

[0009] Fig.17 A top view of some embodiments of edge couplers having a bonding structure is shown.

[0010] Fig.18 A top view of some embodiments of an edge coupler having a second intermediate structure is shown.

[0011] Fig.19A and 19B Cross-sectional views of some embodiments of PICs comprising a grating coupler and an edge coupler separated by a waveguide are shown.

[0012] Fig. 20 A flow chart showing some embodiments of a method of manufacturing a PIC including a grating coupler and an edge coupler. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one component or feature to another component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Photonic integrated circuits (PICs) use electromagnetic waves to provide high-speed signal communications. The use of electromagnetic waves provides lower power consumption and generates less heat than traditional electrical signals. PICs receive electromagnetic waves through optical couplers. Grating couplers and edge couplers are examples of optical couplers. Edge couplers have higher coupling efficiency and wider bandwidth than grating couplers, although they are most effective when placed at the edge of the chip and take up more space than grating couplers. Grating couplers have a more compact design and may be placed in more space on the chip, but they generally have lower coupling efficiency and lower bandwidth than edge couplers. Due to the trade-offs involved in choosing one type of optical coupler over another, edge couplers and grating couplers have different tasks and functions in PICs, so they are more effective. In many cases, a combination of grating couplers and edge couplers is required to enable the integration of different functions on the same chip. However, it is time-consuming and expensive to form grating couplers and edge couplers separately, making it impractical to use PICs with both edge couplers and grating couplers on the same chip.

[0016] The present disclosure provides a technology for integrating the manufacture of a grating coupler with the manufacture of an edge coupler on the same substrate. First, deep trench etching is performed on a substrate including a semiconductor layer to separate a grating coupler region from an edge coupler region. A first etching is then performed according to a first mask, which results in the formation of multiple grooves in the grating coupler region and etching back a first portion in the edge coupler region to a first depth. A second etching is then performed according to a second mask, extending the first portion of the multiple grooves to a second depth, while also etching back the first portion in the edge coupler region to the second depth. The first etching and the second etching performed on the grating coupler region and the edge coupler region reduce the production cost of PICs using grating couplers and edge couplers on the same substrate because the lithography, patterning, deposition and etching steps used in the method are reduced.

[0017] Figure 1A , 1B 1C show a top view 100a, a cross-sectional view 100b, and a perspective view 100c of some embodiments of PICs including grating couplers and edge couplers according to the present disclosure. Figure 1A , 1B and 1C.

[0018] The PIC includes a semiconductor layer 104 above an insulating layer 102. A handle substrate 101 is below the insulating layer 102. A grating coupler region 106 is within the semiconductor layer 104 on a portion of the PIC, and an edge coupler region 108 is within the semiconductor layer 104 on another portion of the PIC near an edge of the insulating layer 102. The insulating layer 102 extends continuously between the grating coupler region 106 and the edge coupler region 108. An insulating pad 111 is directly above the upper surface of the semiconductor layer 104, and an insulator 116 surrounds the sidewalls of the semiconductor layer 104. The insulator 116 (see Figure 1A ) is not in Figure 1B and 1C Now refer to Figure 1B and 1C 108 to better illustrate the structures in the edge coupler region 108. In some embodiments, the semiconductor layer 104, the insulating layer 102, and the handle substrate 101 are part of a silicon-on-insulator (SOI) substrate. The optical fiber or other optical structure 132a, 132b (in Figure 1C The optical coupler 134 is coupled to the grating coupler region 106 and the edge coupler region 108 (shown in dashed lines in FIG. 1 ). The optical fiber or other optical structure 132a, 132b transmits the electromagnetic wave 134 to the couplers in the grating coupler region 106 and the edge coupler region 108. The optical coupler then further transmits the electromagnetic wave 134 to the PIC (see FIG. Fig.19A ).

[0019] The bottom structure 114, the intermediate structure 112, and the upper structure 110 are stacked to form an edge coupler in the edge coupler region 108. The bottom structure 114 extends to the insulating layer 102, and the upper structure 110 extends to the uppermost surface of the semiconductor layer 104. The bottom structure 114, the intermediate structure 112, and the upper structure 110 have first ends 126a, 126b, 126c facing the same direction, and second ends 128 (shown in dotted lines) are opposite to the first ends 126a, 126b, 126c. In some embodiments, the bottom structure 114, the intermediate structure 112, and the upper structure 110 have adjacent second ends 128. The tapered sidewalls 130a, 130b, 130c extend between the first ends 126a, 126b, 126c and the adjacent second ends 128 of the bottom structure 114, the intermediate structure 112, and the upper structure 110. In some embodiments, the adjacent second ends 128 are within the semiconductor layer 104. In other embodiments, the adjacent second end 128 is at the sidewall of the semiconductor layer 104. In some embodiments, the first end 126c of the upper structure 110 is a first distance L1 from the edge of the insulating layer 102, and the first end 126a of the bottom structure 114 is a second distance L2 from the edge of the insulating layer 102. In further embodiments, the second distance L2 is less than the first distance L1. In other embodiments, the second distance L2 is greater than the first distance L1. In some embodiments, the first end 126b of the intermediate structure 112 is a third distance L3 from the edge of the insulating layer 102, and the third distance L3 is between the first distance L1 and the second distance L2.

[0020] Compared to an edge coupler defined by a single edge coupler, an edge coupler having multiple tapered structures (e.g., bottom structure 114, intermediate structure 112, and upper structure 110) can reduce coupling losses while increasing the bandwidth and alignment tolerance of the edge coupler. Adding multiple tapered structures to the edge coupler also adds greater complexity to the manufacturing method, including increased cost and time for forming the tapered structures. In some embodiments, the backside structure 124 is also in the edge coupler region 108 and is separated from the bottom structure 114 by an extension structure 109 of the semiconductor layer 104.

[0021] A plurality of grooves of different depths are arranged in the grating coupler region 106. A first group of grooves 118 are arranged on one side of the grating coupler region, a second group of grooves 120 are arranged near the first group of grooves 118, and a third group of grooves 122 are arranged near the second group of grooves 120, opposite the first group of grooves 118. In some embodiments, there are one or more additional groups of grooves. In other embodiments, the third group of grooves is omitted, leaving the first and second groups of grooves 118, 120. In some embodiments, the number of the plurality of grooves is between about 10 and 30 grooves, between about 6 and 20 grooves, between about 15 and 40 grooves, or in another suitable range. In some embodiments, the plurality of grooves are equally divided between the groove groups.

[0022] The plurality of trenches in the grating coupler region 106 extend to a plurality of depths 136, 138, 140 (see Figure 1A ). In some embodiments, the depth of the grooves increases from one side of the grating coupler region 106 to the other side. That is, the first group of grooves 118 may have a first depth 136, the second group of grooves 120 may have a second depth 138 greater than the first depth 136, and the third group of grooves 122 may have a third depth 140 greater than the first depth 136. This variation in groove depth reduces the coupling loss between the optical fiber or other optical structure 132a transmitting the electromagnetic wave 134 and the photonic circuit by guiding the electromagnetic wave 134 through the grating coupler in one direction. The multiple depths of the grooves also increase the complexity of the method for forming the grating coupler, adding one or more additional patterning and etching steps to the process. In some embodiments, the first group of grooves 118 of the plurality of grooves extend from the upper surface of the upper structure 110 to a bottom surface that is flush with the upper surface of the intermediate structure 112. That is, the upper surface of the intermediate structure 112 is at a first depth 136 from the upper surface of the upper structure 110.

[0023] Both grating couplers and edge couplers benefit from designs that are manufactured using more complex methods, and the added steps due to this complexity increase the time and resource costs incurred when forming grating couplers and edge couplers separately. The integrated process flow described herein describes a method for forming grating couplers having multiple trench depths and edge couplers having multiple tapered structures using the same photolithography and etching steps during their fabrication, thereby reducing the cost of the complex forms of couplers described previously and the time taken to form the optical components.

[0024] refer to Figures 2A-2D, 3A-3C, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A-14C, and 15A-15C provide cross-sectional views of some embodiments of PICs having edge couplers and grating couplers at various stages of fabrication. Although Figures 2A-2D , 3A-3C, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A-14C and 15A-15C are described as a series of actions, but it should be understood that these actions are not restrictive, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the illustrated and / or described actions can be omitted in whole or in part.

[0025] As shown in the cross-sectional view 200a, the top view 200b, 200c and the perspective view 200d. Figure 2A , 2B , 2C and 2D, a substrate including a processing substrate 101, an insulating layer 102 and a semiconductor layer 104, a first mask 202 and an etch stop layer 204 are formed above the semiconductor layer 104. The first mask 202 covers the grating coupler region 106 and the edge coupler region 108, leaving the area around the edge coupler region 108 exposed. Before forming the first mask 202, an etch stop layer 204 is formed above the insulating pad 111. In some embodiments, the first mask 202 is or includes a photoresist or other suitable material, and / or is formed by photolithography or some other suitable process. In some embodiments, the etch stop layer 204 includes silicon nitride (Si3N4) or the like, and the insulating pad 111 includes silicon dioxide (SiO2) or the like. In some embodiments, the processing substrate 101 and the semiconductor layer 104 each include single crystal silicon, germanium, or the like.

[0026] As shown in the cross-sectional view 300a, the top view 300b and the perspective view 300c. Figure 3A , 3B 3C, deep trench etching 302 is performed on the semiconductor layer 104 according to the first mask 202 to remove the portion of the semiconductor layer 104 outside the grating coupler region 106 and the edge coupler region 108. The deep trench etching 302 exposes the insulating layer 102 below the semiconductor layer 104 and completely isolates the grating coupler region 106 from the edge coupler region 108. In some embodiments, the deep trench etching 302 causes the semiconductor layer in the edge coupler region to have a tapered sidewall. In some embodiments, the deep trench etching 302 may include dry etching.

[0027] As shown in the cross-sectional view 400a and the top view 400b. Figure 4A and 4B , insulator 116 is formed in the opening formed by deep trench etching 302 (see Figures 5A-5C ). In addition, the first mask 202 and a portion of the insulator 116 above the etch stop layer 204 are removed. In some embodiments, a planarization process (e.g., a chemical mechanical planarization (CMP) process) is used to remove the first mask 202 and a portion of the insulator 116. In some embodiments, the insulator 116 is formed by and / or using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or any combination of the foregoing. In some embodiments, the insulator 116 includes silicon dioxide (SiO2) or the like.

[0028] As shown in the cross-sectional view 500a and the top views 500b and 500c. Figure 5A , 5B 5C, a hard mask layer 508, an advanced patterning film (APF) layer 506, a silicon oxynitride layer 504, and a bottom-layer anti-reflective coating (BARC) layer 502 are formed on the etch stop layer 204. In addition, a second mask 510 is formed and patterned over the BARC layer 502. The second mask 510 exposes a series of rectangles in the BARC layer 502 over the grating coupler region 106. The second mask 510 further covers a portion of the edge coupler region 108, leaving the BARC layer 502 over a first portion 512 of the edge coupler region 108 exposed. The first portion 512 corresponds to the region where the bottom structure 114 (see Figure 1A) on the upper surface of the edge coupler region 108. The BARC layer 502 outside the edge coupler region 108 is also exposed. In some embodiments, the hard mask layer 508, the APF layer 506, the silicon oxynitride layer 504 and the BARC layer 502 are formed by and / or using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or any combination of the foregoing. In some embodiments, the second mask 510 is formed by depositing a mask layer and patterning the mask layer into the second mask 510. For example, CVD, PVD, ALD, a spin coating process, some other suitable deposition process, or any combination of the foregoing can be used. Patterning can be performed, for example, by a lithography / etching process or some other suitable patterning process. In some embodiments, the APF layer 506 includes amorphous carbon, etc. In some embodiments, the hard mask layer 508 includes tetraethoxysilane (TEOS), etc.

[0029] As shown in the cross-sectional view 600a, the top view 600b and the perspective view 600c. Fig. 6A , 6B and 6C, performing a second etch 602 to form a groove in the grating coupler region 106 and to etch the first portion 512 in the edge coupler region to a first depth 136. The second etch 602 exposes the tapered sidewalls of the upper structure precursor 110a within the edge coupler region 108. In some embodiments, a portion of the insulator 116 is also etched. In some embodiments, the back portion 124a is also etched. In some embodiments, the second etch 602 is a dry etch. Combining the etching step for forming the grooves for the grating coupler with the tapered structure of the edge coupler results in a more cost-effective PIC that utilizes grating couplers and edge couplers on the same chip. The reduction in cost increases the feasibility of PICs having multiple types and variations of couplers on one chip, thereby allowing for more flexibility in designing the final product.

[0030] As shown in the cross-sectional view 700a and the top views 700b and 700c. Fig. 7A , 7B and 7C, removing the APF layer 506 (see Figures 5A-5C ), silicon oxynitride layer 504, BARC layer 502 and second mask 510, and a third mask 702 is formed above the grating coupler region 106. The edge coupler region 108 is not covered by the third mask 702. Fig. 7AAs shown, the third mask 702 exposes the first portion 106a of the plurality of trenches in the grating coupler region 106 and covers the first group of trenches 118 in the plurality of trenches in the grating coupler region 106. In some embodiments, a planarization process (e.g., a CMP process) is used. In some embodiments, the third mask 702 is formed in the same manner as the second mask 510.

[0031] As shown in the cross-sectional view 800a, the top view 800b and the perspective view 800c. Fig. 8A , 8B 8C, a third etch 802 is performed according to the third mask 702, extending the first portion 106a of the trench in the grating coupler region 106 and further etching the first portion 512 in the edge coupler region to the second depth 312. The third etch 802 exposes the upper surface of the bottom structure 114. The third etch 802 further exposes the tapered sidewalls of the upper structure precursor 110a in the edge coupler region 108. In some embodiments, a portion of the insulator 116 is further etched. In some embodiments, the back portion 124a is also further etched. In some embodiments, the third etch 802 is a dry etch.

[0032] As shown in the cross-sectional view 900a and the top views 900b and 900c. Fig.9A , 9B 9C, the third mask 702 is removed and a fourth mask 902 is formed over the grating coupler region 106 and the edge coupler region 108. Fig.9A As shown, the fourth mask 902 exposes the second portion 106b of the plurality of trenches in the grating coupler region 106 and covers the first group of trenches 118 and the second group of trenches 120 of the plurality of trenches in the grating coupler region 106. In some embodiments, the third mask 702 is removed using one or more lift-off processes. In some embodiments, the fourth mask 902 is formed in the same manner as the second mask 510.

[0033] As shown in the cross-sectional view 1000a and the top view 1000b. Fig. 10A and 10B A fourth etch 1002 is performed according to the fourth mask 902 to extend the second portion 106b of the trench in the grating coupler region 106 to the third depth 140. In some embodiments, the backside portion 124a is further etched to expose the upper surface of the backside structure 124. In some embodiments, the fourth etch 1002 is a dry etch.

[0034] As shown in the cross-sectional view 1100a and the top view 1100b. Fig.11A and 11B, forming an insulating layer over the edge coupler region 108 and the grating coupler region 106, and extending the insulator 116 over the semiconductor layer 104 and the hard mask layer 508 (see Fig. 10A ). Insulator 116 extends into the plurality of trenches in grating coupler region 106 and into the opening formed over edge coupler region 108. In some embodiments, insulator 116 comprises an oxide. The insulating layer may be deposited using CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing. In some embodiments, the insulating layer comprises silicon dioxide (SiO2), the same material as insulator 116, or the like.

[0035] As shown in the cross-sectional view 1200a and the top view 1200b. Fig. 12A and 12B , the portion of insulator 116 above etch stop layer 204 is removed. In some embodiments, the portion above etch stop layer 204 is removed using a planarization process (eg, a CMP process).

[0036] As shown in the cross-sectional view 1300a and the top view 1300b. Fig.13A and 13B , the etch stop layer 204 is removed. In some embodiments, the etch stop layer 204 is removed using a wet etching process 1302. In other embodiments, the etch stop layer 204 is removed using a dry etching process.

[0037] As shown in the cross-sectional view 1400a and the top views 1400b and 1400c. Fig.14A , 14B As shown in FIGS. 14C and 14D , a fifth mask 1402 is formed over the grating coupler region 106 and the edge coupler region 108. Fig.14A As shown, the fifth mask 1402 covers the plurality of trenches in the grating coupler region 106 and exposes a portion of the upper structure precursor 110a in the edge coupler region 108. In some embodiments, the fifth mask 1402 is formed in the same manner as the second mask 510.

[0038] As shown in the cross-sectional view 1500a, the top view 1500b and the perspective view 1500c. Fig.15A , 15B and 15C, a fifth etching 1502 is performed according to the fifth mask 1402 to etch the upper structure precursor 110a (see Fig.15A ). The etching of the upper structure precursor 110a exposes the upper surface of the intermediate structure 112 and the sidewalls of the upper structure 110 in the edge coupler region 108. In some embodiments, the fifth etch 1502 is a dry etch. The insulator 116 is not Fig. 15C15 to better illustrate the structure in the edge coupler region. In some embodiments, the fifth etch 1502 etches a portion of the upper surface of the upper structure precursor 110a to a first depth 136.

[0039] Fig.16A and 16B A top view 1600a and a cross-sectional view 1600b of some embodiments of a PIC are shown, including a grating coupler and an edge coupler having a bottom structure and an upper structure. They will be described simultaneously. The insulator 116 is not Fig. 16B 1 to better illustrate the structure in the edge coupler region 108 .

[0040] In some embodiments, the intermediate structure 112 (see Figure 1A ) does not exist between the upper structure 110 and the bottom structure 114. The tapered sidewalls of the upper structure 110 extend from the upper surface of the upper structure 110 to the upper surface of the bottom structure 114. In some embodiments, the third set of grooves 122 (see Figure 1A ), and there are two sets of grooves with two different depths. Omitting the definition of the intermediate structure 112 (see Figure 1A ) and the third set of grooves 122 (see Figure 1A ) will not have dedicated lithography and etching steps for the edge coupler region 108 or the grating coupler region 106. That is, each lithography and etching step that affects the trenches in the grating coupler region 106 will also affect the upper structure 110 or the bottom structure 114 of the edge coupler region 108. This leads to a more integrated approach, such as eliminating dedicated steps for forming the grating coupler or the edge coupler. However, the additional efficiency and losses brought by multiple trench depths and tapered structures in the optical coupler will be reduced compared to optical couplers with more trench depths and tapered structures.

[0041] Fig.17 A top view 1700 of some embodiments of edge couplers with a bonding structure is shown. Insulator 116 (see Figure 1A ) is not shown to better illustrate the structure in the edge coupler region 108.

[0042] In some embodiments, the bonding region 1704 extends from one side of the edge coupler region. In some embodiments, the bonding region 1704 extends from the adjacent second end 128 of the base structure 114. In other embodiments, the bonding region 1704 extends from the end of the base structure 114 facing away from the edge of the insulating layer 102. In some embodiments, the bonding region 1704 includes an additional structure 1702 configured to guide electromagnetic waves from the edge coupler into the PIC. In further embodiments, the extension structure 109 extends into the bonding region 1704.

[0043] In some embodiments, the first ends 126a, 126b, 126c of the bottom structure 114, the middle structure 112, and the upper structure 110 have a first width w1, a second width w2, and a third width w3, respectively. The first width w1 is smaller than the second width w2, and the second width w2 is smaller than the third width w3. In further embodiments, the adjacent second ends 128 of the bottom structure 114, the middle structure 112, and the upper structure 110 have a fourth width w4 that is larger than the first width w1, the second width w2, and the third width w3. In some embodiments, the first width w1 is approximately between 60 and 80 nanometers, etc. In some embodiments, the second width w2 is approximately between 70 and 90 nanometers, etc. In some embodiments, the third width w3 is approximately between 90 and 110 nanometers, etc. In some embodiments, the fourth width w4 is approximately between 150 and 600 nanometers, etc.

[0044] Fig.18 A top view 1800 of some embodiments of an edge coupler having a second intermediate structure is shown.

[0045] In some embodiments, the edge coupler region 108 has an additional intermediate structure 1802 between the intermediate structure 112 and the bottom structure 114. The additional intermediate structure 1802 can reduce the coupling loss of the edge coupler by changing the modal distribution of the propagating electromagnetic wave through the edge coupler in smaller increments. In some embodiments, the first end 126a of the bottom structure 114 is at the edge of the insulating layer 102 or faces the edge of the insulating layer 102. In some embodiments, the first end 126a of the bottom structure 114 is separated from the edge of the insulating layer 102 by the insulator 116. The insulator 116 can protect the end of the bottom structure 114 from damage caused by etching and cutting of the insulating layer 102.

[0046] In some embodiments, the backside structure 124 (see Figure 1A ) and extension structure 109 (see Figure 1A ) are omitted. This is done to save space on the PIC.

[0047] Fig.19A and 19B Cross-sectional views 1900a, 1900b of some embodiments of a PIC comprising a grating coupler and an edge coupler separated by a waveguide are shown.

[0048] like Fig.19A As shown in the cross-sectional view 1900a of FIG. 1 , in some embodiments, the intermediate region 1902 is formed in the semiconductor layer 104. The intermediate region 1902 includes a plurality of waveguides, lasers, polarizers and other photonic circuit components 1904 to form the PIC. The grating coupler and the edge coupler guide the electromagnetic wave 134 into the photonic circuit component 1904.

[0049] In some embodiments, the first group of trenches 118 in the grating coupler region 106 have a bottom surface flush with the first depth 136, while the second group of trenches 120 extend to the second depth 138, and the third group of trenches 122 extend to the third depth 140. In further embodiments, the uppermost surface of the intermediate structure 112 is at the first depth 136 from the top of the semiconductor layer 104, the uppermost surface of the bottom structure 114 is at the second depth 138, and the uppermost surface of the back structure 124 is at the third depth 140. That is, the first group of trenches 118 extend to a depth level with the uppermost surface of the intermediate structure 112, the second group of trenches 120 extend to a depth level with the uppermost surface of the bottom structure 114, and the third group of trenches 122 extend to a depth level with the uppermost surface of the back structure 124. In some embodiments, the semiconductor layer extends from the top of the semiconductor layer to a fourth depth 1906, and the first depth 136 is less than half of the fourth depth 1906, while the third depth 140 is greater than half of the fourth depth 1906. In further embodiments, the second depth 138 is approximately half of the fourth depth 1906. In some embodiments, the first depth 136 is approximately 50 to 80 nanometers, approximately 30 to 65 nanometers, approximately 65 to 100 nanometers, etc. In some embodiments, the second depth 138 is approximately 115 to 145 nanometers, approximately 95 to 130 nanometers, approximately 130 to 165 nanometers, etc. In some embodiments, the third depth 140 is approximately 180 to 210 nanometers, approximately 160 to 195 nanometers, approximately 195 to 230 nanometers, etc. In some embodiments, the fourth depth 1906 is approximately 245 to 275 nanometers, approximately 225 to 260 nanometers, approximately 260 to 295 nanometers, etc.

[0050] like Fig.19B As shown in the cross-sectional view 1900b, in some embodiments, the first ends 126a, 126b, 126c (see Figures 1A-1C ) are adjacent at adjacent first ends 126, and second ends 128a, 128b, 128c of the bottom structure 114, the intermediate structure 112, and the upper structure 110 are horizontally offset from each other. In this configuration, the width of the adjacent first ends 126 is greater than the width of the second ends 128a, 128b, 128c. That is, the width of the second ends 128a, 128b, 128c is less than the width of the adjacent first ends 126. In some embodiments, the width of the second ends 128a, 128b, 128c is approximately equal to the width w1, w2, w3 of the first ends 126a, 126b, 126c, such as Fig.17 described.

[0051] Fig. 20A method 2000 of forming a PIC with an edge coupler and a grating coupler according to some embodiments is shown. Although the method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be performed in an order different from the order shown, and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some of the illustrated actions or events can be omitted, and other unillustrated actions or events can be included.

[0052] At block 2002, a deep trench etch is performed through a semiconductor layer of a substrate, exposing an edge coupler region having tapered sidewalls extending between a first end and a second end opposite the first end. See, for example, FIG. 7 .

[0053] At block 2004, a first etch is performed on the substrate resulting in a first plurality of trenches extending to a first depth and a first portion of the edge coupler region being etched to the first depth. See, for example, FIG.

[0054] At block 2006, a second etch is performed on the substrate, the second etch extending the first portion of the first plurality of trenches to a second depth and etching the first portion of the edge coupler region to a second depth, thereby exposing the upper surface of the bottom structure and the tapered sidewalls of the intermediate structure within the edge coupler region. See, for example, FIG. 12 .

[0055] At block 2008, a third etch is performed on the substrate to extend the second portion of the first plurality of trenches to a third depth. See, for example, FIG.

[0056] At block 2010, a fourth etch is performed on the substrate, resulting in a second portion of the edge coupler region being etched to a first depth, exposing the tapered sidewalls of the upper structure within the edge coupler region and the upper surface of the intermediate structure. See, for example, FIG.

[0057] Thus, the present disclosure is directed to a method of forming a photonic integrated circuit including an edge coupler and a grating coupler.

[0058] Some embodiments relate to an integrated chip (IC) comprising: a processing substrate; a semiconductor layer comprising a grating coupler region and an edge coupler region; an insulating layer located between the processing substrate and the semiconductor layer; a grating coupler located in the grating coupler region, comprising a plurality of grooves arranged in the semiconductor layer; and an edge coupler located in the edge coupler region of the semiconductor layer, comprising: a bottom structure having a first end near an edge of the insulating layer and tapered sidewalls extending laterally from the first end; and an upper structure extending above the bottom structure, the upper structure having a first end near the edge of the insulating layer and tapered sidewalls extending laterally from the first end between the tapered sidewalls of the bottom structure, wherein the first end of the upper structure is at a first distance from the edge of the insulating layer, and the first end of the bottom structure is at a second distance from the edge of the insulating layer, and the second distance is different from the first distance, and wherein the processing substrate extends continuously from directly below the plurality of grooves to directly below the upper structure.

[0059] In some embodiments, the plurality of grooves extend into the semiconductor layer such that a first groove and a second groove of the plurality of grooves have a bottom surface at a first depth, and a third groove and a fourth groove of the plurality of grooves have a bottom surface at a second depth greater than the first depth.

[0060] In some embodiments, the IC also includes an intermediate structure, perpendicular to the upper structure and the bottom structure and having a first end close to the edge of the insulating layer, wherein the first end of the intermediate structure is at a third distance from the edge of the insulating layer, and the third distance is greater than the first distance and less than the second distance.

[0061] In some embodiments, a groove of the plurality of grooves extends from an upper surface of the upper structure to a bottom surface that is flush with an upper surface of the intermediate structure.

[0062] In some embodiments, the width of the first end of the bottom structure is less than the width of the first end of the upper structure, wherein the upper structure has a second end contacting the tapered sidewall, wherein the bottom structure has a second end contacting the tapered sidewall, and wherein the second end of the bottom structure is flush with the second end of the upper structure.

[0063] In some embodiments, the second end of the bottom structure faces the edge of the insulating layer.

[0064] In some embodiments, the first end of the bottom structure is spaced apart from the edge of the insulating layer by an insulator.

[0065] In some embodiments, a groove of the plurality of grooves extends from an upper surface of the upper structure to below an upper surface of the base structure.

[0066] In some embodiments, the first end of the bottom structure faces an edge of the insulating layer.

[0067] Other embodiments relate to an integrated chip (IC) comprising: an insulating layer; a semiconductor layer located on the insulating layer; a grating coupler comprising a plurality of grooves arranged in the semiconductor layer; and an edge coupler comprising: a bottom structure extending above the insulating layer, the bottom structure having a first end near an edge of the insulating layer, and a tapered sidewall extending laterally from the first end; an upper structure extending above the bottom structure, the upper structure having a first end near the edge of the insulating layer, and a tapered sidewall extending laterally from the first end; and an intermediate structure extending above the bottom structure and below the upper structure, the intermediate structure having a first end near the edge of the insulating layer, and a tapered sidewall extending laterally from the first end, wherein bottom surfaces of the plurality of grooves are flush with top surfaces of the intermediate structure and the bottom structure.

[0068] In some embodiments, the tapered side walls of the bottom structure, the middle structure, and the upper structure are joined together at a first distance from the edge of the insulating layer, wherein the bottom structure, the middle structure, and the upper structure have a first width, respectively, and wherein the first ends of the bottom structure, the middle structure, and the upper structure have a second width, a third width, and a fourth width, respectively, wherein the second width, the third width, and the fourth width are smaller than the first width.

[0069] In some embodiments, the first width is less than the second width and the third width, and wherein the second width is less than the third width.

[0070] In some embodiments, a top surface of the intermediate structure is flush with bottom surfaces of the first and second trenches of the plurality of trenches.

[0071] In some embodiments, a top surface of the bottom structure is flush with bottom surfaces of a third trench and a fourth trench of the plurality of trenches.

[0072] Still other embodiments relate to a method of forming a grating coupler and an edge coupler on an integrated chip (IC), comprising: performing deep trench etching through a semiconductor layer of a substrate to expose an edge coupler region having a tapered sidewall extending between a first end and a second end opposite to the first end; performing a first etch on the substrate, causing a first plurality of trenches to extend to a first depth, and a first portion of the edge coupler region to be etched to the first depth; performing a second etch on the substrate, the second etch extending the first portion of the first plurality of trenches to a second depth, and etching the first portion of the edge coupler region to the second depth, exposing an upper surface of a bottom structure within the edge coupler region and the tapered sidewall of an intermediate structure; performing a third etch on the substrate to extend the second portion of the first plurality of trenches to a third depth; and performing a fourth etch on the substrate, causing a second portion of the edge coupler region to be etched to the first depth, exposing the tapered sidewall of the upper structure within the edge coupler region and the upper surface of the intermediate structure.

[0073] In some embodiments, the second portion of the edge coupler region has a tapered sidewall exposed after the first etch, and wherein the tapered sidewall is covered by an insulator in the fourth etch.

[0074] In some embodiments, a first end of the bottom structure is exposed in the deep trench etching, a first end of the middle structure is exposed in the second etching, and a first end of the upper structure is exposed in the fourth etching.

[0075] In some embodiments, the method further includes: before the first etching, depositing an etch stop layer on the substrate; after the third etching, depositing an insulating layer in the first plurality of trenches and above the tapered sidewalls of the intermediate structure exposed by the second etching; performing a CMP process to remove a portion of the insulating layer above the etch stop layer; and removing the etch stop layer before the fourth etching.

[0076] In some embodiments, the first, second, and third etches further include etching a second plurality of trenches between the first plurality of trenches and the edge coupler region, wherein the second plurality of trenches delineate a waveguide between the first plurality of trenches and the edge coupler region.

[0077] In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate, wherein the semiconductor layer of the SOI substrate extends to a fourth depth, and wherein the first depth is less than half of the fourth depth and the third depth is greater than half of the fourth depth.

[0078] It should be understood that in this written description and the appended claims, the terms "first", "second", "second", "third" are merely general identifiers used for ease of description to distinguish different elements of a figure or series of figures. By themselves, these terms do not imply any temporal ordering or structural proximity of these elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or non-illustrated embodiments. For example, a "first dielectric layer" described in conjunction with a first figure does not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and does not necessarily correspond to a "first dielectric layer" of an embodiment not described in the figure.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, characterized in that: include: processing substrates; a semiconductor layer including a grating coupler region and an edge coupler region; an insulating layer, located between the processing substrate and the semiconductor layer; a grating coupler located in the grating coupler region, comprising a plurality of trenches arranged in the semiconductor layer; as well as An edge coupler, located in the edge coupler region of the semiconductor layer, comprising: a bottom structure having a first end proximate an edge of the insulating layer and a tapered sidewall extending laterally from the first end; as well as an upper structure extending above the bottom structure, the upper structure having a first end proximate the edge of the insulating layer and tapered sidewalls extending laterally from the first end between the tapered sidewalls of the bottom structure, wherein the first end of the upper structure is at a first distance from the edge of the insulating layer, and the first end of the bottom structure is at a second distance from the edge of the insulating layer, and the second distance is different from the first distance, and The processing substrate continuously extends from directly below the plurality of trenches to directly below the upper structure.

2. The integrated chip according to claim 1, characterized in that: The plurality of trenches extend into the semiconductor layer such that a first trench and a second trench of the plurality of trenches have bottom surfaces at a first depth, and a third trench and a fourth trench of the plurality of trenches have bottom surfaces at a second depth greater than the first depth.

3. The integrated chip according to claim 1, characterized in that: It also includes an intermediate structure, which is perpendicular to the upper structure and the bottom structure and has a first end close to the edge of the insulating layer, wherein the first end of the intermediate structure is at a third distance from the edge of the insulating layer, and the third distance is greater than the first distance and less than the second distance.

4. The integrated chip according to claim 1, characterized in that: The width of the first end of the bottom structure is smaller than the width of the first end of the upper structure, wherein the upper structure has a second end contacting the tapered sidewall, wherein the bottom structure has a second end contacting the tapered sidewall, and The second end of the bottom structure is flush with the second end of the top structure.

5. The integrated chip according to claim 1, characterized in that: The first end of the bottom structure is spaced apart from the edge of the insulating layer by an insulator.

6. The integrated chip according to claim 1, characterized in that: A groove of the plurality of grooves extends from an upper surface of the upper structure to below an upper surface of the base structure.

7. The integrated chip according to claim 1, characterized in that: The first end of the bottom structure faces an edge of the insulating layer.

8. An integrated chip, characterized in that: include: Insulation layer; A semiconductor layer, located on the insulating layer; a grating coupler comprising a plurality of trenches arranged in the semiconductor layer; as well as Edge coupler, comprising: a bottom structure extending above the insulating layer, the bottom structure having a first end proximate an edge of the insulating layer and a tapered sidewall extending laterally from the first end; an upper structure extending above the bottom structure, the upper structure having a first end proximate the edge of the insulating layer and a tapered sidewall extending laterally from the first end; and an intermediate structure extending above the bottom structure and below the upper structure, the intermediate structure having a first end proximate to the edge of the insulating layer and a tapered sidewall extending laterally from the first end, The bottom surfaces of the plurality of grooves are flush with the top surfaces of the intermediate structure and the bottom structure.

9. The integrated chip according to claim 8, characterized in that: The tapered sidewalls of the bottom structure, the middle structure, and the upper structure are joined together at a first distance from the edge of the insulating layer, wherein the bottom structure, the middle structure, and the upper structure each have a first width, and The bottom structure, the middle structure and the first end of the upper structure have a second width, a third width and a fourth width respectively, wherein the second width, the third width and the fourth width are smaller than the first width.

10. The integrated chip according to claim 8, characterized in that: A top surface of the intermediate structure is flush with bottom surfaces of first and second trenches of the plurality of trenches.

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