Voltage regulation circuit

Abstract

The present disclosure relates to a voltage regulation circuit that receives an input voltage, in particular a DC voltage supply as an input, and outputs a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage, in particular independent of temperature changes. The voltage regulation circuit includes a first circuit branch and a second circuit branch coupled in parallel between an input voltage and ground. The first branch includes a current generator including a first depletion-mode MOSFET transistor coupled between an input voltage and a voltage reference circuit, the gate source voltage of which is a PTAT (proportional to absolute temperature) voltage. The voltage reference circuit comprises a first enhancement mode MOSFET transistor, the gate source voltage of the first enhancement mode MOSFET transistor is CTAT (complementary to absolute temperature) voltage, the source electrode of the first enhancement mode MOSFET transistor is coupled to the ground through a source electrode resistor, and reference voltage is formed on the first enhancement mode MOSFET transistor, namely the sum of PTAT voltage drop on the source electrode resistor and the gate source voltage of the enhancement mode MOSFET transistor.

Description

Technical Field

[0001] The present description relates to a voltage regulation circuit that receives an input voltage, particularly a DC (direct current) voltage supply, and outputs a regulated voltage. Background Art

[0002] In recent years, the rise of GaN (Gallium Nitride) high electron mobility transistor technology has attracted the attention of power electronics designers. Today, the goal is to develop fully integrated power converters with both power devices capable of maintaining high voltages and low-voltage driver devices to create a suitable driver. Due to fewer interconnections between the driver and the power stage, this may lead to several improvements in the direction of obtaining a smaller area, lower cost, improved reliability and reduced parasitic elements. This makes it possible to use all the advantages of GaN-based technology, such as higher breakdown voltage, operating frequency and lower on-resistance compared to usual power MOS devices.

[0003] For example, to realize a monolithic gate driver, several circuit blocks are used along with a stable voltage bias provided by a voltage regulator.

[0004] In order to obtain a stable supply voltage used by other parts of the circuit, the voltage regulator should have a voltage reference generator that provides a low drift voltage.

[0005] Most known architectures use pn junctions to obtain a voltage reference and exploit all devices based on it, from diodes to bipolar transistors. In particular, the operating principle of the so-called bandgap voltage reference is to balance the negative temperature coefficient of the pn junction (usually the voltage V on the base-emitter junction of a bipolar transistor) in a circuit. BE ) and thermal voltage V T The positive temperature coefficient of V T =kT / q.

[0006] In GaN technology, where transistors are based on a two-dimensional electron gas (2DEG), these classical design methods cannot be applied.

[0007] exist Figure 1 , as an example in this regard, a voltage regulation circuit 10 is schematically represented, which receives an input voltage (particularly a voltage supply VCC) and outputs a regulated voltage, which is an analog supply voltage VREG, which may be a positive voltage supply VDD, which is stabilized relative to the input voltage (particularly the voltage supply VCC). As shown in the figure, such a voltage is referred to as ground GND.

[0008] In the prior art, most architectures that provide voltage references in circuits that cannot utilize pn junctions can be categorized as:

[0009] External reference, such as a Zener diode: This approach presents several problems, such as limitations in frequency operation due to parasitic components of the bond wires (inductors and capacitors) or large temperature drifts; and

[0010] Internal reference: This approach is very challenging due to the few component types available in GaN technology, such as Schottky diodes, Si-Cr resistors, MIM capacitors, and N-type HEM transistors (depletion and enhancement). Using these components to create a voltage reference with low temperature drift and low line sensitivity is complex.

[0011] Additionally, most internal references use another circuit block to create a regulated voltage that can be used as a voltage bias for other circuit blocks. This means higher current consumption and more complex circuits.

[0012] Furthermore, designing such a circuit block, i.e., a voltage regulator with a voltage reference, also presents several challenges, such as:

[0013] Compensate for voltage drift due to temperature and process variables;

[0014] Loop stability;

[0015] Line sensitivity (depends on supply voltage); and

[0016] Load sensitivity. Utility Model Content

[0017] Various embodiments disclosed herein provide a voltage regulating circuit with a voltage reference that addresses the deficiencies of the prior art.

[0018] According to one or more embodiments, this may be accomplished by a voltage regulation circuit having the features set forth in the following discussion.

[0019] The present disclosure describes solutions for a voltage regulation circuit that receives an input voltage (particularly a DC voltage supply) and outputs a regulated voltage.

[0020] comprising a voltage reference circuit configured to supply a reference voltage that is in particular independent of temperature variations,

[0021] The voltage regulation circuit includes a first circuit branch and a second circuit branch coupled in parallel between the input voltage and ground,

[0022] The first branch includes

[0023] a current generator including a first depletion-mode MOSFET transistor coupled between the input voltage and a voltage reference circuit, wherein the gate-source voltage of the first depletion-mode MOSFET transistor is a PTAT (proportional to absolute temperature) voltage,

[0024] The voltage reference circuit includes a first enhancement MOSFET transistor, whose gate-source voltage is a CTAT (complementary to absolute temperature) voltage, whose source is coupled to ground through a source resistor, and a reference voltage is formed thereon, namely, the sum of a PTAT voltage drop on the source resistor and a gate-source voltage of the enhancement MOSFET transistor, the first enhancement MOSFET transistor being arranged on the first branch and coupled to the first depletion MOSFET transistor in a control node through a drain, the control node being coupled to the gate of the first depletion MOSFET transistor,

[0025] The first depletion-mode MOSFET transistor injects a PTAT current in the first branch to determine a PTAT voltage drop across the source resistor,

[0026] The second branch includes an output stage coupled between the voltage to be regulated and an output node at which the regulated voltage is obtained, the output stage includes a second MOSFET transistor at which the output of the output node is obtained, a resistor divider is coupled to the output node, thereby outputting a divided output regulated voltage at a corresponding voltage divider output node, the divided output regulated voltage is used as a process variable input of a negative feedback loop, the negative feedback loop is also coupled to the reference voltage, and the output of the negative feedback loop controls the gate of the second MOSFET transistor.

[0027] In a variant embodiment, in the output stage coupled between the voltage to be regulated and an output node at which the regulated voltage is obtained, the second MOSFET transistor is coupled to the gate of the first depletion MOSFET transistor,

[0028] The negative feedback loop includes coupling the voltage divider output node of the resistor divider with the gate of the first enhancement MOSFET transistor, forming a reference voltage on the first enhancement MOSFET transistor, namely the sum of the PTAT voltage drop on the source resistor and the gate-source voltage of the enhancement MOSFET transistor.

[0029] In a variant embodiment, the enhancement MOS transistor is cascaded with a second enhancement MOSFET transistor, the gate of the first enhancement MOSFET transistor is coupled to ground through a first resistor of a voltage divider, and the gate of the second enhancement MOSFET transistor is coupled to the first resistor through a second resistor and to the output node through a third resistor.

[0030] In a variant embodiment, the gate of the first depletion-mode MOSFET transistor is coupled to its source via a resistor and is coupled to the drain of the first enhancement-mode MOSFET transistor via the second enhancement-mode MOSFET transistor.

[0031] In a variant embodiment, the first depletion MOS transistor and the second MOSFET are cascaded through corresponding third and fourth depletion transistors, in particular, the third depletion transistor is placed between the voltage to be adjusted and the first depletion MOS transistor, and its gate is coupled to the source of the first depletion MOSFET transistor, and the fourth depletion transistor is coupled between the voltage to be adjusted and the second MOSFET transistor, and its gate is coupled to the source of the second MOSFET transistor.

[0032] In a variant embodiment, the gates of the first depletion MOSFET transistor and the second transistor are connected to ground via a capacitor.

[0033] In a variant embodiment, the negative feedback loop includes a differential amplifier whose input is coupled to the voltage divider output node and the control node, the gate of the first enhancement MOSFET transistor is coupled to its drain, and the output of the differential amplifier is coupled to the gate of the second transistor.

[0034] In a variant embodiment, the depletion-mode n-type MOSFET transistor and the enhancement-mode n-type MOSFET transistor are obtained using gallium nitride technology, in particular, they are GaN high electron mobility transistors.

[0035] In an embodiment, the second MOSFET transistor is a second depletion mode MOSFET transistor.

[0036] In an embodiment, the solution described herein also relates to a voltage regulating circuit receiving an input voltage (particularly a DC voltage supply) and outputting a regulated voltage,

[0037] comprising a voltage reference circuit configured to supply a reference voltage that is in particular independent of temperature variations,

[0038] The voltage regulation circuit includes a first circuit branch and a second circuit branch coupled in parallel between the input voltage and ground, including

[0039] The first branch includes

[0040] a current generator including a first depletion-mode MOSFET transistor coupled between the input voltage and a voltage reference circuit, wherein the gate-source voltage of the first depletion-mode MOSFET transistor is a PTAT (proportional to absolute temperature) voltage,

[0041] The voltage reference circuit includes a first enhancement mode MOSFET transistor, whose gate-source voltage is a CTAT (complementary to absolute temperature) voltage, whose source is coupled to ground through a source resistor,

[0042] The first depletion-mode MOSFET transistor injects a PTAT current in the first branch to determine a PTAT voltage drop across the source resistor,

[0043] The second branch comprises an output stage coupled between the voltage to be regulated and an output node at which the regulated voltage is obtained, the output stage comprising a second MOSFET transistor, in particular a depletion MOSFET, coupled to the gate of the first depletion MOSFET transistor,

[0044] The output node is coupled to the gate of the first enhancement MOSFET transistor through a resistor divider, and a reference voltage is formed on the first enhancement MOSFET transistor, that is, the sum of the PTAT voltage drop on the source resistor and the gate-source voltage of the enhancement MOSFET transistor.

[0045] In another aspect of the present disclosure, a voltage regulation circuit is provided, comprising: a first circuit branch and a second circuit branch connected in parallel and coupled between an input voltage and ground, the first circuit branch comprising a current generator, the current generator comprising a first depletion-mode MOSFET transistor, whose gate-source voltage is a proportional to absolute temperature (PTAT) voltage, and the input voltage is a direct current (DC) voltage supply; and a voltage reference circuit, configured to supply a reference voltage that is independent of temperature changes, the first depletion-mode MOSFET transistor coupled between the input voltage and the voltage reference circuit, the voltage reference circuit comprising a first enhancement-mode MOSFET transistor, whose gate-source voltage is a complementary to absolute temperature (CTAT) voltage, and the first enhancement-mode MOSFET The source of the transistor is coupled to ground through a source resistor, a first depletion-mode MOSFET transistor is configured to inject a PTAT current in the first branch, which determines a PTAT voltage drop across the source resistor, a second circuit branch includes an output stage coupled between an input voltage and an output node at which a regulated voltage is output, the output stage includes a second depletion-mode MOSFET transistor coupled to a gate of the first depletion-mode MOSFET transistor; and a resistor divider coupling the output node to a gate of the first enhancement-mode MOSFET transistor, a reference voltage being a sum of the PTAT voltage drop across the source resistor and a gate-source voltage of the first enhancement-mode MOSFET transistor being formed across the first enhancement-mode MOSFET transistor.

[0046] In an embodiment, the first depletion MOSFET transistor and the second depletion MOSFET transistor are cascaded with a third depletion MOSFET transistor and a fourth depletion MOSFET transistor, respectively, the third depletion MOSFET transistor is coupled between the input voltage and the first depletion MOSFET transistor, the gate of the third depletion MOSFET transistor is coupled to the drain of the first depletion MOSFET transistor, the fourth depletion MOSFET transistor is coupled between the input voltage and the second depletion MOSFET transistor, and the gate of the fourth depletion MOSFET transistor is coupled to the source of the MOSFET transistor of the output stage.

[0047] In an embodiment, the voltage regulating circuit further comprises: a second enhancement MOSFET transistor cascaded with the first enhancement MOSFET transistor, a gate of the second enhancement MOSFET transistor coupled to ground via a first resistor of a resistor divider, a gate of the second enhancement MOSFET transistor coupled to the first resistor via a second resistor of the resistor divider and coupled to the output node via a third resistor of the resistor divider.

[0048] In an embodiment, the gates of the first depletion MOSFET transistor and the second depletion MOSFET transistor are coupled to ground through compensation capacitors.

[0049] In an embodiment, the voltage regulating circuit further comprises: a differential amplifier having an input coupled to a node of the resistor divider and a drain of the first enhancement MOSFET transistor, a gate of the first enhancement MOSFET transistor coupled to the drain of the first enhancement MOSFET transistor, and an output of the differential amplifier coupled to the gate of the second depletion MOSFET transistor.

[0050] In an embodiment, the first depletion mode MOSFET transistor and the second depletion mode MOSFET transistor and the first enhancement mode MOSFET transistor are gallium nitride (GaN) high electron mobility transistors.

[0051] In another aspect of the present disclosure, a voltage regulation circuit is provided, comprising: an input node configured to receive an input voltage; a voltage reference circuit coupled to ground, the voltage reference circuit comprising a first enhancement-type transistor; a current generator circuit coupled between the input node and the voltage reference circuit, the current generator circuit comprising a first depletion-type transistor; a voltage divider circuit coupled to ground; an output stage coupled between the input node and the voltage divider circuit, the output stage comprising a second depletion-type transistor; and an output node configured to output a regulated voltage, the output node being located between the voltage divider circuit and the output stage.

[0052] In an embodiment, a voltage reference circuit and a current generator circuit are connected in parallel with the voltage divider circuit and the output stage.

[0053] In an embodiment, the voltage regulating circuit further includes: a capacitor coupled between gates of the first depletion-mode transistor and the second depletion-mode transistor.

[0054] In an embodiment, the voltage regulating circuit further includes a protection circuit including a third depletion-mode transistor coupled between the input node and the first depletion-mode transistor and a fourth depletion-mode transistor coupled between the input node and the second depletion-mode transistor.

[0055] In an embodiment, the voltage regulating circuit further includes an amplifier including a first input coupled to a node between the voltage reference circuit and the current generator circuit, a second input coupled to the voltage divider circuit, and an output coupled to the output stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] One or more embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0057] Figure 1 It is a voltage regulation circuit;

[0058] Figure 2 is a circuit diagram of a voltage regulating circuit according to an embodiment;

[0059] Figure 3 is a circuit diagram of a voltage regulating circuit according to a first yet another embodiment;

[0060] Figure 4 is a circuit diagram of a voltage regulating circuit according to a second embodiment; and

[0061] Figure 5 yes Figure 4 A circuit diagram of an embodiment of a voltage regulating circuit. DETAILED DESCRIPTION

[0062] In the following description, one or more specific details are illustrated to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so that certain aspects of the embodiments will not be obfuscated.

[0063] Reference to "an embodiment" or "an embodiment" in the framework of this specification is intended to indicate that a particular configuration, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to one and the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] The references used herein are provided for convenience only and therefore do not limit the degree of protection or the scope of the embodiments.

[0065] exist Figure 2 A circuit diagram representing the voltage regulator circuit 20 is shown in FIG.

[0066] Such a voltage regulator circuit 20 receives a DC voltage supply VCC as an input voltage and supplies a regulated voltage VREG at an output node REG, which is regulated to take into account variations determined by a load coupled to the output node REG and also to take into account possible variations of the input voltage VCC. In an embodiment, the regulated voltage VREG may correspond to an analog voltage supply VREG of a gate driver in GaN technology, for example.

[0067] As shown, such a voltage regulating circuit 20 includes a voltage reference circuit, generally indicated at 50, which is configured to supply a reference voltage VREF that is particularly independent of temperature variations. In particular, the voltage reference circuit 50 described herein is configured to operate in some respects in a manner similar to a bandgap reference circuit, particularly providing components having negative temperature coefficients and components having positive temperature coefficients.

[0068] Then, the voltage regulating circuit 20 comprises a current generator circuit 31 and an output stage 33. The current generator circuit 31 is coupled at its input to the input voltage VCC. The voltage divider circuit 40 is coupled via a voltage divider output node A of the voltage divider circuit 40 (i.e., a node at which the divided voltage is obtained, in particular in the example between the resistor R3 and the resistor R4) to a voltage reference circuit 50, which is also coupled to such current generator circuit 31 via a control node C. The voltage regulating circuit 20 comprises a first circuit branch B1 and a second circuit branch B2 connected in parallel, each branch being coupled between said input voltage VCC and ground GND.

[0069] On the first branch B1, there is arranged such a current generator circuit 31 coupled to the input voltage VCC, which includes a first depletion type n-type MOSFET QD2, i.e., having an n-channel operating in depletion mode, whose drain is coupled to the input voltage VCC and whose source is coupled to the source resistor R1. Therefore, a current ID2 equal to (-VGS(QD2)) / R1 (where VGS(QD2) is the gate-source voltage of the first depletion type n-type MOSFET QD2) flows into the first branch B1, specifically into the enhancement type MOSFET QE2, and in particular into the resistor R5.

[0070] The voltage reference circuit 50 actually comprises on a first branch B1 a first enhancement n-type (ie n-channel operating in enhancement mode) MOSFET transistor QE2, whose source is coupled to ground GND via a source resistor R5 and which is coupled to a control node C via its drain.

[0071] The second circuit branch B2 includes a second depletion type n-type MOSFET transistor QD4, whose drain is coupled to the input voltage VCC and whose source, i.e., the output node REG, outputs the regulated voltage VREG. The gates of the second depletion type n-type MOSFET transistor QD4 and the first depletion type n-type MOSFET QD2 are coupled together and coupled to the control node C. The second depletion type n-type MOSFET transistor QD4 can also be defined as a transfer transistor. Such a gate electrode is coupled to the ground GND via the compensation capacitor CC. As described above, in a variant embodiment, the second depletion type n-type MOSFET transistor QD4 can be replaced by an enhancement type n-type MOSFET transistor.

[0072] The second depletion mode n-type MOSFET transistor QD4 represents the output stage 33, with its gate operating as a control input coupled to the control node C and an output at the source corresponding to the output node REG. Therefore, the output terminal of the current generator 31 can be considered to correspond to the drain of the enhancement mode MOSFET transistor QE1, i.e., the node C, which represents the input terminal of the output stage 33, and the output terminal of the output stage 33, i.e., the output node REG, outputs the regulated voltage VREG.

[0073] Then, a voltage divider circuit 40 is provided on a second branch B2 between the source of the second depletion type n-type MOSFET transistor QD4 (i.e., the regulated output node REG) and the ground GND. The voltage divider 40 includes three resistors R2, R3, and R4 connected in series. The resistor R2 is coupled to the regulated output node REG, and the regulated voltage VREG is obtained at the regulated output node REG. The resistor R4 is coupled to the ground GND. The common node between the resistor R3 and the resistor R4 is coupled to the voltage divider output node A, at which the reference voltage VREF is obtained.

[0074] Therefore, the proposed architecture embeds the voltage reference and the voltage regulator in one circuit, using the voltage reference circuit 50 as part of the feedback network to regulate the output voltage VREG.

[0075] As indicated, in Figure 2 In the circuit, there are two types of N-type transistors:

[0076] Depletion-type QDs, such as QD2 and QD4, have a gate-source voltage of PTAT (proportional to absolute temperature); and

[0077] The gate-source voltage of an enhanced QE, such as QE2, is CTAT (complementary to absolute temperature).

[0078] Therefore, a current ID2 equal to (-VGS(QD2)) / R1 flows into the first circuit branch B1, thereby generating a PTAT voltage drop VP across the resistor R5 equal to ID2*R5=-VGS(QD2)*R5 / R1, because it is proportional to the gate-source voltage of the first depletion-type n-type MOSFET transistor QD2. The resistance value of the resistor R1 at the source of the first depletion-type n-type MOSFET transistor QD2 is selected to obtain the desired bias current value. The reference voltage VREF is obtained at the gate of the MOSFET QE2 coupled to the voltage divider output node A as the sum of the voltage drop VP across the resistor R5 and the gate-source voltage VGS(QE2) (i.e., CTAT) across the first enhancement-type n-type MOSFET QE2, as previously described. Thus, the voltage reference circuit 50 essentially comprises a first enhancement n-type MOSFET QE2 which provides a CTAT contribution through its gate-source voltage VGS(QE2) and a voltage drop VP across a resistor R5 which originates from the current of the generator 31 comprising a PTAT first depletion n-type MOSFET transistor QD2. The reference voltage VREF is also a fixed potential in the voltage divider 40. Thus, the regulated voltage VREG is obtained as:

[0079] VREG=((R2+R3+R4) / R4)*VREF=((R2+R3+R4) / R4)*(VGS(QE2)+(-VGS(QD2)·R5 / R1)

[0080] Therefore, the CTAT contribution and the PTAT contribution produced by the current ID2 of the current generator 31 compensate each other. The ratio of the resistor R5 to the resistor R1 can be set to eliminate any temperature dependency.

[0081] In the second branch B2, QD4 represents the output transistor of the regulator, thereby generating a regulated voltage VREG, while R2, R3 and R4 act as a voltage divider 40 and a negative feedback network as described, thereby biasing the gate voltage of the enhancement MOSFET QE2. In particular, changes in the current drawn by the load at the output node REG on the second branch B2, for example, are returned to the first branch B1 by the arrangement through the voltage divider 40 to control the bias of the gate of the enhancement MOSFET QE2, the gate bias of which changes the current flowing in the first branch B1 and thus changes the voltage of the control node C, which is also specifically coupled directly to the gate of the output MOSFET QD4 in the embodiment shown, thereby controlling its output, namely the regulated voltage VREG. In other words, if the regulated voltage VREG decreases, then due to the increase in load current, the gate voltage of the enhancement MOSFET QE2 is pulled down through the resistor divider, thereby reducing the conduction of the MOSFET QE2 itself, and then the voltage of the control node C and the gate voltage of the output MOSFET QD4 are pulled up, and the regulated voltage VREG increases accordingly, thereby returning to a steady state. During the adjustment of the regulated voltage VREG, the reference voltage VREF may experience transient changes, but in any case returns to its value in the steady state.

[0082] Figure 3 , which further comprises a cascade protection, in particular a protection cascade circuit 32 formed by depletion MOSFET transistors QD1 and QD3. The current generator circuit 31 is coupled at its input to the input voltage VCC, in particular via the protection cascade circuit 32.

[0083] On the first branch B1, such a current generator circuit 31 is arranged, which is coupled to the input voltage VCC and comprises a first depletion type n-type MOSFET QD2, whose drain is coupled to the input voltage VCC and whose source is coupled to the source resistor R1. In the embodiment shown, with the insertion of the cascode 32, the drain of the MOSFET is coupled to the input voltage VCC by coupling to the source of the MOSFET QD1, which in turn is coupled to the input voltage VCC.

[0084] In the second circuit branch B2, the drain of the second depletion n-type MOSFET transistor QD4 is coupled to the input voltage VCC through the protection cascade circuit 32, and its source, i.e., the output node REG, outputs the regulated voltage VREG. The gates of the second depletion n-type MOSFET transistor QD4 and the first depletion n-type MOSFET QD2 are coupled together and coupled to the control node C. These gate electrodes are coupled to the ground GND through the compensation capacitor CC. Therefore, the drains of the two gate-coupled depletion n-type MOSFETs QD2 and QD4 are coupled to the input voltage VCC through the protection cascade, i.e., the gate of the depletion n-type MOSFET QD1 is coupled to the source of the first depletion n-type MOSFET transistor QD2, its source is coupled to the drain of the first depletion n-type MOSFET transistor QD2 and its drain is coupled to the supply voltage VCC, and the gate of the depletion n-type MOSFET QD3 is coupled to the source of the depletion n-type MOSFET transistor QD4, its source is coupled to the drain of the second depletion n-type MOSFET transistor QD4 and its drain is coupled to the regulated voltage VCC.

[0085] Depletion mode MOSFET transistors QD1 and QD3 are therefore used in a cascade configuration with respective transistors QD2 and QD4 to improve power supply rejection and thus extend the supply voltage range.

[0086] In addition, the enhancement MOSFET QE1 is used as a cascode to reduce the voltage tracking of the reference voltage VREF. To this end, the voltage reference circuit 50 therefore includes a first enhancement n-type MOSFET transistor QE2 on the first branch B1, whose source is coupled to the ground GND through the source resistor R5, and Figure 2 , which is coupled through its drain to the control node C. As described above, the circuit 20′ includes another cascade configuration, i.e., the enhancement type n-type MOSFET QE1 is coupled through its drain to the control node C, while its gate is coupled to the common node of the resistors R2 and R3 and its source is coupled to the drain of the first enhancement type n-type MOSFET QE2, the gate of the first enhancement type n-type MOSFET QE2 is coupled to the voltage divider output node A at which the reference voltage VREF is obtained and its source is coupled to the ground GND through the source resistor R5.

[0087] In the voltage regulator circuit 20', in the second branch B2, the MOSFET QD4 still represents the output transistor of the regulator, thereby generating the regulated voltage VREG, and as previously described, R2, R3 and R4 act as a voltage divider 40 and a negative feedback network, thereby biasing the gate voltages of the enhancement MOSFETs QE1 and QE2. In particular, the second depletion type n-type MOSFET transistor QD4 still represents the output stage 33, with its gate operating as a control input coupled to the node C and an output at the source corresponding to the output node REG. Therefore, the output terminal of the current generator 31 can be considered to correspond to the drain of the enhancement MOSFET transistor QE1, i.e., the node C, which represents the input terminal of the output stage 33, and the output terminal of the output stage 33, i.e., the output node REG, outputs the regulated voltage VREG.

[0088] The compensation capacitor CC ensures closed-loop stability.

[0089] The exemplary voltage regulator circuit 20 or 20 ′ provides an average voltage of 6V with low line sensitivity and low temperature spread.

[0090] The voltage regulator circuits 20 and 20' are more suitable for small oscillations of the voltage to be regulated.

[0091] exist Figure 4 In FIG. 1 , another embodiment of the voltage regulator circuit described herein, indicated at 60 , is shown which is more suitable for regulating higher oscillations and which may be used, as an example, for regulating a supply rail for a high current switching load.

[0092] The first branch B1 is substantially similar to the one of the embodiments 20, 20' in that it comprises a current generator circuit 71 comprising a first depletion type n-type, i.e., n-channel MOSFET QD2 operating in depletion mode, whose drain is coupled to the input voltage VCC and whose source is coupled to a source resistor R1. The other end of the resistor is coupled to the control node C.

[0093] The voltage regulator circuit 60 comprises a voltage reference circuit 90 which is similar to the voltage reference circuit 50 and in fact comprises on a first branch B1 a first enhancement n-type, i.e. n-channel, MOSFET transistor QE2 operating in enhancement mode, which is coupled via its source to ground GND via a source resistor R5 and to a control node C via its drain.

[0094] However, in this case, the control node C, ie, the drain of the MOSFET transistor QE2 is short-circuited to its gate, so that the reference voltage VREF formed on the gate also exists on its drain, ie, the control node C.

[0095] Also in this case, the second depletion n-type MOSFET transistor QD4 represents the output stage 33, with its gate operating as the control input. Figure 4 As shown in , the differential amplifier 75 is arranged with its positive input coupled to the control node C, i.e. receiving the reference voltage VREF as input. Then, a voltage divider circuit 80 is provided on the second branch B2 between the source of the second depletion type n-type MOSFET transistor QD4 (i.e. the regulated output node REG) and the ground GND. The voltage divider 80 comprises two resistors R3, R4 connected in series, i.e. the resistor R2 is not shown in this case, but it can certainly be considered to be included in the resistor R3, especially if R2 represents the source resistor of the stage 33. Therefore, in this case, the resistor R3 is coupled to the regulated output node REG at which the regulated voltage VREG is obtained. The resistor R4 is coupled to the ground GND. The common node between the resistor R3 and the resistor R4 is also marked as node A, but in this case is not directly coupled to the gate of the first enhancement type n-type MOSFET transistor QE2, but it is coupled to the negative input of the differential amplifier 75. The output of the differential amplifier 75 is coupled to the gate of the second depletion type n-type MOSFET transistor QD4.

[0096] Thus, here the reference voltage VREF is generated in the same manner, i.e. by the circuit 90 on the gate of QE2, but instead of being coupled to the voltage divider node A, it is coupled to the control node C, which is one of the two inputs of the differential amplifier, the other receiving the voltage on the voltage divider node A, i.e. VREG*R4 / (R3+R4). Thus, the second depletion type n-type MOSFET transistor QD4 is driven by the difference or error between the reference voltage VREF and the regulated voltage VREG, in particular divided by the ratio value of the voltage divider 80, e.g. R4 / (R3+R4). The regulated voltage VREG is the same as described in the other embodiments, or of course minus the R2 resistor:

[0097] VREG=((R3+R4) / R4)*VREF=((R3+R4) / R4)*(VGS(QE2)+(-VGS(QD2)·R5 / R1),

[0098] The resulting regulated voltage is proportional to the divider ratio multiplied by a reference voltage set by the difference between the gate-source voltage of the enhancement MOSFET and the gate-source voltage of the depletion MOSFET on the B1 branch divided by the ratio of the resistances of their source resistors (e.g., R5 and R1).

[0099] exist Figure 5A circuit diagram illustrating an embodiment of a differential amplifier 75 is shown in FIG. 1 , which includes an input pair of enhancement MOSFETs QE6 and QE7 coupled to input terminals (i.e., nodes C and A), whose sources are coupled to a current generator, i.e., a depletion MOSFET QD8, with a source resistor R8, in order to bias the input pair QE6, QE7. The pair of enhancement MOSFETs QE6 and QE7 are also coupled to a supply voltage by a circuit arrangement, wherein their drains are coupled to the sources of respective depletion MOSFETs QD6, QD7, coupled to the supply voltage VCC through the drains, and the gate of MOSFET QD7 is coupled to the gate of QD4. The source of MOSFET QD7 is coupled to the gate of MOSFET QD4 through a resistor R6. The currents in the two branches are fixed by a current generator corresponding to MOSFET QD7 and resistor R6 supplying a given current value and by a current generator corresponding to MOSFET QD8 with resistor R8 supplying a current twice the fixed current value of MOSFET QD7.

[0100] Using a differential amplifier that receives a reference voltage VREF and a voltage proportional to the regulated voltage VREG allows for handling higher oscillations, such as when higher loads are coupled to the regulated voltage node REG.

[0101] Therefore, in this case, the regulated voltage is also fed back by the voltage divider, and the reference voltage is set by the enhancement MOSFET QE2, whose gate-source voltage is CTAT (complementary to absolute temperature), and the input circuit 71 is located on the same branch B1, including the CTAT depletion MOSFET, QD2.

[0102] In this case as well, the gate electrode of the second depletion n-type MOSFET transistor QD4 is coupled to the ground GND via the compensation capacitor CC. In this case as well, in a variant embodiment, the MOSFET QD4 may be an enhancement MOSFET instead of a depletion MOSFET:

[0103] So, in general, the voltage regulation circuit described here includes:

[0104] A voltage reference circuit, such as 50 or 90, is configured to supply a reference voltage (REF) that is particularly independent of temperature variations, and

[0105] A first circuit branch B1 and a second circuit branch B2 are coupled in parallel between the input voltage VCC and the ground GND,

[0106] The first branch B1 includes:

[0107] The current generator, such as 31, 71, comprises a first depletion-mode MOSFET transistor QD2, whose gate-source voltage is proportional to absolute temperature voltage PTAT, coupled between the input voltage VCC and the voltage reference circuit 50 or 90,

[0108] Such a voltage reference circuit 50 or 90 comprises a first enhancement MOSFET transistor, for example QE2, whose gate-source voltage is a CTAT (complementary to absolute temperature) voltage, which is coupled to the ground GND through its source through a source resistor R5, on which a reference voltage (VREF) is formed, that is, the sum of a PTAT voltage drop VP across the source resistor R5 and a gate-source voltage VGS(QE2) of the enhancement MOSFET transistor QE2, the first enhancement MOSFET transistor QE2 being arranged on the first branch B1 and coupled to a first depletion MOSFET transistor QD2 in a control node C through a drain, the control node C being coupled to the gate of the first enhancement MOSFET transistor QE2, and

[0109] A first depletion MOSFET transistor QD2 injects a PTAT current ID2 in the first branch B1, in particular in the control node C, thereby determining a PTAT voltage drop VP across a source resistor, such as R5, and

[0110] The second branch B2, including the output stage 33, 73, is coupled between the voltage for regulating VCC and the output node REG at which the regulated voltage VREG is obtained. The output stage 33, 73 includes a second MOSFET transistor QD4, in particular a depletion-type MOSFET, at which the output of the output node REG is obtained. The resistor divider 40, 80 is coupled to the output node REG, thereby outputting a divided output regulated voltage at the corresponding voltage divider output node A, for example, R4 / (R2+R3+R4) or R4 / (R3+R4), which is input as a process variable of a negative feedback loop, which includes, for example, a MOSFET QE2 or a differential amplifier 75, and which is also coupled to the reference voltage VREF. The output of the negative feedback loop is controlled, that is, the gate of such a second MOSFET transistor QD4 is driven by setting its control voltage.

[0111] A process variable refers to the variable in a negative feedback loop, which is the current measured value of a specific part of the process being monitored or controlled.

[0112] exist Figure 2 , Figure 3In the embodiment of the present invention, the MOSFET QE2 that sets the reference voltage VREF also has the function of controlling the gate of the output MOSFET QD4 in a negative feedback loop. The change of the (divided) voltage VREG is fed back to control the gate of the second MOSFET transistor QD4 through its effect on the MOSFET QE2, which is also coupled (in this case sets) the reference voltage VREF. The gate is controlled by the difference between the divided voltage regulation voltage and the reference voltage REF.

[0113] Therefore, in Figure 2 , Figure 3 In the voltage regulator 20, 20', the output stage 33 is coupled between the regulated voltage VCC and the output node REG, at which such a regulated voltage VREG is obtained, such a second MOSFET transistor QD4 is coupled to the gate of the first depletion MOSFET transistor QD2, in particular to the control node C, and the negative feedback loop includes the coupling of the voltage divider output node A of the resistor divider 40 to the gate of the first enhancement MOSFET transistor QD2, and a reference voltage is formed on the MOSFET transistor QE2, that is, the sum of the PTAT voltage drop VP on the source resistor R5 and the gate-source voltage VGS(QE2) of the enhancement MOSFET transistor (QE2).

[0114] In other words, Figure 2 and Figure 3 The coupling of the components is described in more detail in FIG. 2 , which describes a voltage regulation circuit 20; 20 'receiving an input voltage VCC (in particular a DC voltage supply) as an input and outputting a regulated voltage VREG,

[0115] A voltage reference circuit 50 is included, which is configured to supply a reference voltage VREF which is particularly independent of temperature variations, and

[0116] The voltage regulating circuit 20; 20' comprises a first circuit branch B1 and a second circuit branch B2 coupled in parallel between the input voltage VCC and the ground GND, comprising:

[0117] The first branch B1 includes:

[0118] The current generator 31 comprises a first depletion-mode MOSFET transistor QD2 coupled between the input voltage VCC and the voltage reference circuit 50, and a gate-source voltage thereof is a PTAT (proportional to absolute temperature) voltage,

[0119] The voltage reference circuit 50 comprises a first enhancement type MOSFET transistor QE2, whose gate-source voltage is a CTAT (complementary to absolute temperature) voltage, and whose source is coupled to the ground GND through a source resistor R5.

[0120] The first depletion MOSFET transistor QD2 injects a PTAT current ID2 into the first branch B1, thereby determining a PTAT voltage drop VP across the source resistor R5.

[0121] The second branch B2 comprises an output stage 33 coupled between the regulated voltage VCC and an output node at which the regulated voltage VREG is obtained, the output stage comprising a second MOSFET transistor QD4, in particular a depletion MOSFET, coupled to the gate of the first depletion MOSFET transistor QD2, and

[0122] The output node REG is coupled to the gate A of the first enhancement MOSFET transistor QE2 through a resistor divider 40, and a reference voltage VREF is formed on the first enhancement MOSFET transistor QE2, which is the sum of the PTAT voltage drop VP on the source resistor R5 and the gate-source voltage VGS(QE2) of the enhancement MOSFET transistor QE2.

[0123] exist Figure 4 , Figure 5 In an embodiment, the negative feedback loop includes a differential amplifier 75, whose input is coupled to the voltage divider output node A and the control node C, the gate of the first enhancement MOSFET transistor QE2 is coupled to its drain, and the output of the differential amplifier 75 is coupled to the gate of the second depletion transistor QD4.

[0124] The advantages of the solution described here are clear from the above description.

[0125] The voltage regulator according to the solution described here, using the described circuit arrangement using depletion-mode and enhancement-mode n-channel MOSFETs, obtains regulation of a voltage reference with low line sensitivity and low temperature spread.

[0126] The described circuit also achieves advantages in terms of power consumption, area consumption and cost savings relative to known solutions.

[0127] Without prejudice to the essential principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example, without departing from the scope of protection.

[0128] Depletion mode n-type MOSFET transistors and enhancement mode n-type MOSFET transistors are obtained with gallium nitride technology, in particular the GaN high electron mobility transistor, but it can be used with transistors using other heterojunctions, such as GaAs and AlGaAs, or with other compatible transistor technologies.

[0129] A voltage regulating circuit (20; 20'; 60) receives an input voltage (VCC) (particularly a DC voltage supply as input) and outputs a regulated voltage (VREG), and may include a voltage reference circuit (50; 90) configured to supply a reference voltage (VREF) that is particularly independent of temperature variations, the voltage regulating circuit (20; 20'; 60) comprising a first circuit branch (B1) and a second circuit branch (B2) coupled in parallel between the input voltage (VCC) and ground (GND), the first branch (B1) comprising a current generator (31; 71), the current generator (31; 71) comprising a first depletion MOSFET transistor (Q D2), whose gate-source voltage is a PTAT (proportional to absolute temperature) voltage, coupled between the input voltage (VCC) and a voltage reference circuit (50; 90), wherein the voltage reference circuit (50; 90) comprises a first enhancement MOSFET transistor (QE2), whose gate-source voltage is a CTAT (complementary to absolute temperature) voltage, whose source is coupled to the ground (GND) through a source resistor (R5), and a reference voltage (VREF) is formed thereon, i.e., the sum of a PTAT voltage drop (VP) across the source resistor (R5) and a gate-source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2), wherein the first enhancement MOSFET transistor The invention relates to a first depletion MOSFET transistor (QD2) arranged on the first branch (B1) and coupled to the control node (C) via the drain, the control node (C) being coupled to the gate of the first enhancement MOSFET transistor (QE2), the first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) into the first branch (B1) to determine the PTAT voltage drop (VP) across the source resistor (R5), the second branch (B2) comprising an output stage (33; 73) coupled to the voltage to be regulated (VCC) and to the regulated voltage (VREG) obtained therefrom The output stage (33) includes a second MOSFET transistor (QD4) on which the output of the output node (REG) is partially obtained, and a resistor divider (40; 80) is coupled to the output node (REG), and a divided output regulated voltage (VREG) is output at a corresponding divider output node (A), and the divided output regulated voltage (VREG) is input as a process variable of a negative feedback loop (QE2; 75), and the negative feedback loop (QE2; 75) is also coupled to the reference voltage (VREF), and the output of the negative feedback loop (QE2; 75) controls the gate of the second MOSFET transistor (QD4).

[0130] The output stage (33) can be coupled between the voltage to be regulated (VCC) and an output node at which the regulated voltage (VREG) is obtained, the second MOSFET transistor (QD4) is coupled to the gate of the first depletion MOSFET transistor (QD2), and the negative feedback loop (QE2; 75) includes coupling the voltage divider output node (A) of the resistor divider (40) to the gate of the first enhancement MOSFET transistor (QE2), forming a reference voltage (VREF) at the gate of the first enhancement MOSFET transistor (QE2), that is, the sum of the PTAT voltage drop (VP) on the source resistor (R5) and the gate-source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2).

[0131] The enhancement MOS transistor (QE2) can be cascaded with a second enhancement MOSFET transistor (QE1), the gate of the enhancement MOSFET transistor (QE2) is grounded through the first resistor (R4) of the voltage divider (40), and the gate of the second enhancement MOSFET transistor (QE1) is coupled to the first resistor (R4) through the second resistor (R3) and coupled to the output node through the third resistor (R2).

[0132] The gate of the first depletion MOSFET transistor (QD2) may be coupled to its source via a resistor (R1) and may be coupled to the drain of the first enhancement MOSFET transistor (QE2) in particular via said second enhancement MOSFET transistor (QE1).

[0133] The first depletion MOS transistor (QD2) and the second MOSFET transistor (QD4) can be cascaded through the corresponding third depletion transistor (QD1) and the fourth depletion transistor (QD3), in particular, the third depletion transistor is placed between the voltage to be regulated (VCC) and the first depletion MOS transistor, and its gate is coupled to the drain of the first depletion MOSFET transistor (QD2), and the fourth depletion transistor (QD3) is coupled between the voltage to be regulated (VCC) and the second MOSFET transistor (QD4), and its gate is coupled to the source of the second MOSFET transistor (QD4).

[0134] The gates of the first depletion mode MOSFET transistor (QD2) and the second transistor (QD4) may be connected to ground via a compensation capacitor (CC).

[0135] The negative feedback loop may include a differential amplifier (75) having an input coupled to the voltage divider output node (A) and the control node (C), a gate of the first enhancement mode MOSFET transistor (QE2) coupled to its drain, and an output of the differential amplifier (75) coupled to the gate of the second depletion mode transistor (QD4).

[0136] Depletion mode n-type MOSFET transistors and enhancement mode n-type MOSFET transistors can be obtained using gallium nitride technology, in particular GaN high electron mobility transistors.

[0137] The second MOSFET transistor (QD4) may be a second depletion-mode MOSFET transistor.

[0138] A voltage regulation circuit (20; 20') receiving an input voltage (VCC) (particularly a DC voltage supply) as input and outputting a regulated voltage (VREG) may include a voltage reference circuit (50) configured to supply a reference voltage (VREF) that is particularly independent of temperature variations, the voltage regulation circuit (20; 20') comprising a first circuit branch (B1) and a second circuit branch (B2) coupled in parallel between the input voltage (VCC) and ground (GND), the first branch (B1) comprising a current generator (31), the current generator comprising a first depletion-mode MOSFET transistor (QD2) having a gate-source voltage of a PTAT (proportional to absolute temperature) voltage, coupled between the input voltage (VCC) and the voltage reference circuit (50), the voltage reference circuit (50) comprising a first enhancement-mode MOSFET transistor (QE2) having a gate-source voltage of a CTAT (complementary to absolute temperature) voltage, which is connected through its source through a source resistor (R 5) is coupled to ground (GND), the first depletion MOSFET transistor (QD2) injects a PTAT current (ID2) in the first branch (B1), thereby determining a PTAT voltage drop (VP) across the source resistor (R5), the second branch (B2) comprises an output stage (33) coupled between the voltage to be regulated (VCC) and an output node at which the regulated voltage (VREG) is obtained, the output stage comprises a second MOSFET transistor (QD4), in particular a depletion MOSFET, which is coupled to the gate of the first depletion MOSFET transistor (QD2), the output node (REG) is coupled to the gate (A) of the first enhancement MOSFET transistor (QE2) via a resistor divider (40), a reference voltage (VREF) is formed thereon, namely the sum of the PTAT voltage drop (VP) across the source resistor (R5) and the gate-source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2).

[0139] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments according to the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms given by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A voltage regulating circuit, comprising: a first circuit branch and a second circuit branch connected in parallel and coupled between an input voltage and ground, the first circuit branch including a current generator including a first depletion-mode MOSFET transistor having a gate-source voltage that is a proportional to absolute temperature (PTAT) voltage, the input voltage being a direct current (DC) voltage supply; A voltage reference circuit is configured to supply a reference voltage that is independent of temperature variations, a first depletion-mode MOSFET transistor is coupled between an input voltage and the voltage reference circuit, the voltage reference circuit includes a first enhancement-mode MOSFET transistor, a gate-source voltage of which is a complementary to absolute temperature (CTAT) voltage, The source of the first enhancement mode MOSFET transistor is coupled to ground via a source resistor, A reference voltage is formed across the first enhancement mode MOSFET transistor as a sum of a PTAT voltage drop across the source resistor and a gate-source voltage of the first enhancement mode MOSFET transistor, A first enhancement mode MOSFET transistor is arranged in a first circuit branch, The drain of the first enhancement mode MOSFET transistor is coupled to the first depletion mode MOSFET transistor via a control node, The control node is coupled to the gate of the first enhancement mode MOSFET transistor, a first depletion-mode MOSFET transistor configured to inject a PTAT current in the first circuit branch that determines a PTAT voltage drop across the source resistor, The second circuit branch includes an output stage coupled between an input voltage and an output node at which a regulated voltage is output, The output stage includes MOSFET transistors; as well as A resistor divider is coupled to the output node, the resistor divider being configured to output a divided output regulated voltage at the divider output node, the divided output regulated voltage serving as a process variable input to a negative feedback loop coupled to a reference voltage, the output of the negative feedback loop controlling the gate of a MOSFET transistor of the output stage.

2. The voltage regulator circuit according to claim 1, characterized in that the MOSFET transistor of the output stage is coupled to the gate of the first depletion-mode MOSFET transistor, and The negative feedback loop includes coupling of the voltage divider output node with the gate of the first enhancement mode MOSFET transistor.

3. The voltage regulating circuit according to claim 2, characterized in that it also includes: A second enhancement MOSFET transistor is cascaded with the first enhancement MOSFET transistor, a gate of the second enhancement MOSFET transistor is coupled to ground through a first resistor of the resistor divider, a gate of the second enhancement MOSFET transistor is coupled to the first resistor through a second resistor of the resistor divider and is coupled to the output node through a third resistor of the resistor divider.

4. The voltage regulating circuit according to claim 3, characterized in that the gate of the first depletion MOSFET transistor is coupled to the source of the first depletion MOSFET transistor through a resistor and is coupled to the drain of the first enhancement MOSFET transistor through the second enhancement MOSFET transistor.

5. The voltage regulating circuit according to claim 2, characterized in that the first depletion MOS transistor and the MOSFET transistor of the output stage are cascaded with a third depletion MOSFET transistor and a fourth depletion MOSFET transistor, respectively, A third depletion MOSFET transistor is coupled between the input voltage and the first depletion MOSFET transistor, The gate of the third depletion-mode MOSFET transistor is coupled to the drain of the first depletion-mode MOSFET transistor, a fourth depletion-mode MOSFET transistor coupled between the input voltage and the MOSFET transistor of the output stage, The gate of the fourth depletion-mode MOSFET transistor is coupled to the source of the MOSFET transistor of the output stage.

6. The voltage regulating circuit according to claim 2, characterized in that the gates of the first depletion-mode MOSFET transistor and the MOSFET transistor of the output stage are coupled to ground via compensation capacitors.

7. The voltage regulating circuit of claim 1 , wherein the negative feedback loop comprises a differential amplifier having input terminals coupled to the voltage divider output node and the control node, The gate of the first enhancement mode MOSFET transistor is coupled to the drain of the first enhancement mode MOSFET transistor, The output of the differential amplifier is coupled to the gate of the MOSFET transistor of the output stage.

8. The voltage regulating circuit of claim 1, wherein the first depletion-mode MOSFET transistor and the second depletion-mode MOSFET transistor and the first enhancement-mode MOSFET transistor are gallium nitride (GaN) high electron mobility transistors.

9. The voltage regulating circuit according to claim 1, characterized in that the MOSFET transistor of the output stage is a second depletion-mode MOSFET transistor.

10. A voltage regulating circuit, comprising: a first circuit branch and a second circuit branch connected in parallel and coupled between an input voltage and ground, the first circuit branch including a current generator including a first depletion-mode MOSFET transistor having a gate-source voltage that is a proportional to absolute temperature (PTAT) voltage, the input voltage being a direct current (DC) voltage supply; as well as A voltage reference circuit is configured to supply a reference voltage that is independent of temperature variations, a first depletion-mode MOSFET transistor is coupled between an input voltage and the voltage reference circuit, the voltage reference circuit includes a first enhancement-mode MOSFET transistor, a gate-source voltage of which is a complementary to absolute temperature (CTAT) voltage, The source of the first enhancement mode MOSFET transistor is coupled to ground via a source resistor, a first depletion-mode MOSFET transistor configured to inject a PTAT current in the first branch that determines a PTAT voltage drop across the source resistor, The second circuit branch includes an output stage coupled between an input voltage and an output node at which a regulated voltage is output, The output stage includes a second depletion MOSFET transistor coupled to the gate of the first depletion MOSFET transistor; as well as A resistor divider couples the output node to the gate of the first enhancement mode MOSFET transistor, where a reference voltage is formed as the sum of a PTAT voltage drop across the source resistor and a gate-source voltage of the first enhancement mode MOSFET transistor.

11. The voltage regulating circuit according to claim 10, characterized in that the first depletion MOSFET transistor and the second depletion MOSFET transistor are cascaded with the third depletion MOSFET transistor and the fourth depletion MOSFET transistor, respectively. A third depletion MOSFET transistor is coupled between the input voltage and the first depletion MOSFET transistor, The gate of the third depletion-mode MOSFET transistor is coupled to the drain of the first depletion-mode MOSFET transistor, a fourth depletion-mode MOSFET transistor coupled between the input voltage and the second depletion-mode MOSFET transistor, The gate of the fourth depletion-mode MOSFET transistor is coupled to the source of the MOSFET transistor of the output stage.

12. The voltage regulating circuit according to claim 10, further comprising: A second enhancement MOSFET transistor is cascaded with the first enhancement MOSFET transistor, a gate of the second enhancement MOSFET transistor is coupled to ground through a first resistor of the resistor divider, a gate of the second enhancement MOSFET transistor is coupled to the first resistor through a second resistor of the resistor divider and is coupled to the output node through a third resistor of the resistor divider.

13. The voltage regulating circuit of claim 10, wherein the gates of the first depletion MOSFET transistor and the second depletion MOSFET transistor are coupled to ground via compensation capacitors.

14. The voltage regulating circuit according to claim 10, further comprising: A differential amplifier has an input coupled to the node of the resistor divider and the drain of the first enhancement mode MOSFET transistor, a gate of the first enhancement mode MOSFET transistor coupled to the drain of the first enhancement mode MOSFET transistor, and an output of the differential amplifier coupled to the gate of the second depletion mode MOSFET transistor.

15. The voltage regulating circuit of claim 10, wherein the first depletion MOSFET transistor and the second depletion MOSFET transistor and the first enhancement MOSFET transistor are gallium nitride (GaN) high electron mobility transistors.

16. A voltage regulating circuit, comprising: an input node configured to receive an input voltage; a voltage reference circuit coupled to ground, the voltage reference circuit comprising a first enhancement mode transistor; a current generator circuit coupled between the input node and the voltage reference circuit, the current generator circuit comprising a first depletion-mode transistor; a voltage divider circuit coupled to ground; an output stage coupled between the input node and the voltage divider circuit, the output stage comprising a second depletion-mode transistor; as well as An output node is configured to output a regulated voltage, the output node being located between the voltage divider circuit and the output stage.

17. The voltage regulating circuit according to claim 16, characterized in that the voltage reference circuit and the current generator circuit are connected in parallel with the voltage divider circuit and the output stage.

18. The voltage regulating circuit according to claim 16, further comprising: A capacitor is coupled between the gates of the first depletion-mode transistor and the second depletion-mode transistor.

19. The voltage regulating circuit according to claim 16, further comprising: The protection circuit includes a third depletion-mode transistor coupled between the input node and the first depletion-mode transistor and a fourth depletion-mode transistor coupled between the input node and the second depletion-mode transistor.

20. The voltage regulating circuit according to claim 16, further comprising: An amplifier includes a first input terminal coupled to a node between a voltage reference circuit and a current generator circuit, a second input terminal coupled to a voltage divider circuit, and an output terminal coupled to an output stage.

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