Circuit based on I2C bus

Abstract

The utility model discloses a circuit based on an I2C bus, and the circuit comprises a first interface module which receives first data from external equipment, and a first power supply which reduces the first data and the first power supply at a first voltage level to second data and a second power supply at a second voltage level; or, increasing the third data of the second voltage level to the fourth data of the first voltage level and outputting the fourth data to the external equipment; a second interface module receiving the first clock signal from the master device, and a first power supply reducing the first clock signal and the first power supply at a first voltage level to a second clock signal and a second power supply at a second voltage level; and the data module is coupled to the first interface module and the second interface module, and works based on the second data, the second clock signal or the deformation thereof. On the basis of not changing the device type selection of the original low-voltage I2C slave device interface circuit, the stacked slave device interface circuit is realized by using the low-voltage transistor, so that the low-voltage I2C slave device can be butted with the high-voltage I2C master device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a circuit based on an I2C bus. Background Art

[0002] I2C (Inter-Integrated Circuit) is a serial communication protocol suitable for short-distance data transmission. I2C communication usually uses a multi-master-slave architecture, including a master device and at least one slave device. The master device is mostly an MCU, and the slave device is mostly a controlled chip. The main function of the slave device is implemented by the data module on the controlled chip. According to the level of the master and slave devices in the I2C communication protocol, the operating voltage on the I2C bus can be divided into 5V, 3.3V and 1.8V. According to different operating voltages and system requirements, select the master and slave devices for docking.

[0003] Normally, when the levels between the master and slave devices of the I2C bus match, the master device and the slave device are directly connected. In some engineering applications, based on the I2C bus driver circuit designed with conventional architecture, the slave device controlled chip can only choose 3.3V MOSFET transistors as interface devices due to process limitations, while the master device outputs a high level of 5V. This leads to a mismatch in the levels between the master and slave devices of the I2C bus. The 3.3V interface devices in the slave device interface circuit directly face the 5V voltage, causing these interface devices to be broken down due to overvoltage, thereby affecting the function of the entire chip. In order to meet the strict timing and level matching requirements of I2C communication, the conventional solution is to use a dedicated level conversion chip to convert the levels of the master and slave devices on the I2C bus to ensure the correctness of data transmission, which not only increases the total cost of the system but also increases the complexity of the system. Utility Model Content

[0004] In response to the technical problems existing in the prior art, the present application provides a circuit based on an I2C bus, characterized in that it includes a first interface module, configured to receive first data and a first power supply from an external device through the I2C bus, and configured to reduce the first data and the first power supply having a first voltage level to second data and a second power supply having a second voltage level; or, configured to increase third data having a second voltage level to fourth data having a first voltage level and output it to an external device; a second interface module, configured to receive a first clock signal and the first power supply from a master device through the I2C bus, and configured to reduce the first clock signal and the first power supply having a first voltage level to a second clock signal and a second power supply having a second voltage level; and a data module, coupled to the first interface module and the second interface module, configured to work based on the second data, the second clock signal or a variation thereof.

[0005] In particular, the first interface module includes a first trigger (214), a level converter (216) coupled to the first trigger (214); and a first transistor (213), a first electrode of the first transistor (213) coupled to the first trigger (214), a control electrode of the first transistor (213) coupled to the level converter (216), and a second electrode of the first transistor (213) grounded; a first step-down unit coupled between the first trigger (214) and the first electrode of the first transistor (213), configured to receive first data from the external device and provide second data to the first trigger (214), or to increase third data output by the first transistor (213) to fourth data and output it to the external device; and a second step-down unit coupled to the first trigger (214) and the level converter (216), configured to receive the first power supply and provide the second power supply to the first trigger (214) and the level converter (216); wherein the first voltage level is higher than the second voltage level.

[0006] In particular, the first step-down unit includes a second transistor (2111), a first electrode of the second transistor (2111) is configured to receive the first data, a control electrode of the second transistor (2111) is configured to receive a control voltage, and a second electrode is coupled to the first electrode of the first transistor (213).

[0007] Particularly, the first buck unit further comprises a first current source (2112) coupled between the second electrode of the second transistor (2111) and the ground.

[0008] In particular, the second step-down unit comprises a third transistor (2121), a control electrode of the third transistor (2121) being configured to receive a control voltage, a first electrode of the third transistor (2121) being configured to receive a first power supply, and a second electrode of the third transistor (2121) being coupled to the level converter (216) and providing the second power supply thereto.

[0009] In particular, the second step-down unit further includes a second current source (2122) coupled between the second electrode of the third transistor (2121) and the ground.

[0010] In particular, the second interface module includes a second trigger (324), and a third step-down unit coupled to the second trigger (324), configured to receive the first power supply and provide the second power supply to the second trigger (324); and a fourth step-down unit coupled to the second trigger (324), configured to receive a first clock signal from the external device and provide the second clock signal to the second trigger (324).

[0011] In particular, the third step-down unit includes a fourth transistor (3211), a first electrode of the fourth transistor (3211) is configured to receive a first power supply, a control electrode of the fourth transistor (3211) is configured to receive the control voltage, and a second electrode of the fourth transistor (3211) is coupled to the second trigger (324) and provides a second power supply thereto.

[0012] In particular, the third step-down unit further includes a third current source (3212) coupled between the second electrode of the fourth transistor (3211) and the ground.

[0013] In particular, the fourth step-down unit includes a fifth transistor (3221) and a fourth current source (3222) connected in series with each other, a first electrode of the fifth transistor (3221) is configured to receive the first clock signal, a control electrode of the fifth transistor (3221) is configured to receive the control voltage, a second electrode of the fifth transistor (3221) is coupled between the fourth current source (3222) and the second trigger (324) and provides a second clock signal to the second trigger (324), and a second end of the fourth current source (3222) is grounded.

[0014] In particular, it also includes a power supply module, which is coupled to the control electrodes of the second transistor (2111) and the third transistor (2121), and is coupled to the control electrodes of the fourth transistor (3211) and the fifth transistor (3221), and is configured to provide the control voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0016] Figure 1 FIG. 1 is a schematic diagram of a slave device structure based on an I2C bus according to an embodiment of the present application;

[0017] Figure 2 FIG. 1 is a schematic diagram of a circuit of a slave device interface module based on an I2C bus according to an embodiment of the present application; and

[0018] Figure 3 Shown is a circuit diagram of a slave device interface module based on the I2C bus according to another embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0021] The technologies, methods and devices known to ordinary technicians in the relevant fields may not be discussed in detail, but where appropriate, the technologies, methods and devices should be considered as part of the specification. The connection between the units in the drawings is only for the convenience of explanation, which means that at least the units at both ends of the connection are communicating with each other, and is not intended to limit the unconnected units to be unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only communicate with the signals shown in the figure.

[0022] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor, wherein the control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or the third electrode may be the gate; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or the third electrode may be the base. The transistor may be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0023] In the following text, low-voltage devices or equipment refer to devices or equipment with an operating voltage range of 3.3V and below, and high-voltage devices or equipment refer to devices or equipment with an operating voltage of 5V.

[0024] When the I2C master device is a high-voltage device, the logic level output by the master device is a high level of 5V or a low level of 0V. Correspondingly, the logic levels of the bidirectional data transmission line and clock line of the I2C bus are a high level of 5V or a low level of 0V. In order to achieve the internal device level and process matching of the I2C slave device, when the I2C slave device is a low-voltage device, each device in the I2C slave device interface circuit is also a low-voltage device.

[0025] The present application proposes a circuit based on the I2C bus. On the basis of not changing the original low-voltage I2C slave device interface circuit device selection, a stacked slave device interface circuit is realized by using low-voltage MOSFET transistors, so that the low-voltage I2C slave device can be connected to the high-voltage I2C master device. The slave device based on the I2C bus proposed in the present application meets the requirements of the I2C bus communication timing, and at the same time has the characteristics of high transmission rate of the low-voltage I2C slave device.

[0026] Figure 1 Shown is a schematic diagram of the structure of a slave device based on the I2C bus according to an embodiment of the present application.

[0027] According to one embodiment, the I2C slave device 1 is configured to respond to the master device command, receive the first data from the master device or output the fourth data to the master device through the I2C bus, and receive the first clock signal. The first end of the I2C slave device 1 is coupled to the bidirectional data transmission line (not shown) of the I2C bus, receives the first data or outputs the fourth data. The second end of the I2C slave device 1 is coupled to the clock line (not shown) of the I2C bus, receives the first clock signal. The third end of the I2C slave device 1 receives the high level voltage VDDH.

[0028] According to one embodiment, the I2C slave device 1 includes a power module 10. The power module 10 is configured to provide power to the internal circuit of the I2C slave device 1. A first terminal of the power module 10 is coupled to a third terminal of the I2C slave device 1 to receive a high-level voltage VDDH, a second terminal thereof outputs a low-level voltage VDDL, and a third terminal thereof outputs a control voltage Vb.

[0029] In one embodiment, the high level voltage VDDH is generally a DC voltage of 5 V. The low level voltage VDDL is generally about 1.8 V. When the high level output by the I2C master device is 5 V and the low level is 0 V, the high level of the first data, the fourth data and the first clock signal is 5 V and the low level is 0 V.

[0030] According to one embodiment, the I2C slave device 1 also includes a first interface module 11. The first interface module 11 is configured to receive first data from the master device through the I2C bus and convert it into a signal SDI, or convert the received signal SDO into fourth data during the master-slave device data transmission process based on the I2C bus. The first end of the first interface module 11 is coupled to the first end of the I2C slave device 1 to receive the first data or output the fourth data. The second end of the first interface module 11 outputs the signal SDI, and the third end thereof receives the signal SDO. The fourth end of the first interface module 11 is coupled to the third end of the power module 10 to receive the control voltage Vb. The fifth end of the first interface module 11 is coupled to the second end of the power module 10 to receive the low level voltage VDDL. The sixth end of the first interface module 11 is coupled to the third end of the I2C slave device 1 to receive the high level voltage VDDH.

[0031] In one embodiment, for the low-voltage I2C slave device 1 , the high level of the signal SDI output by the first interface module 11 is usually 1.8V and the low level is usually 0V.

[0032] According to one embodiment, the I2C slave device 1 further includes a second interface module 12. The second interface module 12 is configured to receive a first clock signal and convert the first clock signal into a clock signal SCLK1 when the master and slave devices based on the I2C bus perform data transmission. The first end of the second interface module 12 is coupled to the second end of the I2C slave device 1 to receive the first clock signal. The second end of the second interface module 12 outputs the clock signal SCLK1. The third end of the second interface module 12 is coupled to the third end of the power module 10 to receive the control voltage Vb. The fourth end of the second interface module 12 is coupled to the second end of the power module 10 to receive the low level voltage VDDL. The fifth end of the second interface module 12 is coupled to the third end of the I2C slave device 1 to receive the high level voltage VDDH.

[0033] In one embodiment, for the low voltage I2C slave device 1 , the high level of the clock signal SCLK1 is usually 1.8V and the low level is usually 0V.

[0034] According to one embodiment, the I2C slave device 1 may further include a data module 13. The data module 13 is configured to receive a signal SDI or an output signal SDO output by the first interface module 11, and to receive a clock signal SCLK1 output by the second interface module 12. A first end of the data module 13 is coupled to a second end of the first interface module 11, and receives a signal SDI output by the first interface module 11. A second end of the data module 13 is coupled to a third end of the first interface module 11, and outputs a signal SDO. A third end of the data module 13 is coupled to a second end of the power module 10, and receives a low-level voltage VDDL. A fourth end of the data module 13 is coupled to a second end of the second interface module 12, and acquires the clock signal SCLK1. In one embodiment, the data module 13 may be a digital circuit.

[0035] In one embodiment, for the low voltage I2C slave device 1 , the high level of the signal SDO output by the data module 13 is usually 1.8V and the low level is usually 0V.

[0036] Figure 2 Shown is a circuit diagram of a slave device interface module based on the I2C bus according to an embodiment of the present application.

[0037] According to one embodiment, the first interface module 21 includes a first buck unit 211 and a transistor 213, which are coupled in series between a first end of the first interface module and a ground. The first buck unit 211 is configured to receive a high-level first data and reduce it to a second data, such as 3.3V, acceptable to a low-voltage device; or to increase a third data, such as 3.3V, acceptable to a low-voltage device to a fourth data, such as a high-level data. The first end of the first buck unit 211 is coupled to the first end of the first interface module 21. The second end of the first buck unit 211 is coupled to the fourth end of the first interface module 21 and receives a control voltage Vb. The third end of the first buck unit 211 outputs the second data or receives the third data. The first electrode of the transistor 213 is coupled to the third end of the first buck unit 211 and receives the second data or outputs the third data. The control electrode of the transistor 213 is coupled to the output end of the level converter 216, and the second electrode thereof is grounded.

[0038] According to an embodiment of the present application, the high level of the second data and the third data is usually 3.3V, and the low level is usually 0V.

[0039] In one embodiment, the first step-down unit 211 includes a transistor 2111. A first electrode of the transistor 2111 is coupled to a first terminal of the first step-down unit 211, and receives first data or outputs fourth data. A control electrode of the transistor 2111 is coupled to a second terminal of the first step-down unit 211, and receives a control voltage Vb. A second electrode of the transistor 2111 is coupled to a third terminal of the first step-down unit 211, and outputs second data or receives third data. In one embodiment, the transistor 2111 may be, for example, an N-type transistor.

[0040] According to one embodiment, the first step-down unit 211 further includes a current source 2112. The current source 2112 is coupled between the second electrode of the transistor 2111 and the ground. The current source 2112 is configured to discharge the current flowing through the transistor 2111 through the current source 2112, so that the potential of the second electrode of the transistor 2111 is always lower than the potential of its control electrode, stabilize the voltage between the control electrode of the transistor 2111 and its second electrode, thereby ensuring the stability of the transistor 2111 when it is turned on. The current source 2112 can be a current source device such as a MOSFET.

[0041] According to one embodiment, the first interface module 21 further includes a second step-down unit 212. The second step-down unit 212 is configured to reduce the high-level voltage VDDH to a second power supply, such as 3.3V, which is acceptable to the low-voltage device. The first end of the second step-down unit 212 is coupled to the sixth end of the first interface module 21 to receive the high-level voltage VDDH. The second end of the second step-down unit 212 is coupled to the fourth end of the first interface module 21 to receive the control voltage Vb. The third end of the second step-down unit 212 outputs the second power supply.

[0042] In one embodiment, the second buck unit 212 includes a transistor 2121. A first electrode of the transistor 2121 is coupled to a first terminal of the second buck unit 212, and receives a high level voltage VDDH. A control electrode of the transistor 2121 is coupled to a second terminal of the second buck unit 212, and receives a control voltage Vb. A second electrode of the transistor 2121 is coupled to a third terminal of the second buck unit 212, and outputs a second power supply. In one embodiment, the transistor 2121 may be, for example, an N-type transistor.

[0043] According to one embodiment, the second step-down unit 212 may further include a current source 2122. The current source 2122 is coupled between the second electrode of the transistor 2121 and the ground. The current source 2122 is configured to discharge the current flowing through the transistor 2121 through the current source 2122, so that the potential of the second electrode of the transistor 2121 is always lower than the potential of its control electrode, stabilize the voltage between the control electrode of the transistor 2121 and its second electrode, and ensure the stability of the transistor 2121 when it is turned on. The current source 2122 may be a current source device such as a MOSFET.

[0044] According to one embodiment, the first interface module 21 further includes a level converter 216. A first end of the level converter 216 is coupled to a third end of the second step-down module 212 to receive a second power supply. A second end of the level converter 216 is coupled to a fifth end of the first interface module 21 to receive a low level voltage VDDL. A third end of the level converter 216 is coupled to a third end of the first interface module 21 to receive a signal SDO. The level converter 216 is configured to output corresponding high and low levels based on the received signal SDO. In one embodiment, the level converter 216 may be a low voltage device including 1.8V and 3.6V devices.

[0045] According to one embodiment, the first interface module 21 further includes a trigger 214 and an inverter 215 coupled in series with each other. The first end of the trigger 214 is coupled between the third end of the second buck unit 212 and the level converter 216, and receives the second power supply. The second end of the trigger 214 is coupled between the third end of the first buck unit 211 and the transistor 213, and receives the second data. The output end of the trigger 214 is coupled to the inverter 215. The first end of the inverter 215 is coupled to the fifth end of the first interface module 21, and receives the low level voltage VDDL. The output end of the inverter 215 is coupled to the second end of the first interface module 21. In one embodiment, the trigger 214 and the inverter 215 are both low voltage devices. The trigger 214 can be, for example, a Schmitt trigger that can realize the hysteresis comparison function. The trigger 214 and the inverter 215 are configured to enable the subsequent modules to obtain stable high and low level inputs.

[0046] According to one embodiment, when the I2C slave device 1 receives the first data from the master device, the second step-down unit 212 is used to make point A reach the power supply voltage level at which the level converter 216 and the trigger 214 can work normally. At this time, the signal SDO received by the level converter 216 is at a low level, and the transistor 213 is turned off under the control of the level converter 216. When the level on the bidirectional data transmission line is at a high level (5V), the first step-down unit 211 is used to make the level of point C reach the input voltage level acceptable to the trigger 214 and the transistor 213.

[0047] According to one embodiment, when the I2C slave device 1 outputs data to the master device, the second step-down unit 212 is used to make point A reach the power supply voltage level at which the level converter 216 can work normally. The level converter 216 receives the signal SDO, and the transistor 213 is turned on or off under the control of the level converter 216 and outputs the third data. When the transistor 213 is turned on, the level on the bidirectional data transmission line is a low level of 0V; when the transistor 213 is turned off, the level on the bidirectional data transmission line is a high level of 5V, and the first step-down unit 211 makes the potential of point C within the tolerable range of the transistor 213.

[0048] According to one embodiment, the transistor 2111 in the first step-down unit 211 is selected to meet the breakdown voltage of the transistor 213 and the input voltage level for the normal operation of the flip-flop 214. The transistor 2121 in the second step-down unit 212 is selected to meet the power supply voltage level for the normal operation of the flip-flop 214 and the level converter 216. In one embodiment, the transistors 2111, 2121, and 213 may be low-voltage devices.

[0049] According to one embodiment, the value range of the control voltage Vb is 2.5V < Vb - VGS1 < 3.3V or 2.5V < Vb - VGS2 < 3.3V, where VGS1 is the potential difference between the control electrode and the second electrode of the transistor 2111 in the first step-down unit 211, and VGS2 is the potential difference between the control electrode and the second electrode of the transistor 2121 in the second step-down unit 212. In one embodiment, when VGS1 and VGS2 are 0.7 - 0.8V, the value of the control voltage Vb is between 3.3V and 4.1V. At this time, the first and second step-down units can operate normally, and the flip-flop 214 and the level converter 216 can operate normally.

[0050] Figure 3 Shown is a schematic circuit diagram of a slave device interface module based on the I2C bus according to another embodiment of the present application.

[0051] According to one embodiment, the second interface module 32 includes a third step-down unit 321. The third step-down unit 321 is configured to reduce the high-level voltage VDDH to a second power supply, such as 3.3V, acceptable to low-voltage devices. The first end of the third step-down unit 321 is coupled to the fifth end of the second interface module 32 to receive the high-level voltage VDDH. The second end of the third step-down unit 321 is coupled to the third end of the second interface module 32 to receive the control voltage Vb. The third end of the third step-down unit 321 outputs the second power supply.

[0052] According to one embodiment, the third step-down unit 321 may include a transistor 3211. The first pole of the transistor 3211 is coupled to the first end of the third step-down unit 321 to receive the high-level voltage VDDH. The control electrode of the transistor 3211 is coupled to the second end of the third step-down unit 321 to receive the control voltage Vb. The second pole of the transistor 3211 is coupled to the third end of the third step-down unit 321. The transistor 3211 may be, for example, an N-type transistor.

[0053] According to one embodiment, the third step-down unit 321 may further include a current source 3212. The current source 3212 is coupled between the second electrode of the transistor 3211 and the ground. The current source 3212 is configured to discharge the current flowing through the transistor 3211 through the current source 3212, so that the potential of the second electrode of the transistor 3211 is always lower than the potential of its control electrode, stabilize the voltage between the control electrode of the transistor 3211 and its second electrode, thereby ensuring the stability of the transistor 3211 when it is turned on. The current source 3212 may be a current source device such as a MOSFET.

[0054] According to one embodiment, the second interface module 32 further includes a fourth step-down unit 322. The fourth step-down unit 322 is configured to reduce the high-level first clock signal to a second clock signal of, for example, 3.3V, which can be accepted by the low-voltage device. The first end of the fourth step-down unit 322 is coupled to the first end of the second interface module 32 to receive the first clock signal. The second end of the fourth step-down unit 322 is coupled to the third end of the second interface module 32 to receive the control voltage Vb. The third end of the fourth step-down unit 322 is grounded, and the fourth end thereof outputs the second clock signal.

[0055] According to one embodiment, the fourth buck unit may include a transistor 3221 and a current source 3222 connected in series. The first electrode of the transistor 3221 is coupled to the first end of the fourth buck unit 322 and receives the first clock signal. The control electrode of the transistor 3221 is coupled to the second end of the fourth buck unit 322 and receives the control voltage Vb. The second electrode of the transistor 3221 is coupled to the first end of the current source 3222. The second end of the current source 3222 is grounded. In some embodiments, the current source 3222 may be a current source device including, for example, a MOSFET. The transistor 3221 may be, for example, an N-type transistor.

[0056] In one embodiment, the second interface module 32 further includes a trigger 324 and an inverter 325 connected in series with each other. The first end of the trigger 324 is coupled to the third end of the third buck unit 321 to receive the second power supply. The second end of the trigger 324 is coupled to the fourth end of the fourth buck unit 322 to receive the second clock signal. The first end of the inverter 325 is coupled to the fourth end of the second interface module 32 to receive the low level voltage VDDL. The second end of the inverter 325 is coupled to the output end of the trigger 324. The output end of the inverter 325 is coupled to the second end of the second interface module 32. In one embodiment, the trigger 324 and the inverter 325 are both low voltage devices. The trigger 324 can be, for example, a Schmitt trigger that can realize the hysteresis comparison function. The trigger 324 and the inverter 325 are configured to enable the subsequent modules to obtain stable high and low level inputs.

[0057] In some embodiments, when data is transmitted between I2C master and slave devices, the third buck unit 321 is used to provide a power supply voltage for normal operation for the trigger 324 , and the fourth buck unit 321 is used to provide an input voltage for normal operation for the trigger 324 .

[0058] In one embodiment, when the first clock signal decreases from a high level to a low level, the trigger 324 releases the charge through the current source 3222 in the fourth step-down unit. When the first clock signal increases from a low level to a high level, the input voltage of the trigger 324 increases from a low level accordingly and reaches an input voltage level at which the hysteresis comparison function can be normally implemented.

[0059] According to one embodiment, the selection of transistor 3211 in the third step-down unit 321 and transistor 3222 in the fourth step-down unit 322 is based on the power supply and input voltage level that meet the normal operation of trigger 324. In one embodiment, transistor 3211 and transistor 3221 can be low voltage devices.

[0060] The present application achieves the connection between the low-voltage I2C slave device and the high-voltage I2C master device by simply modifying the low-voltage I2C slave device interface without adding additional hardware devices, thereby avoiding overvoltage damage to the slave device due to level matching problems. At the same time, the I2C slave device can well meet the timing requirements of the I2C bus communication. The I2C slave device proposed in the present application is more convenient and flexible to use, and more economical.

[0061] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A circuit based on I2C bus, characterized in that: include A first interface module is configured to receive first data and a first power source from an external device through an I2C bus, and is configured to reduce the first data and the first power source having a first voltage level to second data and the second power source having a second voltage level; or is configured to increase third data having a second voltage level to fourth data having a first voltage level, and output the data to the external device; A second interface module is configured to receive a first clock signal and the first power supply from a master device through an I2C bus, and is configured to reduce the first clock signal and the first power supply having a first voltage level to a second clock signal and a second power supply having a second voltage level; as well as A data module, coupled to the first interface module and the second interface module, is configured to operate based on the second data, the second clock signal or a variation thereof.

2. The circuit according to claim 1, characterized in that The first interface module includes a first flip-flop (214), a level converter (216) coupled to the first flip-flop (214); as well as a first transistor (213), wherein a first electrode of the first transistor (213) is coupled to the first trigger (214), a control electrode of the first transistor (213) is coupled to the level converter (216), and a second electrode of the first transistor (213) is grounded; A first step-down unit coupled between the first trigger (214) and the first electrode of the first transistor (213), configured to receive first data from the external device and provide second data to the first trigger (214), or to increase third data output by the first transistor (213) to fourth data and output the fourth data to the external device; as well as a second step-down unit coupled to the first flip-flop (214) and the level converter (216), configured to receive the first power supply and provide a second power supply to the first flip-flop (214) and the level converter (216); Wherein, the first voltage level is higher than the second voltage level.

3. The circuit according to claim 2, characterized in that The first step-down unit includes a second transistor (2111), a first electrode of the second transistor (2111) is configured to receive the first data, a control electrode of the second transistor (2111) is configured to receive a control voltage, and a second electrode is coupled to the first electrode of the first transistor (213).

4. The circuit according to claim 3, characterized in that The first step-down unit further includes a first current source (2112) coupled between the second electrode of the second transistor (2111) and ground.

5. The circuit according to claim 3, characterized in that The second step-down unit comprises a third transistor (2121), a control electrode of the third transistor (2121) is configured to receive a control voltage, a first electrode of the third transistor (2121) is configured to receive a first power supply, and a second electrode of the third transistor (2121) is coupled to the level converter (216) and provides the second power supply thereto.

6. The circuit according to claim 5, characterized in that The second step-down unit further includes a second current source (2122) coupled between the second electrode of the third transistor (2121) and the ground.

7. The circuit according to claim 1, characterized in that The second interface module includes a second trigger (324), and a third step-down unit coupled to the second trigger (324), configured to receive the first power supply and provide the second power supply to the second trigger (324); as well as A fourth step-down unit coupled to the second flip-flop (324) is configured to receive a first clock signal from the external device and provide the second clock signal to the second flip-flop (324).

8. The circuit according to claim 7, characterized in that The third step-down unit comprises a fourth transistor (3211), a first electrode of the fourth transistor (3211) being configured to receive a first power supply, a control electrode of the fourth transistor (3211) being configured to receive a control voltage, and a second electrode of the fourth transistor (3211) being coupled to the second trigger (324) and providing a second power supply thereto.

9. The circuit according to claim 7, characterized in that The third step-down unit further includes a third current source (3212) coupled between the second electrode of the fourth transistor (3211) and the ground.

10. The circuit according to claim 8, characterized in that The fourth step-down unit comprises a fifth transistor (3221) and a fourth current source (3222) connected in series with each other, a first electrode of the fifth transistor (3221) being configured to receive the first clock signal, a control electrode of the fifth transistor (3221) being configured to receive the control voltage, a second electrode of the fifth transistor (3221) being coupled between the fourth current source (3222) and the second trigger (324) and providing the second clock signal to the second trigger (324), and a second end of the fourth current source (3222) being grounded.

11. The circuit according to claim 6, characterized in that It also includes a power supply module, which is coupled to the control electrodes of the second transistor (2111) and the third transistor (2121) and is configured to provide the control voltage.

12. The circuit according to claim 10, characterized in that It also includes a power supply module, which is coupled to the control electrodes of the fourth transistor (3211) and the fifth transistor (3221) and is configured to provide the control voltage.

13. The circuit according to claim 11, characterized in that The control voltage is greater than 2.5V and the potential difference between the control electrode and the second electrode of the second transistor (2111), and less than 3.3V and the potential difference between the control electrode and the second electrode of the second transistor (2111); or The control voltage is greater than 2.5V and the sum of the potential difference between the control electrode and the second electrode of the third transistor (2121), and is less than 3.3V and the sum of the potential difference between the control electrode and the second electrode of the third transistor (2121).

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