Mainboard special for testing high-speed hard disk

Abstract

The utility model discloses a special mainboard for testing a high-speed hard disk, which comprises a south bridge chip and a Super I / O chip, the special mainboard for testing the high-speed hard disk is applied to an upper computer, the special mainboard for testing the high-speed hard disk is electrically connected with a hard disk interface card, and the hard disk interface card is used for accessing a tested hard disk. The South Bridge chip is electrically connected with at least one tested hard disk, one end of the Super I / O chip is electrically connected with the South Bridge chip, the other end of the Super I / O chip is electrically connected with the hard disk interface card, and the South Bridge chip is in communication connection with the hard disk interface card through the Super I / O chip. And the requirements of research and development and production links on batch and automation of the detection process are met.

Description

Technical Field

[0001] The utility model relates to the technical field of hard disks, in particular to a special mainboard for high-speed hard disk testing. Background Art

[0002] At present, in the process of R&D and production of high-speed hard disks, a large number of cycles of functional verification are required for newly developed high-speed hard disks, and the functions and performance of newly produced hard disks also require a large number of quality tests. These test items include the stability of the hard disk's PCIe connection identification, reset identification, energy-saving function stability, function and performance stability in high and low temperature environments, function and performance stability under offset voltage, read and write performance, UART function, and SMBus function.

[0003] Since hard disks do not support hot plugging, after a batch of hard disks are tested, the corresponding equipment must be shut down before the tested hard disks can be unplugged, and the next batch of hard disks can only be tested after the next restart. However, the time for shutting down and starting up the host is long, resulting in low efficiency in hard disk testing, which cannot meet the needs of R&D and production links for batch and automated testing processes. Utility Model Content

[0004] The main purpose of the utility model is to provide a special motherboard for high-speed hard disk testing and a hard disk testing system, aiming to improve the efficiency of testing hard disks and meet the needs of R&D and production links for batch and automated testing processes.

[0005] To achieve the above object, the utility model proposes a high-speed hard disk test dedicated motherboard, the high-speed hard disk test dedicated motherboard is applied to a host computer, the high-speed hard disk test dedicated motherboard is electrically connected to a hard disk interface card, the hard disk interface card is used to access the hard disk under test, and is characterized in that the high-speed hard disk test dedicated motherboard includes:

[0006] Southbridge chip;

[0007] A Super I / O chip, wherein an input end of the Super I / O chip is electrically connected to the South Bridge chip, an output end of the Super I / O chip is electrically connected to the hard disk interface card, and the South Bridge chip establishes a communication connection with the hard disk interface card through the Super I / O chip;

[0008] The south bridge chip outputs a first signal to the hard disk interface card via the Super I / O chip, and the hard disk interface card simulates a host shutdown state within a preset time according to the first signal.

[0009] Optionally, the high-speed hard disk test mainboard further includes:

[0010] Multiple serial port chips and multiple first pins, the output end of the Super I / O chip is electrically connected to one end of the multiple serial port chips, and the other ends of the multiple serial port chips are connected to the hard disk interface card one by one through the multiple first pins; wherein the south bridge chip establishes a communication connection with the hard disk interface card via the Super I / O chip, the multiple serial port chips and the multiple first pins in sequence.

[0011] Optionally, the high-speed hard disk test dedicated mainboard also includes:

[0012] A CPU slot, multiple signal transmission interfaces and a signal conversion module, the south bridge chip is electrically connected to one end of one of the signal transmission interfaces, one end of the other signal transmission interfaces are electrically connected to the CPU slot, the other ends of the multiple signal transmission interfaces are electrically connected to one end of the signal conversion module, and the other end of the signal conversion module is electrically connected to the south bridge chip; wherein the other end of the signal transmission interface is electrically connected to at least one hard disk under test through a communication line.

[0013] Optionally, the high-speed hard disk test dedicated mainboard also includes:

[0014] A plurality of signal repeaters, wherein one end of one of the signal repeaters is electrically connected to the south bridge chip, one end of another of the signal repeaters is electrically connected to the CPU slot, and the other ends of the plurality of signal repeaters are electrically connected one by one to the other ends of the plurality of signal transmission interfaces respectively.

[0015] Optionally, the plurality of signal repeaters include a first signal repeater, a second signal repeater, a third signal repeater and a fourth signal repeater, and the plurality of signal transmission interfaces include a first signal transmission interface, a second signal transmission interface, a third signal transmission interface and a fourth signal transmission interface, the first signal transmission interface and the second signal transmission interface are both electrically connected to the CPU slot via the first signal repeater to receive the corresponding signal output by the CPU slot; the first signal transmission interface and the second signal transmission interface are both electrically connected to the CPU slot via the second signal repeater to output the corresponding signal to the CPU slot; the third signal transmission interface and the fourth signal transmission interface are both electrically connected to the CPU slot and the south bridge chip via the third signal repeater to receive the corresponding signal output by the CPU slot or the south bridge chip; the third signal transmission interface and the fourth signal transmission interface are both electrically connected to the CPU slot and the south bridge chip via the fourth signal repeater to output the corresponding signal to the CPU slot or the south bridge chip. Optionally, the high-speed hard disk test dedicated motherboard also includes:

[0016] A second pin, one end of which is electrically connected to the signal conversion module, and the other end of which is used to connect to an external device.

[0017] Optionally, the high-speed hard disk test dedicated mainboard also includes:

[0018] A third pin, one end of the third pin is electrically connected to the output end of the Super I / O chip, and the other end of the third pin is used to connect to a fan.

[0019] Optionally, the high-speed hard disk test dedicated mainboard also includes:

[0020] A fourth pin, one end of the fourth pin is electrically connected to the output end of the Super I / O chip, and the other end of the fourth pin is used to connect to the diagnostic card.

[0021] The technical scheme of the utility model includes a south bridge chip and a Super I / O chip, the south bridge chip establishes a communication connection with a hard disk interface card through the Super I / O chip, the hard disk interface card is used to access the hard disk under test, the south bridge chip outputs a first signal to the hard disk interface card through the Super I / O chip, and the hard disk interface card simulates the state of the host computer shutting down according to the first signal within a preset time. In this way, the user can sequentially connect the hard disk under test to the host computer through the utility model of a high-speed hard disk test dedicated motherboard and the hard disk interface card, when the hard disk under test completes all test processes including energy-saving state judgment and slot voltage control through the host computer, the south bridge chip outputs a first signal to the hard disk interface card through the Super I / O chip, and the hard disk interface card simulates the state of the host computer shutting down according to the first signal within a preset time, that is, at this time, the hard disk interface card releases the system resources occupied by the hard disk under test, and disconnects the electrical connection between the hard disk under test and the host computer, so that the user can replace the hard disk under test without shutting down the host computer. In actual application, the user does not need to switch the host computer on and off before replacing the hard disk under test, which saves a lot of time, thereby improving the efficiency of testing the hard disk. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0023] Figure 1 This is a module schematic diagram of an embodiment of a dedicated motherboard for high-speed hard disk testing of the utility model;

[0024] Figure 2This is a module schematic diagram of another embodiment of a dedicated motherboard for high-speed hard disk testing of the utility model.

[0025] Description of Figure Numbers:

[0026] Label name Label name 10 Hard disk interface card 70 Signal transmission interface 20 Main control chip 80 Signal conversion module 30 Super I / O chip 90 Signal Repeater 40 Serial port chip 100 Second pin 50 First pin 110 The third pin 60 CPU socket 120 Pin 4

[0027] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0029] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0030] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0031] At present, in the process of R&D and production of high-speed hard disks, a large number of cycles of functional verification are required for newly developed high-speed hard disks, and the functions and performance of newly produced hard disks also require a large number of quality tests. These test items include the stability of the hard disk's PCIe connection identification, reset identification, energy-saving function stability, function and performance stability in high and low temperature environments, function and performance stability under offset voltage, read and write performance, UART function, and SMBus function.

[0032] Since hard disks do not support hot plugging, after a batch of hard disks are tested, the corresponding equipment must be shut down before the tested hard disks can be unplugged, and the next batch of hard disks can only be tested after the next restart. However, the time for shutting down and starting up the host is long, resulting in low efficiency in hard disk testing, which cannot meet the needs of R&D and production links for batch and automated testing processes.

[0033] To this end, the utility model proposes a special motherboard for high-speed hard disk testing, which aims to improve the efficiency of testing hard disks and meet the needs of R&D and production links for batch and automated testing processes.

[0034] refer to Figure 1 A high-speed hard disk test dedicated motherboard, the high-speed hard disk test dedicated motherboard is applied to a host computer, the high-speed hard disk test dedicated motherboard is electrically connected to a hard disk interface card 10, the hard disk interface card 10 is used to access the hard disk under test, characterized in that the high-speed hard disk test dedicated motherboard includes:

[0035] South bridge chip 20;

[0036] A Super I / O chip 30, wherein the input end of the Super I / O chip 30 is electrically connected to the South Bridge chip 20, the output end of the Super I / O chip 30 is electrically connected to the hard disk interface card 10, and the South Bridge chip 20 establishes a communication connection with the hard disk interface card 10 through the Super I / O chip 30;

[0037] The south bridge chip 20 outputs a first signal to the hard disk interface card 10 via the Super I / O chip 30 , and the hard disk interface card 10 simulates the shutdown state of the host computer within a preset time according to the first signal.

[0038] In this embodiment, the south bridge chip 20 can be implemented by a main controller, such as an MCU (Microcontroller Unit), a DSP (Digital Signal Process), an FPGA (Field Programmable Gate Array), a SOC (System On Chip), etc.

[0039] In this embodiment, there must be a resource mismatch between the south bridge chip 20 and a large number of low-speed devices such as serial and parallel interfaces, floppy disk drives, keyboards, mice, etc., which need to be converted and managed, and the Super I / O chip can complete this function.

[0040] Specifically, in this embodiment, the south bridge chip 20 establishes a communication connection with the hard disk interface card 10 through the Super I / O chip 30. The hard disk interface card 10 is used to access the hard disk under test. The south bridge chip 20 outputs a first signal to the hard disk interface card 10 via the Super I / O chip 30, wherein the first signal may be one of a control signal, a status signal or a data signal; the hard disk interface card 10 simulates the state of the host shutdown within a preset time according to the first signal. With such arrangement, the user can electrically connect the hard disk under test to the host computer in sequence through the utility model's special motherboard for high-speed hard disk testing and the hard disk interface card 10. After the hard disk under test completes all test processes including energy-saving status judgment and slot voltage control through the host computer, the south bridge chip 20 outputs a first signal to the hard disk interface card 10 through the SuperI / O chip 30. The hard disk interface card 10 simulates the host computer's shutdown state according to the first signal, that is, the hard disk interface card 10 releases the system resources occupied by the south bridge chip 20 and disconnects the electrical connection between the south bridge chip 20 and the host computer, so that the user can replace the hard disk under test without shutting down the host computer. In actual applications, the user does not need to turn on and off the host computer before replacing the hard disk under test, which saves a lot of time, thereby improving the efficiency of testing the hard disk.

[0041] refer to Figure 2 In one embodiment of the present utility model, the high-speed hard disk test dedicated motherboard includes:

[0042] Multiple serial port chips 40 and multiple first pins, the output end of the Super I / O chip 30 is electrically connected to one end of the multiple serial port chips 40, and the other ends of the multiple serial port chips 40 are connected to the hard disk interface card 10 one by one through the multiple first pins; wherein the south bridge chip 20 establishes a communication connection with the hard disk interface card 10 via the Super I / O chip 30, the multiple serial port chips 40 and the multiple first pins 50 in sequence.

[0043] In this embodiment, the serial port chip 40 is an RS232 serial port chip.

[0044] In this embodiment, the Super I / O chip 30 is electrically connected to the South Bridge chip 20 via the eSPI bus. The South Bridge chip 20 outputs the corresponding signal and outputs the TTL serial port signal after conversion by the Super I / O chip 30. The TTL serial port signal is converted into the RS232 signal by the RS232 serial port chip and output to the hard disk interface card 10 via multiple first pins, wherein the RS232 signal is the first signal; the RS232 signal is used to communicate with the MCU on the hard disk interface card 10, and the MCU in the hard disk interface card 10 executes the corresponding program according to the RS232 signal to simulate the state of the upper shutdown. With such a setting, in practical applications, the Super I / O chip 30 and the eSPI bus can provide fast and stable data transmission, thereby ensuring reliable communication between the South Bridge chip 20 and the hard disk interface card 10, while providing a higher data transmission rate and lower signal delay.

[0045] refer to Figure 2 In one embodiment of the present utility model, the high-speed hard disk test dedicated mainboard further includes:

[0046] A CPU slot 60, multiple signal transmission interfaces 70 and a signal conversion module 80, the south bridge chip 20 is electrically connected to one end of one of the signal transmission interfaces 70, one end of the other signal transmission interfaces 70 are electrically connected to the CPU slot 60, the other ends of multiple signal transmission interfaces 70 are electrically connected to one end of the signal conversion module 80, and the other end of the signal conversion module 80 is electrically connected to the south bridge chip 20; wherein the other end of the signal transmission interface 70 is electrically connected to at least one hard disk under test via a communication line.

[0047] In this embodiment, the CPU socket 60 is used to connect the CPU to the motherboard to ensure reliable communication and data transmission between the CPU and other components on the motherboard.

[0048] In this embodiment, the signal transmission interface 70 is a high-speed data transmission interface, which is responsible for supporting data transmission between high-speed devices; for example, in this embodiment, the signal transmission interface adopts the SlimSAS 4i interface, which is an ultra-high-speed transmission interface with the advantages of high bandwidth, high density, flexibility and low power consumption. The CPU can effectively improve the communication efficiency with the hard disk under test through the SlimSAS 4i interface.

[0049] In this embodiment, the signal conversion module 80 adopts a USB to UART chip, and the signal conversion module 80 is electrically connected to the south bridge chip 20 through the USB interface on the south bridge chip 20, and is used to convert the USB signal output by the south bridge chip 20 into a UART signal; by converting the USB signal into a UART signal, the hard disk detection motherboard of the utility model can communicate with more different types of devices or systems. For example, the signal conversion module 80 establishes a communication connection with the UART interface of the hard disk under test, thereby enhancing its versatility and compatibility.

[0050] In this embodiment, the signal conversion module 80 also supports the selection of the UART signal level, and the selection range includes two common levels of 1.8V and 3.3V. For the user, the user can select the 1.8V or 3.3V UART signal according to the level required by the hard disk being tested, thereby improving the compatibility of the utility model dedicated motherboard for high-speed hard disk testing.

[0051] In this embodiment, the host computer can be electrically connected to the SlimSAS 4i interface via a communication line, so that the CPU in the CPU slot 60 and the south bridge chip 20 communicate with the host computer through multiple SlimSAS 4i interfaces.

[0052] In one embodiment of the present utility model, the high-speed hard disk test dedicated mainboard further includes:

[0053] There are multiple signal repeaters 90, one end of one of the signal repeaters 90 is electrically connected to the south bridge chip 20, one end of the other signal repeaters 90 is electrically connected to the CPU slot 60, and the other ends of the multiple signal repeaters 90 are electrically connected one by one to the other ends of the multiple signal transmission interfaces 70 respectively.

[0054] In this embodiment, the function of the signal repeater is to amplify, forward and enhance the signal, and transmit the signal to a distant location, so as to increase the transmission distance and improve the signal quality. The signal repeater 90 adopts a PCIe signal repeater, which is used to clean and filter the signal passing through, eliminate interference and noise, thereby improving the quality and stability of the signal and extending the transmission distance of the signal; and the signal repeater 90 usually supports multiple PCIe channels and can transmit multiple PCIe signals at the same time, thereby providing convenience for applications that require multi-channel transmission. With such a configuration, in actual applications, the existing hard disk test motherboard uses an ordinary signal transmission interface 70, and the ordinary signal output interface has insufficient channels or bandwidth for transmitting signals, while the data transmission rate of PCIe Gen 4 is twice that of PCIe Gen 3. Therefore, the existing hard disk test motherboard only supports the detection of PCIe Gen 3 hard disks at most, but cannot support the detection of PCIe Gen 4 hard disks. The utility model high-speed hard disk test dedicated motherboard combines multiple SlimSAS 4i interfaces and multiple PCIe signal repeaters. The SlimSAS 4i interface has multiple channels for transmitting signals and the channel bandwidth is large. The PCIe signal repeater can improve the quality of the signal. Therefore, the utility model high-speed hard disk test dedicated motherboard can support the transmission rate of signals with higher transmission rates, thereby supporting the detection of PCIe Gen 4 hard disks.

[0055] refer to Figure 2 In one embodiment of the utility model, the plurality of signal repeaters 90 include a first signal repeater, a second signal repeater, a third signal repeater and a fourth signal repeater, and the plurality of signal transmission interfaces 70 include a first signal transmission interface, a second signal transmission interface, a third signal transmission interface and a fourth signal transmission interface, and the first signal transmission interface and the second signal transmission interface are both electrically connected to the CPU slot 60 via the first signal repeater to receive the corresponding signal output by the CPU slot 60; the first signal transmission interface and the second signal transmission interface are both electrically connected to the CPU slot 60 via the second signal repeater The repeater is electrically connected to the CPU slot 60 to output corresponding signals to the CPU slot 60; the third signal transmission interface and the fourth signal transmission interface are electrically connected to the CPU slot 60 and the south bridge chip 20 respectively through the third signal repeater to receive corresponding signals output by the CPU slot 60 or the south bridge chip 20; the third signal transmission interface and the fourth signal transmission interface are electrically connected to the CPU slot 60 and the south bridge chip 20 respectively through the fourth signal repeater to output corresponding signals to the CPU slot 60 or the south bridge chip 20.

[0056] In this embodiment, the first signal transmission interface, the second signal transmission interface, the third signal transmission interface and the fourth signal transmission interface are respectively electrically connected to the first signal repeater, the second signal repeater, the third signal repeater and the fourth signal repeater through four-way PCIe (high-speed serial computer expansion bus standard) to increase the signal transmission rate.

[0057] In this embodiment, one end of the first signal repeater is electrically connected to two TX interfaces of the CPU slot 60, one end of the second signal repeater is electrically connected to two RX interfaces of the CPU slot 60, one end of the third signal repeater is electrically connected to another TX interface of the CPU slot 60 and one TX interface of the south bridge chip 20, and one end of the fourth signal repeater is electrically connected to another RX interface of the CPU slot 60 and one RX interface of the south bridge chip 20; the south bridge chip 20 can transmit corresponding signals to the hard disk under test through the third signal repeater and the third signal transmission interface and the fourth signal transmission interface in sequence, and can also receive signals output by the hard disk under test through the fourth signal repeater and the third signal transmission interface and the fourth signal transmission interface in sequence; the CPU slot 60 can output corresponding signals to the hard disk under test through the first signal repeater and the first signal transmission interface and the second signal output interface in sequence, and can also receive signals output by the hard disk under test through the second signal repeater and the first signal transmission interface and the second signal transmission interface in sequence. With such a configuration, the communication rate between the south bridge chip 20 and the CPU and the hard disk under test can be increased, thereby improving the efficiency of testing the hard disk.

[0058] refer to Figure 2 In one embodiment of the present utility model, the high-speed hard disk test dedicated mainboard further includes:

[0059] A second plug pin 100 , one end of which is electrically connected to the signal conversion module 80 , and the other end of which is used to connect to an external device.

[0060] In this embodiment, the second pin 100 is used to lead out part of the UART signal output by the signal conversion module 80. With this arrangement, the user can electrically connect the second pin 100 through a corresponding device to receive part of the UART signal, so as to monitor the signal output by the south bridge chip 20. With this arrangement, in actual applications, the user can receive and analyze part of the UART signal in real time through a corresponding device electrically connected to the second pin 100, which helps the user to better understand the operating status of the south bridge chip 20, detect potential problems, and optimize and adjust the performance of the system.

[0061] refer to Figure 2 In one embodiment of the present utility model, the high-speed hard disk test dedicated mainboard further includes:

[0062] A third pin 110 , one end of which is electrically connected to the output end of the Super I / O chip 30 , and the other end of which is used to connect to a fan.

[0063] In this embodiment, the third pin 110 is used to electrically connect to at least one cooling fan. The south bridge chip 20 outputs a corresponding control signal through the Super I / O chip 30 to control the start of the cooling fan. The cooling fan is used to dissipate heat from the CPU. Such a setting can ensure that the CPU always runs within an appropriate temperature range to prevent overheating from causing performance degradation or damage.

[0064] refer to Figure 2 In one embodiment of the present utility model, the high-speed hard disk test dedicated mainboard further includes:

[0065] A fourth pin 120 , one end of which is electrically connected to the output end of the Super I / O chip 30 , and the other end of which is used to connect to a diagnostic card.

[0066] In this embodiment, when a high-speed hard disk test dedicated mainboard fails, the diagnostic card can detect the fault by detecting the signal on the fourth pin 120, so as to facilitate users to find the fault in time and make corresponding debugging and maintenance.

[0067] refer to Figure 2 In one embodiment of the present utility model, the high-speed hard disk test dedicated mainboard further includes:

[0068] A USB interface group, wherein the input end of the USB interface group is used to access an external device, and the output end of the USB interface group is electrically connected to the south bridge chip 20.

[0069] In this embodiment, the USB interface group includes two USB3.0 Type A interfaces and two USB2.0 pins to support the access of devices such as keyboards, mice, and U disks to the south bridge chip 20. This configuration provides greater scalability and flexibility for the utility model's high-speed hard disk test dedicated motherboard to meet the needs of different application scenarios.

[0070] In this embodiment, the high-speed hard disk test dedicated mainboard also includes:

[0071] SATA interface and M.2Key M interface, the SATA interface is electrically connected to the south bridge chip 20, the M.2KeyM interface is electrically connected to the south bridge chip 20, and the SATA interface and the M.2Key M interface are used to access storage devices.

[0072] In this embodiment, the SATA interface is used to access a SATA SSD solid-state hard drive, and the M.2Key M interface can communicate with the south bridge chip 20 via a SATA signal or a PCIe 4X signal to support access to a SATA SSD or NVMe SSD. This arrangement enables the utility model to provide a high-speed hard drive testing dedicated motherboard with high flexibility and scalability, and to support multiple types of storage devices to meet different needs.

[0073] In this embodiment, the high-speed hard disk test dedicated mainboard also includes:

[0074] A first RJ45 network port, a second RJ45 network port, a first network card chip and a second network card chip, the output end of the first RJ45 network port and the output end of the second RJ45 network port are electrically connected to the first network card chip and the second network card chip respectively, and the first network card chip and the second network card chip are respectively connected to the south bridge chip 20 through a PCIe 1X signal.

[0075] In this embodiment, the south bridge chip 20 is connected to the external network through the first RJ45 network port and the second RJ45 network port, so that the utility model of a high-speed hard disk test dedicated motherboard can be used online. The first RJ45 network port and the second RJ45 network port are both gigabit network ports, thereby providing high-speed data transmission capabilities to meet the needs of large data volume transmission; the first RJ45 network port and the second RJ45 network port adopt a redundant fault-tolerant design. Even if one of the network ports fails, the other network port can continue to provide network connection, thereby increasing the reliability and stability of the network and reducing the risk of data loss or communication interruption due to network failure.

[0076] In this embodiment, the high-speed hard disk test dedicated mainboard also includes:

[0077] HDMI interface (High Definition Multimedia Interface), the HDMI is electrically connected to the CPU slot 60 via DDI (Digital Display Interface).

[0078] In this embodiment, the HDMI interface is connected to the CPU slot by DDI, so that the transmission and processing of digital signals can be realized, which is convenient for human-computer interaction. The HDMI interface can be used to access display devices such as TVs and projectors.

[0079] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A motherboard dedicated to high-speed hard disk testing, the motherboard dedicated to high-speed hard disk testing is applied to a host computer, the motherboard dedicated to high-speed hard disk testing is electrically connected to a hard disk interface card, the hard disk interface card is used to access the hard disk under test, characterized in that: The high-speed hard disk test dedicated motherboard includes: Southbridge chip; A Super I / O chip, wherein an input end of the Super I / O chip is electrically connected to the South Bridge chip, an output end of the Super I / O chip is electrically connected to the hard disk interface card, and the South Bridge chip establishes a communication connection with the hard disk interface card through the Super I / O chip; The south bridge chip outputs a first signal to the hard disk interface card via the Super I / O chip, and the hard disk interface card simulates a host shutdown state within a preset time according to the first signal.

2. A high-speed hard disk test dedicated motherboard as claimed in claim 1, characterized in that: The high-speed hard disk test dedicated mainboard also includes: Multiple serial port chips and multiple first pins, the output end of the Super I / O chip is electrically connected to one end of the multiple serial port chips, and the other ends of the multiple serial port chips are connected to the hard disk interface card one by one through the multiple first pins; wherein the south bridge chip establishes a communication connection with the hard disk interface card via the Super I / O chip, the multiple serial port chips and the multiple first pins in sequence.

3. A high-speed hard disk test dedicated motherboard as claimed in claim 1, characterized in that: The high-speed hard disk test dedicated mainboard also includes: A CPU slot, multiple signal transmission interfaces and a signal conversion module, the south bridge chip is electrically connected to one of the signal transmission interfaces, the other signal transmission interfaces are electrically connected to the CPU slot, multiple signal transmission interfaces are electrically connected to one end of the signal conversion module, and the signal conversion module is electrically connected to the south bridge chip; wherein the signal transmission interface is electrically connected to at least one hard disk under test via a communication line.

4. A high-speed hard disk test dedicated motherboard as claimed in claim 3, characterized in that: The high-speed hard disk test dedicated mainboard also includes: A plurality of signal repeaters, one of which is electrically connected to the south bridge chip, and the other signal repeaters are electrically connected to the CPU slot, and the plurality of signal repeaters are electrically connected one by one to the plurality of signal transmission interfaces respectively.

5. A high-speed hard disk test dedicated motherboard as claimed in claim 4, characterized in that: The plurality of signal repeaters include a first signal repeater, a second signal repeater, a third signal repeater and a fourth signal repeater, and the plurality of signal transmission interfaces include a first signal transmission interface, a second signal transmission interface, a third signal transmission interface and a fourth signal transmission interface, the first signal transmission interface and the second signal transmission interface are both electrically connected to the CPU slot via the first signal repeater to receive the corresponding signal output by the CPU slot; the first signal transmission interface and the second signal transmission interface are both electrically connected to the CPU slot via the second signal repeater to output the corresponding signal to the CPU slot; the third signal transmission interface and the fourth signal transmission interface are both electrically connected to the CPU slot and the south bridge chip respectively via the third signal repeater to receive the corresponding signal output by the CPU slot or the south bridge chip; the third signal transmission interface and the fourth signal transmission interface are both electrically connected to the CPU slot and the south bridge chip respectively via the fourth signal repeater to output the corresponding signal to the CPU slot or the south bridge chip.

6. A high-speed hard disk test dedicated motherboard as claimed in claim 4, characterized in that: The high-speed hard disk test dedicated mainboard also includes: A second pin, one end of which is electrically connected to the signal conversion module, and the other end of which is used to connect to an external device.

7. A high-speed hard disk test dedicated motherboard as claimed in claim 2, characterized in that: The high-speed hard disk test dedicated mainboard also includes: A third pin, one end of the third pin is electrically connected to the output end of the Super I / O chip, and the other end of the third pin is used to connect to a fan.

8. A high-speed hard disk test dedicated motherboard as claimed in claim 2, characterized in that: The high-speed hard disk test dedicated mainboard also includes: A fourth pin, one end of the fourth pin is electrically connected to the output end of the Super I / O chip, and the other end of the fourth pin is used to connect to the diagnostic card.

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