Half-bridge packaging structure with multiple chips connected in parallel

Abstract

The utility model relates to the technical field of chip packaging, and particularly discloses a multi-chip parallel half-bridge packaging structure, which comprises a DBC (Direct Bonding Copper) substrate, the DBC substrate is provided with a circuit layer, the circuit layer comprises A-area copper foils and B-area copper foils, the A-area copper foils comprise cathode DC-copper foils and lower-bridge AC copper foils positioned on two sides of the cathode DC-copper foils, and the B-area copper foils are positioned on two sides of the cathode DC-copper foils. The B-area copper foil comprises a positive electrode DC + copper foil and upper-bridge AC copper foils located on the two sides of the positive electrode DC + copper foil, the A-area copper foil and the B-area copper foil are symmetrically arranged, the B-area copper foil comprises an upper-bridge grid driving copper foil and an upper-bridge auxiliary source driving copper foil, and the A-area copper foil comprises a lower-bridge grid driving copper foil and a lower-bridge auxiliary source driving copper foil. According to the utility model, the through-current capability of the module can be improved, the parasitic inductance of a main loop is small, the current intensity from current to a chip is improved, and the packaging structure is realizable, low in cost and high in reliability.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a half-bridge packaging structure of multiple chips connected in parallel. Background Art

[0002] Power electronics technology is widely used in aerospace, rail transportation, electric vehicles, power systems and other fields. The whole circuit is widely used in the industrial field because of its simple structure and strong scalability. Existing commercial modules have problems such as large parasitic inductance, uneven current of switch tubes, and low current capacity. Utility Model Content

[0003] In order to solve the above problems, the present invention proposes a half-bridge packaging structure of multiple chips in parallel, which can improve the flow capacity of the module and reduce the parasitic inductance of the main circuit.

[0004] In order to achieve the above purpose, the technical solution adopted by the utility model is:

[0005] A multi-chip parallel half-bridge packaging structure, comprising a DBC substrate, the DBC substrate having a circuit layer, the circuit layer comprising an A-area copper foil and a B-area copper foil, the A-area copper foil comprising a negative electrode DC-copper foil and an AC copper foil of a lower bridge located on both sides of the negative electrode DC-copper foil, the B-area copper foil comprising a positive electrode DC+copper foil and an AC copper foil of an upper bridge located on both sides of the positive electrode DC+copper foil, and the A-area copper foil and the B-area copper foil are symmetrically arranged, the AC copper foil of the lower bridge and the AC copper foil of the upper bridge are respectively connected through copper blocks, the B-area copper foil comprises an upper bridge gate drive copper foil and an upper bridge auxiliary source drive copper foil, and the A-area copper foil comprises a lower bridge gate drive copper foil and a lower bridge auxiliary source drive copper foil;

[0006] The N chips of the first part of the lower bridge are welded on a lower bridge AC copper foil, and the N chips of the second part of the lower bridge are welded on another lower bridge AC copper foil; the N chips of the first part of the upper bridge are welded on the positive DC+ copper foil and close to an upper bridge AC copper foil, and the N chips of the second part of the upper bridge are welded on the positive DC+ copper foil and close to another upper bridge AC copper foil, and N is a positive integer greater than 2;

[0007] The N chips in the first part of the lower bridge are connected in parallel, the N chips in the second part of the lower bridge are connected in parallel, the N chips in the first part of the upper bridge are connected in parallel, and the N chips in the second part of the upper bridge are connected in parallel, and the N chips in the first part of the lower bridge, the N chips in the second part of the lower bridge, the N chips in the first part of the upper bridge and the N chips in the second part of the upper bridge are connected in series to form a half-bridge package;

[0008] The lower bridge gate driving copper foil, the lower bridge auxiliary source copper foil, the upper bridge gate driving copper foil, and the upper bridge auxiliary source copper foil are all connected to the connection terminals through bonding wires.

[0009] Preferably, the N chipsets in the first part of the lower bridge, the N chipsets in the second part of the lower bridge, the N chipsets in the first part of the upper bridge, and the N chipsets in the second part of the upper bridge are all chips arranged in a straight line.

[0010] Preferably, the N chipsets in the first part of the lower bridge and the N chipsets in the second part of the lower bridge are mirrored; the N chipsets in the first part of the upper bridge and the N chipsets in the second part of the upper bridge are mirrored.

[0011] Preferably, the AC copper foils of the two lower bridges on both sides of the negative electrode DC-copper foil have the same width and are symmetrical about the center line of the negative electrode DC-copper foil.

[0012] Preferably, the AC copper foils of the two upper bridges on both sides of the positive electrode DC+ copper foil have the same width and are symmetrical about the center line of the positive electrode DC+ copper foil.

[0013] Preferably, the DBC substrate further has a DC+ terminal and a DC- terminal, the DC+ terminal is electrically connected to the positive DC+ copper foil by ultrasonic welding; the DC- terminal is electrically connected to the negative DC- copper foil by ultrasonic welding.

[0014] Preferably, the copper foil in area A and the chip welded on the copper foil in area A constitute a lower bridge driving circuit, and the copper foil in area B and the chip welded on the copper foil in area B constitute an upper bridge driving circuit;

[0015] The upper bridge drive circuit is symmetrical in both vertical and horizontal directions;

[0016] The lower bridge driving circuit is symmetrical in both vertical and horizontal directions.

[0017] Preferably, the DBC substrate has a lower copper foil, and a circle of small holes is etched on the lower copper foil at a certain distance from the edge.

[0018] Preferably, the outermost edge of the upper copper foil is set to be 1 mm away from the edge of the ceramic substrate.

[0019] Preferably, the outermost edge of the lower copper foil is set to be 1 mm away from the edge of the ceramic substrate.

[0020] The beneficial effects of using the utility model are:

[0021] The multi-chip parallel half-bridge packaging structure can improve the current carrying capacity of the module because multi-chip parallel is used in both the upper bridge and the lower bridge; the copper foil on the front of the DBC substrate is divided into two areas, and the structure is symmetrical, and the parasitic inductance of the main circuit is small; the positive and negative extremely large copper bus terminals can increase the current intensity of the current to the chip; the packaging structure is feasible, low-cost and highly reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The schematic diagram of the structure of the copper-clad ceramic substrate of the half-bridge packaging structure of multiple chips in parallel of the present invention.

[0023] Figure 2 This is a schematic diagram of the front side of the copper-clad ceramic substrate.

[0024] Figure 3 Schematic diagram of the back side of the copper-clad ceramic substrate.

[0025] Figure 4 A side view of a copper-clad ceramic substrate.

[0026] Figure 5 A top view of the chip layout.

[0027] Figure 6 This is a schematic diagram of the chip layout axial direction.

[0028] Figure 7 This is an axonometric diagram of the internal structure.

[0029] Figure 8 A top view of the internal structure.

[0030] Fig. 9 This is a schematic diagram of the main circuit terminal structure.

[0031] Fig.10 This is a schematic diagram of the external structure.

[0032] Fig.11 This is the circuit topology diagram. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the technical solution more clear, the technical solution is further described in detail below in conjunction with specific implementation methods. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the technical solution.

[0034] In order to make the purpose, technical solution and advantages of the technical solution more clear, the technical solution is further described in detail below in conjunction with specific implementation methods. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the technical solution.

[0035] like Figure 1-Figure 4As shown, this embodiment proposes a half-bridge packaging structure of multiple chips in parallel. The structure of the copper-clad ceramic substrate is divided into area A and area B. The copper-clad ceramic substrate is a rectangular plate structure, wherein the middle layer is a ceramic substrate A2, and the two sides are DBC substrates A1. The lower layer of the ceramic substrate A2 is covered with a lower copper foil A3, and dimple holes A4 of the lower copper foil are opened around the lower copper foil A3, and the mid-length direction is the first direction, and the width direction is the second direction. The front side of the copper-clad ceramic substrate has multiple copper foils, and the front copper foil of area A and the front copper foil of area B are arranged in a mirror symmetric manner in the length direction. The negative electrode DC-copper foil A6 is in the middle, occupying the main area, and the AC copper foils A5 and A7 of the lower bridge are arranged on both sides of the negative electrode DC-copper foil A6 in the second direction, and the AC copper foils A5 and A7 of the lower bridge on both sides are arranged on the outside of the second direction with the gate drive copper foil A8 of the lower bridge, the auxiliary source drive copper foil A9 of the lower bridge, and the gate resistor port copper foil A10. The gate resistor port copper foil A10 is another port copper foil where the gate resistor is located, and the solder resist A11 on the upper copper foil is arranged at the corresponding position of the upper copper foil.

[0036] Area B is mirror-symmetrical with area A. Therefore, the setting method of DBC substrate B1, ceramic substrate B2, lower copper foil B3, dimple hole B4 of lower copper foil, AC copper foil B5 and B7 of upper bridge, positive DC+ copper foil B6, gate drive copper foil B8 of upper bridge, auxiliary source drive copper foil B9 of upper bridge, gate resistor port copper foil B10, and solder resist B11 on upper copper foil is consistent with that of area A, and will not be repeated.

[0037] The copper-clad ceramic substrate has a three-layer structure, the upper and lower layers are both conductor layers, and the middle layer is the ceramic substrate A2 and B2. The upper conductor layer is etched to form multiple independent conductor layers, which together with the power chip, bonding wires, terminals, etc. constitute the circuit topology. The ceramic substrates A2 and B2 of the middle layer play an insulating and thermal conductive role. The lower copper foil A3 and B3 are generally connected to the heat sink through a thermal interface material to play a thermal conductive role. In this embodiment, the conductor layer is high-conductivity oxygen-free copper, hereinafter referred to as copper foil, and the surface of the copper foil can be electroplated to prevent oxidation. The ceramic substrate of the middle layer can generally be selected from ceramic materials such as aluminum oxide, aluminum nitride, aluminum oxide doped with zirconium oxide, and silicon nitride. In this embodiment, in order to improve the heat dissipation performance, the ceramic substrate selects aluminum nitride ceramic with high thermal conductivity. A circle of dimple holes A4 and B4 of the lower copper foil are also etched at a certain distance from the edge of the lower copper foil. The etched small holes help release the thermal stress at the edge of the copper foil and improve reliability. The outer edges of the upper and lower copper foils are at a certain distance from the edges of the ceramic substrates A2 and B2. The distance is determined according to the withstand voltage requirements of the module. In this embodiment, the outermost edge of the upper copper foil is set to 1mm from the edges of the ceramic substrates A2 and B2, and the outermost edge of the lower copper foil A3 and B3 is set to 1mm from the edges of the ceramic substrates A2 and B2. The upper copper foil is processed to form a circuit pattern, which plays a role in conducting electricity and transferring heat. In this implementation case, there are solder resist layers A11 and B11 on the upper copper foil, which prevent the solder from overflowing after melting. The topological circuit proposed in this embodiment one can be a power semiconductor chip such as IGBT and MOSFET. The bonding wire material connecting the surface electrodes of the power semiconductor chip is a conductor material such as copper, aluminum, and gold. In this embodiment, the bonding wire selects the aluminum bonding wire with low cost and the most application.

[0038] like Figure 5 and Figure 6 As shown, the first part of the upper bridge has five chips HQ1, HQ2, HQ3, HQ4, and HQ5, and the second part of the upper bridge has five chips HQ6, HQ7, HQ8, HQ9, and HQ10; the first part of the lower bridge has five chips LQ1, LQ2, LQ3, LQ4, and LQ5, and the second part of the lower bridge has five chips LQ6, LQ7, LQ8, LQ9, and LQ10. Each of the above twenty chips has corresponding auxiliary source bonding wires, gate drive bonding wires, power source bonding wires, and driving resistors.

[0039] Taking the chip HQ5 of the first part of the upper bridge as an example, it has a gate drive bonding wire HQ5-1, an auxiliary source bonding wire HQ5-2, a power source bonding wire HQ5-3 and a driving resistor HQ5-4. Taking the chip HQ10 of the second part of the upper bridge as an example, it has a gate drive bonding wire HQ10-1, an auxiliary source bonding wire HQ10-2, a power source bonding wire HQ10-3, and a driving resistor HQ10-4. Taking the chip LQ1 of the first part of the lower bridge as an example, it has a gate drive bonding wire LQ1-1, an auxiliary source bonding wire LQ1-2, a power source bonding wire LQ1-3 and a driving resistor LQ1-4. Taking the chip LQ6 of the second part of the lower bridge as an example, it has a gate drive bonding wire LQ6-1, an auxiliary source bonding wire LQ6-2, a power source bonding wire LQ6-3, and a driving resistor LQ6-4. The bonding wires and driving resistors of the remaining chips are not repeated.

[0040] In order to improve the current carrying capacity, the power source bonding wires HQ5-3, HQ10-3, LQ1-3, and LQ6-3 are generally composed of multiple thick bonding wires in parallel. In this embodiment, the source power bonding wires HQ5-3, HQ10-3, LQ1-3, and LQ6-3 are each composed of 8 15mil diameter aluminum bonding wires in parallel. In actual application, multiple bonding wires can be selected as much as possible according to the size of the bondable area on the chip. In this embodiment, considering the small size of the chip gate, the gate drive bonding wires HQ5-1, HQ10-1, LQ1-1, and LQ6-1 and the auxiliary source bonding wires HQ5-2, HQ10-2, LQ1-2, and LQ6-2 are each composed of 1 5mil diameter aluminum bonding wire.

[0041] like Figure 7 and Figure 8 As shown, the AC copper foils A5 and A7 of the lower bridge and the AC copper foils B5 and B7 of the upper bridge on both sides of the copper bottom plate 1 are connected to each other through two copper blocks 2 and 3. In addition, there are also DC+ terminals 4, DC- terminals 5, AC terminals 6, upper bridge gate drive terminals 7, upper bridge auxiliary source terminals 8, lower bridge gate drive terminals 10, lower bridge auxiliary source terminals 9, thermistor terminals 11 and 12, upper bridge drain terminals 13, connecting bonding wires 14 to 20, 21-1, 21-2 of the terminals, and plastic housing 22. In this embodiment, the connecting bonding wires of the terminals are all 20 mil aluminum bonding wires. In order to improve the corrosion resistance of the terminals in harsh environments such as moisture, mold, and salt spray, the terminal surface selected in this embodiment is nickel-plated, and gold-plated treatment can also be selected.

[0042] Specifically, the drain electrodes of the ten chips HQ1 to HQ10 on the upper bridge are welded to the positive electrode DC+ copper foil B6 through the first solder, and the positive electrode DC+ copper foil B6 is connected to the DC+ terminal 4 through ultrasonic welding technology; in addition, the upper bridge leads out a drain terminal 13 separately through the bonding wire 20, which is convenient for external electrical connection. The gate electrodes of the ten chips HQ1 to HQ10 on the upper bridge are connected to the gate drive copper foil B8 through the gate drive bonding wires HQ1-1 to HQ10-1, and the gate drive copper foil B8 is connected to the copper foil B10 of the upper bridge through the corresponding driving resistors HQ1-4 to HQ10-4, and finally electrically connected to the gate drive terminal 7 through the bonding wire 14. The auxiliary sources of the ten chips HQ1 to HQ10 on the upper bridge are connected to the auxiliary source copper foil B9 through the auxiliary source bonding wires HQ1-2 to HQ10-2, and then electrically connected to the auxiliary source terminal 8 of the upper bridge through the bonding wire 15. The drain electrodes of the ten chips LQ1 to LQ10 of the lower bridge are soldered to the AC copper foils A5 and A7 through the first solder, and then connected to the AC copper foils B5 and B7 through the copper blocks 2 and 3, and finally connected to the AC terminals 6-1 and 6-2 through the bonding wires 27-1 and 27-2; the gate electrodes of the ten chips LQ1 to LQ10 of the lower bridge are connected to the gate drive copper foil A8 through the gate drive bonding wires LQ1-1 to LQ10-1, and the gate drive copper foil A8 is connected to the copper foil A10 of the lower bridge through the corresponding driving resistors LQ1-4 to LQ10-4, and finally electrically connected to the lower bridge gate terminal 10 through the bonding wire 17. The auxiliary sources of the ten chips LQ1 to LQ10 of the lower bridge are connected to the auxiliary source copper foil A9 through the auxiliary source bonding wires LQ1-2 to LQ10-2, and then electrically connected to the lower bridge auxiliary source terminal 9 through the bonding wire 16.

[0043] like Fig. 9 As shown, the AC terminal is electrically connected to the AC copper foils B5 and B7 through bonding wires 21-1 and 21-2. The DC+ terminal 4 and the DC- terminal 5 are electrically connected to the DC+ and DC- copper foils B6 and A6 through ultrasonic welding technology. In addition, the ultrasonic welding terminal increases the flow intensity of the current, thereby increasing the current intensity flowing to the chip, improving the performance of the chip, and increasing the service life of the terminal.

[0044] like Fig.10 As shown, the external structure is composed of a plastic shell 22, a copper base plate 1, wiring terminals 4-13, a connecting nut 23 and a plastic cover plate 24.

[0045] The circuit topology diagram of the packaged chip formed by the half-bridge package structure of multiple chips in parallel is as follows: Fig.11As shown, it is mainly composed of an upper bridge gate drive terminal 7, a lower bridge gate drive terminal 10, an upper bridge auxiliary source terminal 8, a lower bridge auxiliary source terminal 9, a DC+ terminal 4, an AC terminal 6 (6-1, 6-2), a DC- terminal 5 and thermistor terminals 11, 12 and electrical connections therebetween.

[0046] In this embodiment, the power chips HQ1~HQ5 of the first part of the upper bridge and the power chips HQ6~HQ10 of the second part of the upper bridge are symmetrical in the vertical direction, the power chips LQ1~LQ5 of the first part of the lower bridge and the power chips LQ6~LQ10 of the second part of the lower bridge are symmetrical in the vertical direction, and the upper bridge chips HQ1~HQ10 and the lower bridge chips LQ1~LQ10 are at the same left-right distance from the central axis. The DC+ terminal 4, DC- terminal 5 and AC terminals 6-1 and 6-2 are symmetrical in the left-right direction, and the DC+ terminal 4 and DC- terminal 5 are symmetrical in the vertical direction. In addition, the upper bridge drive circuit and the lower bridge drive circuit are also symmetrical in the vertical direction and the left-right direction. In this way, the symmetry of the power commutation circuit and the drive circuit of the parallel chip is achieved, and the current sharing characteristics of the parallel chip are improved.

[0047] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, many changes can be made in the specific implementation methods and application scopes based on the ideas of the present technical content. As long as these changes do not deviate from the concept of the present invention, they all fall within the scope of protection of this patent.

Claims

1. A multi-chip parallel half-bridge packaging structure, characterized in that: The DBC substrate comprises a circuit layer, wherein the circuit layer comprises an A-area copper foil and a B-area copper foil, wherein the A-area copper foil comprises a negative electrode DC-copper foil and an AC copper foil of a lower bridge located on both sides of the negative electrode DC-copper foil, wherein the B-area copper foil comprises a positive electrode DC+copper foil and an AC copper foil of an upper bridge located on both sides of the positive electrode DC+copper foil, wherein the A-area copper foil and the B-area copper foil are symmetrically arranged, wherein the AC copper foil of the lower bridge and the AC copper foil of the upper bridge are respectively connected through copper blocks, wherein the B-area copper foil comprises an upper bridge gate driving copper foil and an upper bridge auxiliary source driving copper foil, and wherein the A-area copper foil comprises a lower bridge gate driving copper foil and a lower bridge auxiliary source driving copper foil; The N chips of the first part of the lower bridge are welded on a lower bridge AC copper foil, and the N chips of the second part of the lower bridge are welded on another lower bridge AC copper foil; the N chips of the first part of the upper bridge are welded on the negative DC-copper foil and close to an upper bridge AC copper foil, and the N chips of the second part of the upper bridge are welded on the negative DC-copper foil and close to another lower bridge AC copper foil, and N is a positive integer greater than 2; The N chips in the first part of the lower bridge are connected in parallel, the N chips in the second part of the lower bridge are connected in parallel, the N chips in the first part of the upper bridge are connected in parallel, and the N chips in the second part of the upper bridge are connected in parallel, and the N chips in the first part of the lower bridge, the N chips in the second part of the lower bridge, the N chips in the first part of the upper bridge and the N chips in the second part of the upper bridge are connected in series to form a half-bridge package; The lower bridge gate drive copper foil, the lower bridge auxiliary source copper foil, the upper bridge gate drive, and the upper bridge auxiliary source are all connected to the connection terminals through bonding wires.

2. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The N chipsets in the first part of the lower bridge, the N chipsets in the second part of the lower bridge, the N chipsets in the first part of the upper bridge and the N chipsets in the second part of the upper bridge are all chips arranged in a straight line.

3. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The N chipsets in the first part of the lower bridge and the N chipsets in the second part of the lower bridge are mirrored; the N chipsets in the first part of the upper bridge and the N chipsets in the second part of the upper bridge are mirrored.

4. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The AC copper foils of the two lower bridges on both sides of the negative electrode DC-copper foil have the same width and are symmetrical about the center line of the negative electrode DC-copper foil.

5. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The AC copper foils of the two upper bridges on both sides of the positive electrode DC+ copper foil have the same width and are symmetrical about the center line of the positive electrode DC+ copper foil.

6. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The DBC substrate also has a DC+ terminal and a DC- terminal. The DC+ terminal is electrically connected to the positive DC+ copper foil through an ultrasonic welding process; the DC- terminal is electrically connected to the negative DC- copper foil through an ultrasonic welding technology.

7. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The copper foil in area A and the chip welded on the copper foil in area A constitute a lower bridge driving circuit, and the copper foil in area B and the chip welded on the copper foil in area B constitute an upper bridge driving circuit; The upper bridge drive circuit is symmetrical in both vertical and horizontal directions; The lower bridge driving circuit is symmetrical in both vertical and horizontal directions.

8. The multi-chip parallel half-bridge packaging structure according to claim 1, characterized in that: The DBC substrate has a lower copper foil, and a circle of small holes is etched on the lower copper foil at a certain distance from the edge.

9. The multi-chip parallel half-bridge packaging structure according to claim 8, characterized in that: The distance between the outermost edge of the lower copper foil and the edge of the ceramic substrate is set to 1 mm.

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