Multi-link aggregation communication system

Abstract

The utility model relates to the technical field of communication, and particularly discloses a multilink aggregation communication system, which comprises a power management module, a communication USB (universal serial bus) interface switching circuit, a network connector circuit, an Ethernet switch circuit, an SIM (subscriber identity module) card interface circuit, a wireless aggregation access circuit and a main control circuit. The SIM card interface circuit and the network connector circuit are electrically connected with the wireless aggregation access circuit and the Ethernet switch circuit respectively, and the power management module, the communication USB interface switching circuit, the Ethernet switch circuit and the wireless aggregation access circuit are electrically connected with the main control circuit. According to the utility model, multi-link aggregation, a bidirectional tunnel link, a multi-card adaptive network and double-video coding transmission are integrated, and all network links are integrated into a high-broadband-value channel, so that a stable 100M bandwidth is provided for users to carry out audio and video stream transmission, file transceiving and internet access; and stable transmission of video images in a severe environment with unstable wireless networks is ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of communications, and in particular to a multi-link aggregation communication system. Background Art

[0002] With the rapid improvement of economic development and the continuous progress of society, communication has become an indispensable part of modern social life. The application of large-capacity optical fiber communication technology, wireless cellular mobile communication technology, digital multimedia communication technology, etc. has made communication more convenient and faster, and also stimulated the further development of communication demand. However, the existing mobile Internet communication still has the following problems: 1. When the 5G network bandwidth changes sharply or multiple 5G networks switch to each other, the video transmission is unstable, causing freezes and interruptions; 2. Media live broadcast, video surveillance and video conferencing can only be transmitted with low image quality due to insufficient network bandwidth; 3. A single communication network is easily interfered and information is easily intercepted; 4. The network is unstable due to the signal quality of the base station and the congestion of the base station. Utility Model Content

[0003] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, a multi-link aggregation communication system is provided, which adopts multi-link aggregation, bidirectional tunnel link, multi-card adaptive network, and dual video encoding transmission as an integrated design, and completely solves the problem of video transmission freeze when the bandwidth of multiple 5G networks changes sharply or multiple 5G networks switch to each other in the video encoder + multi-card aggregation routing solution, integrates all network links into a high-bandwidth value channel, and provides users with a stable 100-megabit bandwidth for audio and video streaming, file sending and receiving, and Internet access.

[0004] In order to solve the above technical problems, the technical solution of the utility model is:

[0005] A multi-link aggregation communication system includes a power management module, a communication USB interface switching circuit, a network connector circuit, an Ethernet switch circuit, a SIM card interface circuit, a wireless aggregation access circuit and a main control circuit, wherein the SIM card interface circuit and the network connector circuit are electrically connected to the wireless aggregation access circuit and the Ethernet switch circuit respectively, and the power management module, the communication USB interface switching circuit, the Ethernet switch circuit and the wireless aggregation access circuit are all electrically connected to the main control circuit.

[0006] Preferably, the main control circuit includes a USB-to-serial port control chip U24, a MODEL interface circuit and a power supply pin circuit, and the MODEL interface circuit and the power supply pin circuit are both connected to the USB-to-serial port control chip U24.

[0007] Preferably, the power management module includes a power controller U15, a voltage regulator U1, a power management chip U2, a power management chip U3 and a voltage regulator U4, and the power controller U15, the voltage regulator U1, the power management chip U2, the power management chip U3 and the voltage regulator U4 are all connected to the USB to serial port control chip U24.

[0008] Preferably, the communication USB interface switching circuit includes a HUB communication main control chip U6, a USB interface P25 and a USB interface P1, the USB interface P25 and the USB interface P1 are both connected to the HUB communication main control chip U6, and the HUB communication main control chip U6 is connected to the USB to serial port control chip U24.

[0009] Preferably, the network connector circuit includes network connector P8, network connector P9, network connector P10, and network connector P19; the Ethernet switch circuit includes switch chip U8A, switch chip U8B, network transformer T1, network transformer T2, and network transformer T4; the USB to serial port control chip U24, network connector P8, network connector P9, network connector P10, network connector P19, switch chip U8B, network transformer T1, network transformer T2, and network transformer T4 are all connected to the switch chip U8A.

[0010] Preferably, the SIM card interface circuit includes a SIM card interface U12, a SIM card interface U13 and a SIM card interface U14, the wireless aggregation access circuit includes a wireless network card interface U9, a wireless network card interface U10 and a wireless network card interface U11, the wireless network card interface U9, the wireless network card interface U10 and the wireless network card interface U11 are respectively connected to the SIM card interface U14, the SIM card interface U12 and the SIM card interface U13, and the SIM card interface U14, the SIM card interface U12 and the SIM card interface U13 are all connected to the USB to serial port control chip U24.

[0011] By adopting the above technical scheme, the multi-link aggregation communication system provided by the utility model has the following beneficial effects: the SIM card interface circuit and the network connector circuit in the multi-link aggregation communication system are electrically connected to the wireless aggregation access circuit and the Ethernet switch circuit respectively, the power management module, the communication USB interface switching circuit, the Ethernet switch circuit and the wireless aggregation access circuit are all electrically connected to the main control circuit, and the multi-link aggregation, bidirectional tunnel link, multi-card adaptive network and dual video encoding transmission are integrated into one design, which completely solves the problem of video transmission freeze when the bandwidth of multiple 5G networks changes sharply or multiple 5G networks switch to each other in the video encoder + multi-card aggregation routing scheme, and integrates all network links into a high-bandwidth value channel through the cooperation of the wireless aggregation access circuit and the Ethernet switch circuit, providing users with a stable 100-megabit bandwidth for audio and video streaming, file sending and receiving, and Internet access, ensuring the stable transmission of video images in harsh environments where multiple wireless networks are unstable, and meeting the needs of various high-bandwidth audio and video and data services through network aggregation, bandwidth superposition, parallel transmission intelligent fusion, and operation and maintenance fusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural block diagram of the utility model;

[0013] Figure 2 It is the circuit principle diagram of the main control circuit in the utility model;

[0014] Figure 3 This is a circuit diagram of the power management module in the utility model;

[0015] Figure 4 This is a circuit schematic diagram of the communication USB interface switching circuit in the utility model;

[0016] Figure 5 It is a circuit schematic diagram of the network connector circuit and the Ethernet switch circuit in the utility model;

[0017] Figure 6 This is a circuit schematic diagram of the SIM card interface circuit and the wireless aggregation access circuit in the utility model;

[0018] In the figure, 1-power management module, 2-communication USB interface switching circuit, 3-network connector circuit, 4-Ethernet switch circuit, 5-SIM card interface circuit, 6-wireless aggregation access circuit, 7-main control circuit. DETAILED DESCRIPTION

[0019] The specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the description of these implementation methods is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in each implementation method of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0020] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0022] like Figure 1-6As shown, the multi-link aggregation communication system includes a power management module 1, a communication USB interface switching circuit 2, a network connector circuit 3, an Ethernet switch circuit 4, a SIM card interface circuit 5, a wireless aggregation access circuit 6 and a main control circuit 7. The SIM card interface circuit 5 and the network connector circuit 3 are electrically connected to the wireless aggregation access circuit 6 and the Ethernet switch circuit 4 respectively, and the power management module 1, the communication USB interface switching circuit 2, the Ethernet switch circuit 4 and the wireless aggregation access circuit 6 are all electrically connected to the main control circuit 7. It can be understood that in actual application, the power management module 1, the communication USB interface switching circuit 2, the network connector circuit 3, the Ethernet switch circuit 4, the SIM card interface circuit 5, the wireless aggregation access circuit 6 and the main control circuit 7 can be integrated on the PCB circuit board and installed in the vehicle-mounted multi-card aggregation routing terminal for use. It adopts multi-link aggregation technology, bidirectional tunnel link technology and multi-card adaptive network Hanhgk-H.265+ / H.264+ dual video encoding transmission as one multi-functional application terminal, and uses multi-link aggregation technology to integrate all network links into a high-bandwidth value channel to provide users with a stable 100M bandwidth. Wide bandwidth for audio and video streaming, file sending and receiving, and Internet access. For video transmission, it does not simply use a video encoder to connect a multi-card aggregation router through a network port. It adopts Hanhgk-H.265+ / H.264+ dual video encoding, FEC forward error correction technology, unique UDP fast redundant fault tolerance, PID-controlled adaptive video bandwidth encoding, adaptive network transmission, and multiple technologies to ensure the stable transmission of video images in harsh environments where multiple wireless networks are unstable; it completely solves the problem of video transmission freeze when the video encoder + multi-card aggregation routing solution changes sharply in the bandwidth of multiple 5G networks or multiple 5G networks switch to each other.

[0023] Specifically, the main control circuit 7 includes a USB to serial port control chip U24, a MODEL interface circuit and a power supply pin circuit, and the MODEL interface circuit and the power supply pin circuit are connected to the USB to serial port control chip U24. It can be understood that the USB to serial port control chip U24 adopts an LQFP64 chip, and the MODEL interface circuit and the power supply pin circuit include resistors R60 (12K), R62 (10K), R64 (10K), R66 (10K), R108 (10K), R110 (1M), R64 (10K), R130 (10K), R124 (51K), R125 (100K), R130 (10K), capacitor C11 (1 8pF), C41(18pF), C147(2.2uF), C42(0.1uF), C43(0.1uF), C130(0.1uF), C139(10uF), C131(0.1uF ), C132(0.1uF), C140(10uF), C133(0.1uF), C136(0.1uF), C137(0.1uF), C138(0.1uF), C144(0.1u F), C146 (10uF), C141 (10nF), C142 (10nF), C143 (10nF), C145 (10nF), inductors L5, L6, L7 chip inductors BLM21P221SN, crystal oscillator X2 (12MHz), JM20339 are 64 interface pins; one end of MODE0 is connected to the 59th pin of JM20339, and the other end is connected to the R62 (10K) resistor, and the other end of the R62 (10K) resistor is connected Common ground, one end of MODE1 is connected to the 55th pin of JM20339, and the other end is connected to the R64 (10K) resistor, and the other end of the R62 (10K) resistor is connected to the common ground. One end of MODE2 is connected to the 4th pin of JM20339, and the other end is connected to the R66 (10K) resistor, and the other end of the R62 (10K) resistor is connected to the common ground; VDD_3V3_A is connected to the 8th, 15th, and 56th pins of JM20339, and the other end is connected to the inductor L5 and L6, and then connected to the inductor L5 SATA_A3.3V is connected to the 24th pin of JM20339. Inductor L5SATA_U3.3V is connected to the 21st pin of JM20339; SATA_A1.8V is connected to the 14th pin of JM20339 at one end and the inductor L7 at the other end, and then the inductor L7 is connected to SATA_D1.8V and the 58th pin of JM20339; VBUS is connected to the 13th pin of JM20339 at one end and the other end is connected in parallel to the resistors R124 (51K) and R125 (100K).Then the other end of R124 (51K) is connected to the VDD_5V circuit, and the other end of R125 (100K) is connected to the common ground. One end of REXT is connected to the 26-pin of JM20339 and the other end is connected to the resistor R60 (12K) 1%, and the other end of R60 is connected to the common ground. SATA RST# is connected to the 12th pin of JM20339 at one end and the other end is connected in parallel to the resistor R13010K and the inductor C147 (2.2uF), SATA_D1.8V is connected to the 14th pin of JM20339 at one end and the other end is connected in parallel to the inductor C138 (0.1uF) and the inductor C137 (0.1uF), SATA_U3.3V is connected to the 21st pin of JM20339 at one end and the other end is connected to the inductor C138 (0.1uF), SATA_A3.3V is connected to the 24th pin of JM20339 at one end and the other end is connected to the inductor C133 (0.1uF), SATA_A1.8V is connected to the JM203 The other end of the 29th pin of 39 is connected in parallel to inductors C131 (0.1uF), C132 (0.1uF), and C140 (10uF), one end of SATA_RX_P is connected to the 27th pin of JM20339 and the other end is connected to inductor C141 (10nF), one end of SATA_RX_N is connected to the 28th pin of JM20339 and the other end is connected to inductor C142 (10nF), one end of SATA_TX_N is connected to the 32nd pin of JM20339 and the other end is connected to inductor C143 (10nF), one end of SATA_TX_P is connected to the 31st pin of JM20339 and the other end is connected to inductor C146 (10nF). The main control circuit 7 adopts full-protocol, full-link ultra-large bandwidth superposition of six links, rather than one-to-many backup, and supports the simultaneous insertion of 4G / 5G cards from different operators (China Telecom, China Mobile, China Unicom), superimposed bandwidth, and guarantees the stability and reliability of high-speed transmission in weak network environments, which can optimally reduce delays and protect data.

[0024] Specifically, the power management module 1 includes a power controller U15, a voltage regulator U1, a power management chip U2, a power management chip U3 and a voltage regulator U4. The power controller U15, the voltage regulator U1, the power management chip U2, the power management chip U3 and the voltage regulator U4 are all connected to the USB to serial port control chip U24. The power management module 1 specifically includes: SMDJ13CA diode, capacitor C28, capacitor C102, capacitor C177, capacitor C178, capacitor C179, voltage regulator circuit LM78L05-SOT89 / NC, power controller MAX6303CSA / NC, capacitor C70, resistor R16 (10K), resistor R71 (2.2K), resistor R6 (2.2K), resistor R16 (10K), resistor R26 (120K), resistor R2 (47K), transistor MMBT3904, capacitor C2, capacitor C3, capacitor C116, capacitor C7, resistor R19 (10K), step-down power supply MP1495, capacitor C1, capacitor C5, capacitor C6, resistor R3 (40.2K), resistor R18 (13K), capacitor C9, capacitor C10, capacitor C176, resistor R8 (10K), resistor R9 (10K), resistor R10 (40.2K), resistor R11 (7.5K), capacitor C12, capacitor C13, capacitor C14, capacitor C16, capacitor C17, capacitor C21, capacitor C19, capacitor C20, power management chip MP2225GJ, resistor R7 (10K), resistor R12 (22K), inductor L3 (4.7uH), resistor R15 (40.2K), resistor R1 7 (7.5K), capacitor C180, capacitor C19, resistor R100 (100K), resistor R126 (100K), and low input voltage TPS22929ADBV / NC for controlling startup. One end of the capacitor C28 is connected to the third pin of the voltage stabilizing circuit chip U5, and the other end is grounded. One end of the capacitor C102 is connected to the third pin of the transmitting chip U5, and the other end is connected to the second pin. One end of the capacitor C177 is connected to the first pin of U5 and the first pin of U15, and the other end is grounded. One end of the capacitor C178 is connected to the third pin of U15, and the other end is grounded. One end of the capacitor C179 is connected to the fourth pin of U15, and the other end is grounded. One end of the capacitor C70 is connected to the first pin of U15 8 pin, the other end is grounded. One end of resistor R16 (10K) is connected to the 6th pin of U15, and the other end is connected to capacitor C70. One end of resistor R71 (2.2K) is connected to V14, and the other end is connected to IO45; one end of resistor R6 (2.2K) is connected to V13, and the other end is connected to IO47; one end of resistor R26 (120K) is connected to the first pin of V13, and the other end is grounded; one end of resistor R2 (47K) is connected to the third pin of V13, and the other end is connected to the positive voltage; one end of capacitors C2, C3, C116 is connected to the second pin of U1, and the other end is grounded; one end of capacitor C7 is connected to the seventh pin of U1, and the other end is grounded; one end of resistor R4 is connected to the seventh pin of U1, and the other end is connected to the first pin of U1.One end of resistor R19 is connected to the first pin of U1, and the other end is connected to ground. One end of capacitor C1 is connected to the 10nR1 resistor in parallel and then connected to the 5th pin of U1, and the other end is connected to the 3rd pin of U1. Capacitors C5 and C6 are connected to the L1 inductor in parallel and then connected to the 3rd pin of U1, and the other end is connected to ground. Resistor R3 (40.2K) is connected to the L1 inductor in parallel and then connected to the 3rd pin of U1, and the other end is connected to the positive power supply. One end of resistor R18 (13K) is connected to the 8th pin of U1, and the other end is connected to the power supply ground. One end of capacitors C9, C10, and C176 is connected to the second pin of U2, and the other end is connected to ground; one end of resistor R8 (10K) is connected to the 5th pin of U1, and the other end is connected to the 10R resistor. Resistor R9 (10K) One end of resistor R10 (40.2K) is connected to U1 pin 8, and the other end is connected to the positive power supply. One end of resistor R11 (7.5K) is connected to U1 pin 8, and the other end is connected to the power supply ground. Capacitors C12 and C13 are connected to U1 pin 5 and the other end is connected to the power supply ground. One end of capacitor C14 is connected to U1 pin 7, and the other end is connected to the power supply ground. One end of capacitor C16 and capacitor C17 is connected to U3 pin 2 and connected to the 12V positive power supply, and the other end is connected to the power supply ground. One end of resistor R12 (22R) is connected to U3 pin 6, and the other end is connected to IO44 output. Resistor R7 (10K) is connected to U3 pin 6 and the other end is connected to IO44 output. One end of capacitor C21 is connected to U3 pin 7, and the other end is connected to U3 pin 1. Capacitors C19 and C20 are connected to inductor L3 and finally to U3 pin 5, and the other end is connected to the power supply ground. One end of resistor R13 is connected to U3 pin 5, and the other end is connected to 10R resistor. One end of resistor R15 (40.2K) is connected to U3 pin 8, and the other end is connected to 3.8V power supply positive. One end of resistor R17 (7.5K) is connected to U3 pin 8, and the other end is connected to power supply ground. One end of capacitors C23, C24, and C120 is connected to U4 pin 2 and 12V power supply positive, and the other end is connected to ground; one end of capacitor C27 is connected to U 4's 7th pin, and the other end is grounded; one end of resistor R93 is connected to U4's 7th pin, and the other end is connected to U4's 1st pin and grounded; one end of resistor R146 is connected to U4's 1st pin, and the other end is grounded; one end of capacitor C22 is connected to U4's 3rd pin, and the other end is connected to 10nR20 and then connected to U4's 5th pin; one end of resistor R33 is connected to U4's 8th pin, and the other end is connected to a 33K resistor in series; one end of resistor R21 (40.2K) is connected to 5V positive, and the other end is connected to a 33K resistor in series; one end of resistor R134 (7.68K) is connected to the power supply ground, and the other end is connected to a 33K resistor in series; one end of capacitors C25 and C26 is connected to the inductor L4 and finally connected to U4's 5th pin, and the other end is connected to the power supply ground. It can be understood that the power controller U15 uses the MAX6303CSA / NC chip, the above-mentioned power management chip uses the MP2225GJ chip, and the above-mentioned voltage regulators all use the MP1495 voltage regulator. The power management module 1 is used to provide suitable working power for the entire communication system.

[0025] Specifically, the communication USB interface switching circuit 2 includes a HUB communication main control chip U6, a USB interface P25 and a USB interface P1, the USB interface P25 and the USB interface P1 are both connected to the HUB communication main control chip U6, and the HUB communication main control chip U6 is connected to the USB to serial port control chip U24. The communication USB interface switching circuit 2 specifically includes: capacitors C30 (0.1uF), C31 (0.1uF), C32 (0.1uF), C33 (0.1uF), C34 (0.1uF), C35 (0.1uF), CA1 (0.1uF), CA2 (0.1uF), CA3 (0.1uF), CA4 (10uF), C29 (1uF), resistors R30 (10K), R34 (0R), R35 (0R), R36 (0R), R37 (0R), R38 (0R K), R39(0R), R40(2.7K), R14(0R), R52(0R), R148(0R), R149(0R), R80(0R), R98 (0R), R42(0R), R43(0R), R44(0R), R45(0R), R46(0R), R47(0R), R48(0R), R49(0R K), R39 (0R) diodes V16, V17, V18, one end of capacitor C30 (0.1uF) is connected to HUB1_1V8, the other end is connected to the common ground, one end of C31 (0.1uF) is connected to HUB1_1V8, the other end is connected to the common ground, one end of C32 (0.1uF) is connected to HUB1_1V8, the other end is connected to the common ground, one end of C33 (0.1uF) is connected to HUB1_1V8, the other end is connected to the common ground, one end of C36 (10uF) is connected to HUB1_1V8, the other end is connected to the common ground, one end of C29 (1uF) is connected to U6FE2.1-48LAFP 40 pins, the other end is connected to the common ground, one end of CA1 (0.1uF) is connected to the positive pole of VCC_3.3V, the other end is connected to the common ground, one end of CA2 (0.1uF) is connected to the positive pole of VCC_3.3V, the other end is connected to the common ground, one end of CA3 (0.1uF) is connected to the positive pole of VCC_3.3V, the other end is connected to the common ground, one end of CA4 (10uF) is connected to the positive pole of VCC_3.3V, the other end is connected to the common ground; one end of resistor R30 (10K) is connected to U6FE2.1-48LAFP 40 pins, the other end is connected to the positive pole of VCC_3.3V, one end of resistor R34 (0R) is connected to U6FE2.1-48LAFP 35 pins DP6, the other end is connected to the differential signal, one end of resistor R35 (0R) is connected to U6FE2.1-48LAFP 34 pin DM6, the other end is connected to the differential signal, one end of resistor R36 (0R) is connected to U6FE2.1-48LAFP 33 pin DP5, the other end is connected to the differential signal, one end of resistor R37 (0R) is connected to U6FE2.1-48LAFP 32 pin DM5, the other end is connected to the differential signal, resistor R38 (0R) one end is connected to U6FE2.1-48LAFP 30 pin DPU, the other end is connected to the differential signal, resistor R39 (0R) one end is connected to U6FE2.1-48LAFP 29 pin DMU, ​​the other end is connected to the differential signal, resistor R40 (0R) one end is connected to U6FE2.1-48LAFP 27 pin REXT, the other end is connected to the differential signal, resistor R44 (0R) one end is connected to U6FE2.1-48LAFP 13 pin DM3 the other end is connected to the differential signal, R45 (0R) one end is connected to U6FE2.1-48LAFP 14 pin DP3 the other end is connected to the differential signal, R46 (0R) one end is connected to U6FE2.1-48LAFP 16-pin DM2, the other end is connected to the differential signal, R47 (0R) one end is connected to U6FE2.1-48LAFP 17-pin DP2, the other end is connected to the differential signal, R48 (0R) one end is connected to U6FE2.1-48LAFP 18-pin DM1, the other end is connected to the differential signal, R49 (0R) one end is connected to U6FE2.1-48LAFP 19-pin DP1, the other end is connected to the differential signal, R42 (0R) one end is connected to U6FE2.1-48LAFP 11-pin DM4, the other end is connected to the differential signal, R43 (0R) one end is connected to U6FE2.1-48LAFP The 11-pin DP4 is connected to the differential signal at one end, the 3-pin of P1 is connected to the other end, the R52(0R) is connected to the 4-pin of P1 is connected to the other end, the R148(0R) is connected to the 6-pin of P1 is connected to the other end, the R149(0R) is connected to the 7-pin of P1 is connected to the other end, the R80(0R) is connected to the 9-pin of P1 is connected to the other end, the R98(0R) is connected to the 10-pin of P1 is connected to the other end, the diode V16 is connected to the 4-pin of P25 is connected to the 3-pin of P25 at one end, the V17 is connected to the 4-pin of P25 is connected to the 2-pin of P25 at one end, and the V18 is connected to the 1-pin of P25 is connected to the common ground at the other end. Understandably, the HUB communication main control chip U6 adopts FE2.1-48LQFP chip, and the communication USB interface switching circuit adopts responsive data transmission and link usage, millisecond-level response, and distributes data packets according to link quality to optimize transmission quality assurance. Network grabbing function, stable transmission link guarantee, super base station connection, no fear of dense personnel and mobile phone equipment, stable data transmission and reception; full operator network standard support, reducing mobile network signal blind spots, ensuring network connection quality, and meeting network needs in various scenarios. .

[0026] Specifically, the network connector circuit 3 includes a network connector P8, a network connector P9, a network connector P10, and a network connector P19; the Ethernet switch circuit 4 includes a switch chip U8A, a switch chip U8B, a network transformer T1, a network transformer T2, and a network transformer T4; the USB to serial port control chip U24, the network connector P8, the network connector P9, the network connector P10, the network connector P19, the switch chip U8B, the network transformer T1, the network transformer T2, and the network transformer T4 are all connected to the switch chip U8A. Specifically include: capacitors C44 (0.1uF), C45 (0.1uF), C46 (0.1uF), C47 (0.1uF), C48 (0.1uF), C49 (0.1uF), C50 (0.1uF), C51 (0.1uF), C52 (0.1uF), C40 (22uF), C53 (0.1uF), C54 (0.1uF), C55 (0.1uF), C56 (0.1uF), C57 (0.1uF), C58 (0.1uF), C59 (22uF), C37 (22u F, C60(0.1uF), C61(0.1uF), C62(0.1uF), C63(1NF), C64(1000P / 2KV), C68(1NF), C69(1000P / 2KV), C72(1NF), C73(1000 P / 2KV), C65(27PF), C66(27PF), C67(0.1uF), C74(0.047uF), C75(0.1uF), C76(0.047uF), C77(0.047uF), C78(0.1uF), C 79 (0.047uF), resistors R76 (1K), R79 (1K), R74 (1K), R41 (1K), R54 (33R), R57 (33R), R59 (33R), R55 (2.49K), R56 (470K), R31 (0R), R78 (0R), R92 (0R), R135 (0R), R61 (49.9R), R63 (49.9R), R65 (49.9R), R67 (49.9R), inductor Y1 (25M), one end of capacitor C44 (0.1uF) is connected to VC C1.0V, the other end is connected to the common ground, one end of C45 (0.1uF) is connected to VCC1.0V, the other end is connected to the common ground, one end of C46 (0.1uF) is connected to VCC1.0V, the other end is connected to the common ground, one end of C47 (0.1uF) is connected to VCC1.0V, the other end is connected to the common ground, one end of C48 (0.1uF) is connected to VCC1.0V, the other end is connected to the common ground, one end of C49 (0.1uF) is connected to VCC1.0V, the other end is connected to the common ground, one end of C50 (0.1uF) is connected to VCC1.0V, the other end is connected to the common ground, C51 (0.1uF) is connected to VCC1.0V and the other end is connected to the common ground. One end of C52 (0.1uF) is connected to VCC1.0V and the other end is connected to the common ground. One end of C40 (0.1uF) is connected to VCC1.0V and the other end is connected to the common ground. One end of C53 (0.1uF) is connected to VCC3.3V and the other end is connected to the common ground. One end of C54 (0.1uF) is connected to VCC3.3V and the other end is connected to the common ground. One end of C55 (0.1uF) is connected to VCC3.3V and the other end is connected to the common ground. One end of C56 (0.1uF) is connected to VCC3.3V and the other end is connected to the common ground. One end of C57 (0.1uF) is connected to VCC3.3V and the other end is connected to the common ground. Connect to VCC3.3V, and the other end to the common ground. One end of C58 (0.1uF) is connected to VCC3.3V, and the other end is connected to the common ground. One end of C59 (0.1uF) is connected to VCC3.3V, and the other end is connected to the common ground. One end of C37 (22uF) is connected to VCC3.3V, and the other end is connected to the common ground. One end of C60 (0.1uF) is connected to VCC3.3V, and the other end is connected to the common ground. One end of C61 (0.1uF) is connected to VCC3.3V, and the other end is connected to the common ground. One end of C62 (0.1uF) is connected to VCC3.3V, and the other end is connected to the common ground. One end of C63 (1NF) is connected to 1 of T113F_39. 0 and 15 terminals, and the other terminal is connected to the common ground. One terminal of C64 (1000P) is connected to the 2 and 8 terminals of T113F_39, and the other terminal is connected to the common ground. One terminal of C68 (1NF) is connected to the 10 and 15 terminals of T213F_39, and the other terminal is connected to the common ground. One terminal of C69 (1000P) is connected to the 2 and 8 terminals of T213F_39, and the other terminal is connected to the common ground. One terminal of C72 (1NF) is connected to the 10 and 15 terminals of T413F_39, and the other terminal is connected to the common ground. One terminal of C73 (1000P) is connected to the 2 and 8 terminals of T413F_39, and the other terminal is connected to the common ground. One terminal of C75 (0.1uF) is connected to the resistor R 61 (49.9R) and resistor R63 (49.9R), the other end is connected to the common ground, one end of C78 (0.1uF) is connected to resistor R65 (49.9R) and resistor R67 (49.9R), the other end is connected to the common ground, one end of C74 (0.047uF) is connected to resistor R61 (49.9R), the other end is connected to the differential signal, one end of C76 (0.047uF) is connected to resistor R63 (49.9R), the other end is connected to the differential signal, one end of C77 (0.047uF) is connected to resistor R65 (49.9R), the other end is connected to the differential signal, one end of C79 (0.047uF) is connected to resistor R67 (49.9R).9R), the other end is connected to the differential signal, resistors: resistor R76 (1K) one end is connected to the 9th pin of P9406549-1, and the other end is connected to PORTD_LED, resistor R79 (1K) one end is connected to the 9th pin of P10406549-1, and the other end is connected to PORTD_LED, resistor R74 (1K) one end is connected to the 9th pin of P8406549-1, and the other end is connected to PORTD_LED, resistor R41 (1K) one end is connected to the 11th pin of P8406549-1, and the other end is connected to VDD_3V3, resistor R54 (33R) one end is connected to the 2nd and 7th pins of T113F_39, and the other end is connected to C64 (1 000P), one end of resistor R57 (33R) is connected to the 2nd and 7th pins of T213F_39, and the other end is connected to C69 (1000P), one end of resistor R59 (33R) is connected to the 2nd and 7th pins of T413F_39, and the other end is connected to C73 (1000P), one end of resistor R55 (2.49K) is connected to the 42nd pin of U&ARTL8305NB, and the other end is connected to the common ground, one end of resistor R56 (470K) is connected to the 27th pin of U&ARTL8305NB and C67 (0.1uF), and the other end is connected to VDD_3V3, one end of resistor R31 (0R) is connected to PORTA_T_N, and the other end is connected to USB ETH SWTX_N, one end of resistor R78 (0R) is connected to PORTA_T_P, the other end is connected to USB ETH SW TX_P, one end of resistor R78 (0R) is connected to PORTA_R_P, the other end is connected to USB ETH SW RX_P, one end of resistor R135 (0R) is connected to PORTA_R_N, the other end is connected to USB ETHSW TX_N, one end of resistor R61 (49.9R) is connected to C75 (0.1uF) and the other end is connected to C74 (0.047uF), one end of resistor R63 (49.9R) is connected to C75 (0.1uF) and the other end is connected to C76 (0.047uF), one end of resistor R65 (49.9R) is connected to C78 (0.1uF) and the other end is connected to C77 (0.047uF), one end of resistor R67 (49.9R) is connected to C78 (0.1uF) and the other end is connected to C79 (0.047uF), one end of inductor Y1 (25M) is connected to the 39th pin of U&ARTL8305NB and C65 (27PF), and the other end is connected to the 40th pin of U&ARTL8305NB and C66 (27PF). It is understandable that the above network connector uses 406549-1 connector, and the switch chip uses RTL8305NB chip. IP packet forwarding capability>50Kpps (maximum packet), converted into network bandwidth (bps)>500Mb; the actual measurement of aggregated routing bandwidth superposition efficiency: after integrating 2 general working conditions 5G channels, the maximum bandwidth can exceed 150Mb, which can support 2-channel 4K / 16-channel 1080P high-definition video backhaul. .

[0027] Specifically, the SIM card interface circuit 5 includes a SIM card interface U12, a SIM card interface U13 and a SIM card interface U14, the wireless aggregation access circuit 6 includes a wireless network card interface U9, a wireless network card interface U10 and a wireless network card interface U11, the wireless network card interface U9, the wireless network card interface U10 and the wireless network card interface U11 are respectively connected to the SIM card interface U14, the SIM card interface U12 and the SIM card interface U13, and the SIM card interface U14, the SIM card interface U12 and the SIM card interface U13 are all connected to the USB to serial port control chip U24. Specifically include: capacitors C80 (33pF), C81 (33pF), C82 (33pF), C83 (33pF), C84 (33pF), C85 (33pF), C86 (33pF), C87 (33pF), C88 (33pF), C89 (0.1uF), C90 (0.1uF), C91 (0.1uF), C92 (0.1uF), C93 (0.1uF), C96 (220uF), C97 (220uF), C94 (220uF), C95 (0.1uF), C98 (220uF), C99 (220uF), C100 (220uF), resistors R68 (10K), R69 (10K), R70 (10K), one end of capacitor C80 (33pF) is connected to the 10th corner V_CARD1_DATA of U9MINIPCI_e, and the other end is connected to the common ground, one end of C83 (33pF) is connected to the 12th corner V_CARD1_CLK of U9MINIPCI_e, and the other end is connected to the common ground, one end of C86 (33pF) is connected to U9 MINIPCI_e 14th corner V_CARD1_RST, the other end is connected to the common ground, C89 (33pF) is connected to U9 MINIPCI_e 8th corner V_CARD1, the other end is connected to the common ground, C81 (33pF) is connected to U10 MINIPCI_e 10th corner V_CARD2_DATA, the other end is connected to the common ground, C84 (33pF) is connected to U10 MINIPCI_e 12th corner V_CARD2_CLK, the other end is connected to the common ground, C87 (33pF) is connected to U10 MINIPCI_e 14th corner V_CARD2_RST, the other end is connected to the common ground, C90 (0.1uF) one end is connected to U10MINIPCI_e 8th corner V_CARD2_RST, the other end is connected to the common ground, C82 (33pF) one end is connected to U11MINIPCI_e 10th corner V_CARD3_DATA, the other end is connected to the common ground, C85 (33pF) one end is connected to U11 MINIPCI_e 12th corner V_CARD3_CLK, the other end is connected to the common ground, C88 (33pF) one end is connected to U11 MINIPCI_e 14th corner V_CARD3_RST, the other end is connected to the common ground, C92 (0.1uF) one end connected to VCC_3.8V_M1, the other end connected to the common ground, C93 (0.1uF) one end connected to VCC_3.8V_M1, the other end connected to the common ground, C96 (220uF) one end connected to VCC_3.8V_M1, the other end connected to the common ground, C97 (220uF) one end connected to VCC_3.8V_M1, the other end connected to the common ground, C94 (220uF) one end connected to VCC_3.8V_M2, the other end connected to the common ground. Connect to the common ground, one end of C95 (0.1uF) is connected to VCC_3.8V_M2, and the other end is connected to the common ground, one end of C98 (220uF) is connected to VCC_3.8V_M2, and the other end is connected to the common ground, one end of C99 (220uF) is connected to VCC_3.8V_M3, and the other end is connected to the common ground, one end of C100 (220uF) is connected to VCC_3.8V_M3, and the other end is connected to the common ground, one end of resistor R68 (10K) is connected to U9 The 8th corner V_CARD1 of MINIPCI_e and the other end of the 1st corner V_CARD1 of U14MICRO_SIM are connected to U9 MINIPCI_e 10th corner CARD1 DATA and U14MICRO_SIM 7th corner CARD1 DATA, one end of resistor R69 (10K) is connected to U10 MINIPCI_e 8th corner V_CARD2 and the other end of the 1st corner V_CARD1 of U12MICRO_SIM is connected to U10 MINIPCI_e 10th corner CARD2 DATA and U14 MICRO_SIM 7th corner CARD2 DATA, one end of resistor R70 (10K) is connected to U11 MINIPCI_e 8th corner V_CARD3 and U13 MICRO_SIM 1st corner V_CARD1, the other end is connected to U11MINIPCI_e 10th corner CARD3 DATA and U13 MICRO_SIM 7th corner CARD3 DATA. It can be understood that the SIM card interface circuit 5 and the wireless aggregation access circuit 6 can aggregate the 4G / 5G multi-links of multiple operators in the global network, realize the bandwidth aggregation of the ground network and the satellite Internet, realize the aggregation of the public network and the private network, bandwidth superposition, and parallel transmission, so that the network transmission bandwidth is larger, the stability is stronger, the delay is lower, and the security is higher; the coverage is wide, and VPN, APN private network, secure transmission, and public network dedicated characteristics are supported; the computing network fusion platform realizes "network computing" through AI technology, which can realize intelligent routing selection and intelligent management, effectively reduce costs, and improve network capabilities and network quality; the network does its best to meet the solution of reliable communication in weak network environments and transmit high-definition video; it can integrate LTE private network / 5G (700Mhz and 3.3GHz private network access), etc., and effectively supplement the private network blind area. .

[0028] It can be understood that the utility model has a reasonable design and unique structure. It can aggregate 5G / 4G / 3G and optical fiber, support mesh network, wired network, satellite communication link multi-communication link aggregation communication device, and the multi-link aggregation communication device will enhance the overall communication network bandwidth after aggregation to meet the needs of various high-bandwidth audio and video and data services; use NFV 2.0, AI, big data, security and other technical means to comprehensively improve the perception and affinity of the underlying network for computing services / applications, through network aggregation, bandwidth superposition, parallel transmission intelligent fusion, operation and maintenance fusion, and service fusion; support maximum uplink 250Mbps, downlink 350Mbps; modular design, support up to 6 5G / 4G in global frequency bands, 3 satellite access; 2 fiber optic module slots, 1 wired network access aggregation; support video input at the same time, support AHD and HDMI and SDI input combination selection, can be established with the military network through a dedicated line L2TP tunnel (Layer 2 Tunnel Protocol), 108060P supports 25 frames / s actual real-time transmission, and the transmission delay is within 1-2s. 2. Information encryption uses network tunnel, 128-bit encryption algorithm, firewall / VPN, encryption lock, permission management, real-time clock and other technologies to ensure that the monitoring system and video data are not used or damaged beyond the authority; 3. The authentication platform server supports local / cloud deployment, multi-card aggregation authentication service platform; one-click authentication configuration tool, easy management, simple and convenient, full web visualization interface, reduce the difficulty of operation and maintenance personnel management, and reduce enterprise network costs. Realize data flow warning, bandwidth warning, operation status and fault warning, making management easier and more convenient.

[0029] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A multi-link aggregation communication system, characterized in that: It includes a power management module, a communication USB interface switching circuit, a network connector circuit, an Ethernet switch circuit, a SIM card interface circuit, a wireless aggregation access circuit and a main control circuit. The SIM card interface circuit and the network connector circuit are electrically connected to the wireless aggregation access circuit and the Ethernet switch circuit respectively, and the power management module, the communication USB interface switching circuit, the Ethernet switch circuit and the wireless aggregation access circuit are all electrically connected to the main control circuit.

2. The multi-link aggregation communication system according to claim 1, characterized in that: The main control circuit includes a USB-to-serial port control chip U24, a MODEL interface circuit and a power supply pin circuit, and the MODEL interface circuit and the power supply pin circuit are both connected to the USB-to-serial port control chip U24.

3. The multi-link aggregation communication system according to claim 2, characterized in that: The power management module includes a power controller U15, a voltage stabilizer U1, a power management chip U2, a power management chip U3 and a voltage stabilizer U4. The power controller U15, the voltage stabilizer U1, the power management chip U2, the power management chip U3 and the voltage stabilizer U4 are all connected to the USB to serial port control chip U24.

4. The multi-link aggregation communication system according to claim 2, characterized in that: The communication USB interface switching circuit includes a HUB communication main control chip U6, a USB interface P25 and a USB interface P1. The USB interface P25 and the USB interface P1 are both connected to the HUB communication main control chip U6. The HUB communication main control chip U6 is connected to the USB to serial port control chip U24.

5. The multi-link aggregation communication system according to claim 2, characterized in that: The network connector circuit includes network connector P8, network connector P9, network connector P10, and network connector P19; the Ethernet switch circuit includes switch chip U8A, switch chip U8B, network transformer T1, network transformer T2, and network transformer T4; the USB to serial port control chip U24, network connector P8, network connector P9, network connector P10, network connector P19, switch chip U8B, network transformer T1, network transformer T2, and network transformer T4 are all connected to the switch chip U8A.

6. The multi-link aggregation communication system according to claim 2, characterized in that: The SIM card interface circuit includes a SIM card interface U12, a SIM card interface U13 and a SIM card interface U14; the wireless aggregation access circuit includes a wireless network card interface U9, a wireless network card interface U10 and a wireless network card interface U11; the wireless network card interface U9, the wireless network card interface U10 and the wireless network card interface U11 are respectively connected to the SIM card interface U14, the SIM card interface U12 and the SIM card interface U13; the SIM card interface U14, the SIM card interface U12 and the SIM card interface U13 are all connected to the USB to serial port control chip U24.

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