Low-power-consumption voltage sampling circuit and integrated chip applying same

Abstract

The utility model provides a low-power-consumption voltage sampling circuit and an integrated chip applying the low-power-consumption voltage sampling circuit, the low-power-consumption voltage sampling circuit comprises a first sampling circuit, an active clamping circuit, a second sampling circuit and a holding capacitor, and the active clamping circuit is connected between the first sampling circuit and the second sampling circuit; the input end of the first sampling circuit is connected with a sampling port, and the output end of the second sampling circuit is connected with the holding capacitor; wherein in the voltage sampling period, when a sampling control signal is valid, the first sampling circuit and the second sampling circuit are conducted, and the active clamping circuit is not enabled; when the sampling control signal is invalid, the first sampling circuit and the second sampling circuit are switched off, and the active clamping circuit is enabled; wherein the sampling port is a pin port of the integrated circuit, a first resistor is connected between the sampling port and the reference ground, and a given first current flows through the sampling resistor. According to the invention, the influence of noise on the chip pin voltage sampling precision can be effectively avoided.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a low-power voltage sampling circuit and an integrated chip using the same. Background Art

[0002] In integrated circuits, it is often necessary to obtain some voltage signals for applications such as dimming and overvoltage protection. Generally, a small current is set in the integrated circuit. The small current flows through a large resistor set outside the integrated circuit to generate a voltage signal. The large resistor is connected to the sampling port on the integrated circuit. The voltage signal on the sampling port is obtained through the voltage sampling circuit. Traditional voltage sampling circuits such as Figure 1 As shown, the voltage sampling circuit includes a clamp circuit and a sample-and-hold circuit, which samples the input signal VIN (the voltage of the sampling port on the integrated circuit) to obtain the output voltage VO. After the input signal VIN passes through the clamp circuit, the output voltage range is approximately: -V THN ~VDD+V THP , where V THN , V THP They are the GATE threshold voltages of NMOS and PMOS respectively, and VDD is the preset voltage.

[0003] The clamping circuit includes switch tubes M2, P2 and a current limiting resistor R. The switch tubes M2 and P2 are connected, and the current limiting resistor R is connected to the common connection end of the switch tubes M2 and P2. The output voltage VM of the clamping circuit is sampled after passing through the sampling and holding circuit to obtain the output voltage VO. The sampling and holding circuit includes sampling switches M1, P1 and a holding capacitor Co. The sampling switches M1 and P1 are connected in parallel, and the holding capacitor Co is connected to the output end of the voltage sampling circuit. When the control signal C is at a high level (C is not at a low level), the sampling switches M1 and P1 are turned on, and VIN charges and discharges the holding capacitor Co through the current limiting resistor R, so that VO=VIN; when the control signal C is at a low level (C is not at a high level), the sampling switches M1 and P1 are turned off, and the output voltage VO is maintained. The high and low levels of the control signal C are generally VDD and 0, respectively;

[0004] During the period when the output voltage VO is maintained, the input signal VIN is easily disturbed by the noise caused by the parasitic capacitance in the line. THP When VIN<-VTHN, the switch tubes M2 and M1 are both turned on, and VO is discharged, that is, the sampling and holding voltage VO is also interfered by noise.

[0005] If the output voltage VM of the clamp circuit is clamped at a fixed value during the non-sampling period, it may affect the actual value of the input signal VIN, and further affect the output voltage VO after sampling and holding. If the absolute value of the clamped voltage of the clamp circuit is reduced, an additional voltage clamp circuit is required, increasing the system cost. Summary of the invention

[0006] The purpose of the present invention is to provide a voltage sampling circuit with a simple system and low power consumption and an integrated chip using the same. The voltage sampling circuit avoids the noise of the input signal affecting the sampling accuracy, the sampled signal has a strong anti-noise ability, and the system is simple.

[0007] The present invention also provides a voltage sampling circuit, comprising a first sampling circuit, an active clamping circuit, a second sampling circuit and a holding capacitor.

[0008] The active clamping circuit is connected between the first sampling circuit and the second sampling circuit;

[0009] The input end of the first sampling circuit is connected to the sampling port, the output end of the second sampling circuit is connected to the holding capacitor, and the voltage on the holding capacitor is the voltage sampling signal output by the voltage sampling circuit;

[0010] Wherein, during the voltage sampling period, when the sampling control signal is valid, the first sampling circuit and the second sampling circuit are turned on, and the active clamping circuit is not enabled; when the sampling control signal is invalid, the first sampling circuit and the second sampling circuit are turned off, and the active clamping circuit is enabled;

[0011] The sampling port is a pin port of an integrated circuit. A first resistor is connected between the sampling port and a reference ground, and a given first current flows through the sampling resistor.

[0012] Optionally, a current limiting resistor is further included, and the current limiting resistor is connected between the sampling port and the clamping circuit.

[0013] Optionally, when the sampling control signal is invalid, the active clamping circuit clamps the voltage at the connection end of the first sampling circuit and the second sampling circuit, so that the on-voltage of the second sampling circuit does not reach the threshold voltage and the second sampling circuit remains turned off.

[0014] Optionally, the first sampling circuit includes a first sampling switch tube, and the second sampling circuit includes a second sampling switch tube.

[0015] Optionally, the first sampling switch tube and the second sampling switch tube respectively include one or more switch tubes; if the first sampling switch tube and the second sampling switch tube respectively include multiple switch tubes, the multiple switch tubes are connected in parallel.

[0016] Optionally, the first sampling switch tube and the second sampling switch tube respectively include two switch tubes, and the two switch tubes are connected in parallel.

[0017] Optionally, the two switch tubes include a PMOS tube and an NMOS tube.

[0018] Optionally, the two switch tubes include two NMOS tubes.

[0019] Optionally, the active clamping circuit includes a clamping switch tube, a first end of the clamping switch tube is connected to a connection end of the first sampling circuit and the second sampling circuit, and a second end of the clamping switch tube receives a clamping voltage.

[0020] Optionally, the clamping voltage is greater than or equal to a zero reference voltage and less than or equal to a preset voltage value.

[0021] Optionally, when the clamping voltage is equal to the zero reference voltage, the clamping switch tube is set to a PMOS tube;

[0022] When the clamping voltage is equal to a preset voltage value, the clamping switch tube is set to be an NMOS tube.

[0023] The present invention also provides an integrated chip, comprising a sampling port, and also comprising any one of the above-mentioned low-power voltage sampling circuits, wherein the voltage sampling circuit is used to sample the signal of the sampling port on the integrated chip.

[0024] Compared with the prior art, the present invention has the following advantages: it provides a voltage sampling circuit with a simple system and low power consumption, wherein the voltage sampling circuit obtains a sampling voltage by sampling by connecting a first voltage sampling circuit, a clamping circuit and a second sampling circuit, and during a non-sampling period, the clamping circuit can ensure that the second sampling circuit is not mistakenly turned on, thereby avoiding the influence of parasitic capacitance on the PIN pin voltage, avoiding the influence of the noise of the input signal on the sampling accuracy of the PIN pin voltage, and the obtained sampling voltage has a strong noise resistance capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of a voltage sampling circuit in the prior art;

[0026] Figure 2 This is a block diagram of a low-power voltage sampling circuit of the present invention;

[0027] Figure 3 This is a schematic diagram of a voltage sampling circuit embodiment 1 of the present invention;

[0028] Figure 4 This is a schematic diagram of a second embodiment of a voltage sampling circuit of the present invention;

[0029] Figure 5 This is a schematic diagram of a third embodiment of a voltage sampling circuit of the present invention. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitution, modification, equivalent method and scheme made on the spirit and range of the present invention.

[0031] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without these detailed descriptions.

[0032] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all simplified and not in exact proportions, in order to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] like Figure 2 As shown, a block diagram of the voltage sampling circuit of the present invention is illustrated. The voltage sampling circuit is used to sample the voltage VIN of a certain PIN pin in an integrated circuit / chip. The integrated circuit / chip is usually a switch controller in a switch circuit. The voltage of the PIN pin can be used to provide the voltage of other modules in the integrated circuit / chip, such as an LED dimming module and an overvoltage protection module, so as to realize the dimming or overvoltage gear adjustment functions of the subsequent circuit. Therefore, the sampling accuracy of the PIN pin voltage is required to be high. Usually, a current source I1 is set inside the integrated circuit, and a large resistor R1 is also connected to the PIN pin port. The current source I1 outputs a small current flowing through the resistor R1 to generate a voltage as the voltage on the PIN pin, so as to improve the sampling accuracy. Due to the power consumption requirements inside the integrated circuit chip, the current output by the current source is generally very small. Therefore, the resistance value of the large resistor R1 is set to be relatively large. However, due to the presence of parasitic capacitance Ck in the circuit, such as Figure 2 As shown, one end of the parasitic capacitor Ck is connected to the sampling port, and the other end is the generated noise node A. Parasitic current will be generated on the parasitic capacitor Ck due to some signal changes in the system. The parasitic current will generate a large parasitic voltage on the large resistor R1. The parasitic voltage will interfere with the sampling of the PIN pin voltage, so that the sampling accuracy of the PIN pin voltage is affected. Figure 2The voltage sampling circuit shown can solve the problem that the sampling of the PIN pin voltage is susceptible to interference. The voltage sampling circuit of the present invention includes a first sampling circuit 01, an active clamping circuit 03, a second sampling circuit 04 and a holding capacitor Co. The input end of the first sampling circuit 01 is connected to a sampling port, which is the PIN pin port. The active clamping circuit 02 is connected between the first sampling circuit 01 and the second sampling circuit 03. The output end of the second sampling circuit 03 is connected to the holding capacitor Co, and the voltage on the holding capacitor Co is the sampled output voltage VO. Preferably, the voltage sampling circuit also includes a current limiting resistor R connected between the sampling port and the active clamping circuit 02, which is used to limit the current between the sampling port and the clamping circuit 02. During voltage sampling, when the sampling control signal C is valid, the first sampling circuit 01 and the second sampling circuit 03 are turned on at the same time, and the active clamping circuit 02 does not work. At this time, the voltage VIN of the sampling port charges and discharges the holding capacitor Co through the current limiting resistor R; when the sampling control signal C is invalid, the first sampling circuit 01 and the second sampling circuit 03 are turned off at the same time, and the active clamping circuit 02 works to clamp the voltage at the second end of the first sampling circuit 01 and the second sampling circuit 02 to a fixed voltage, namely the clamping voltage, which is greater than or equal to zero voltage 0 and less than or equal to the preset voltage VDD, which is usually the power supply voltage. During non-voltage sampling, the sampling control signal C is invalid. When VIN>VDD+V THP or VIN<-V THN When the first sampling circuit 01 is turned on, the voltage at the output end of the first sampling circuit 01 is clamped at VM2 through the active clamping circuit 02, and VM2 will not be greater than VDD+V THP or less than -V THN , the conduction voltage of the second sampling circuit 03 is less than the threshold voltage, and the second sampling circuit 03 will not be turned on, thereby preventing the noise of the sampling port voltage VIN from affecting the accuracy of the output sampling voltage VO.

[0034] — is valid when it is at high level VDD, and is invalid when the sampling control signal C is at low level 0; -V THP 、V THN They are the turn-on threshold voltages of the PMOS and NMOS tubes in the sampling circuit respectively.

[0035] like Figure 3As shown, a schematic diagram of a voltage sampling circuit embodiment of the present invention is shown, the first sampling circuit 01 and the second sampling circuit 03 respectively include a PMOS tube and an NMOS tube, the PMOS tube and the NMOS tube are connected in parallel, the active clamping circuit 02 includes an NMOS type active clamping tube M3, the drain of the active clamping tube M3 is connected to the first sampling circuit 01 and the second sampling circuit 03, and the source of the active clamping tube M3 is connected to the reference ground; specifically, the first sampling tube includes a PMOS tube P2 and The NMOS tube M2, the second sampling tube includes the PMOS tube P1 and the NMOS tube M1; the source of the P2 tube is connected to the drain of the M2 tube, and its connection end is connected to one end of the current limiting resistor R, and the other end of the current limiting resistor is connected to the sampling end, the drain of the P2 tube is connected to the source of the M2 tube, and its connection end is connected to the drain of the active clamp tube P1; the source of the P1 tube is connected to the drain of the M1 tube, and its connection end is connected to the drain of the active clamp tube P1, the drain of the P1 tube is connected to the source of the M1 tube, and its connection end is connected to the holding capacitor Co. Among them, the control ends of the P1 tube and the P2 tube in the voltage sampling circuit receive the sampling control signal C, and the control ends of the M1 tube and the M2 tube receive the reverse signal of the sampling control signal C. The control end of the M3 tube receives signal; when the C signal is high level VDD, When the C signal is at a low level of 0 potential, When the sampling control signal C is high level VDD, it is valid. When the sampling control signal C is low level 0 and the potential is invalid, the P2 tube, M2 tube, P1 tube, and M1 tube are all turned on, and the M3 tube is turned off, so as to keep the capacitor Co charged and discharged; when the sampling control signal C is low level 0 and the potential is invalid, When the high level VDD is valid, the P2 tube, the M2 tube, the P1 tube, and the M1 tube are all turned off, and the active clamp tube M3 is turned on. The voltage VM2 at the connection end of the second sampling circuit 03 and the first sampling circuit 01 is clamped at the ground potential. The first sampling circuit 01 is easily interfered by noise and mis-turned on, but the active voltage VM2 is clamped to ensure that the gate-source voltage of the switch tube in the second sampling circuit 02 does not reach the turn-on threshold voltage, that is, the turn-on voltage of the second sampling circuit 02 does not reach the threshold voltage, and the second sampling circuit 02 remains turned off and will not be mis-turned on. Therefore, the interference and noise on the sampling terminal voltage VIN will not affect the accuracy of the sampled voltage VO. The active clamp circuit enhances the suppression of noise and effectively avoids the influence of noise on sampling accuracy.

[0036] In addition, if the active clamping tube is a PMOS tube, and the voltage VIN at the sampling end is a negative voltage, when the sampling control signal C is invalid, the voltage VM2 at the connection end can only be clamped at -Vth (Vth is the threshold voltage between the gate and source of the NMOS tube M3, i.e., the conduction threshold voltage), which will cause the second sampling circuit to be mis-conducted, so the active clamping tube in this embodiment can only be an NMOS tube, or an N-type transistor. In addition, the current limiting resistor R can also be connected between the first sampling resistor 01 and the connection end of the active clamping circuit 02. When the active clamping circuit 02 is working and the first sampling circuit 01 is mis-conducted, the current limiting resistor R can limit the current flowing from the sampling end into the active clamping circuit 02 to be too large, thereby damaging the MOS tube. Furthermore, the first sampling circuit 01 and the second sampling circuit 02 may also include a single MOS tube respectively. However, the current flowing through the single MOS tube is limited, and the two MOS tubes connected in parallel can be used to shunt the current. When the current of one MOS tube is greater than the current of the other MOS tube, the MOS tube with a large current will generate more heat, thereby causing an increase in the on-resistance, thereby reducing the current flowing through and achieving current sharing; preferably, the two MOS tubes have the same size, that is, the width-to-length ratio of the two MOS tubes is the same; further, the first sampling circuit 01 and the second sampling circuit 02 may also include more than two parallel-connected switch tubes respectively, so that the current can be further shunted than two switch tubes.

[0037] like Figure 3 As shown, the schematic diagram of the voltage sampling circuit embodiment 2 of the present invention is illustrated. The difference from the embodiment 1 lies in the difference of the active clamping circuit 02. The active clamping circuit 02 of this embodiment clamps the voltage VM at the connection end of the first sampling circuit 01 and the second sampling circuit 02 to VDD, and includes a first PMOS type active clamping tube P3, the drain of which is connected to the connection end of the first sampling circuit 01 and the second sampling circuit 02, the source of which receives the preset voltage VDD, and the gate of which receives the sampling control signal C. Figure 2 In the illustrated embodiment 1, when the sampling control signal C is at a low level and the potential is invalid, the active clamping tube P3 is turned on and the voltage VM2 is clamped at VDD. Similarly, if the active clamping tube of this embodiment is an NMOS tube, and the voltage VIN at the sampling end is a large positive voltage, when the sampling control signal C is invalid, the voltage VM2 at the connection end can only be clamped to VDD+Vth, where -Vth is the gate-source threshold voltage of the P3 tube, i.e., the conduction threshold voltage, which can easily cause the second sampling circuit to be mis-conducted. Therefore, the active clamping tube in this embodiment can only be a PMOS tube, or a P-type transistor. The same parts of this embodiment 2 as those of the embodiment 1 are not further described here.

[0038] like Figure 4As shown, the schematic diagram of the third embodiment of the voltage sampling circuit of the present invention is illustrated. The difference from the first embodiment is that the first sampling circuit 01 and the second sampling circuit 03 are different. In this embodiment, the first sampling circuit 01 and the second sampling circuit 03 are respectively connected by two parallel NMOS tubes. The drains of the two NMOS tubes of the first sampling circuit 01 are connected to the sampling port through the current limiting resistor R, and the source is connected to the clamping circuit, and the gate receives the sampling control signal C; the drains of the two NMOS tubes of the second sampling circuit 03 are also connected to the clamping circuit, and the source is connected to the holding capacitor C, and the gate receives the sampling control signal C. Since the highest voltage received by the gate of the MOS tube in the sampling circuit is VDD, the highest voltage that can be sampled in this embodiment is VDD-Vth. Similarly, if the first sampling circuit 01 and the second sampling circuit 03 are composed of two parallel PMOS tubes, the highest voltage that can be sampled is only VDD. The voltage sampling range of this embodiment is very limited, and this embodiment is only used when sampling small voltages. Therefore, the first sampling circuit 01 and the second sampling circuit 03 usually sample the structure of the second embodiment, and the voltage sampling range of this embodiment is not limited. The rest of the same parts as the above-mentioned other embodiments will not be further described.

[0039] The present invention enhances the ability of the voltage on the holding capacitor Co to suppress input noise, and effectively avoids the influence of the input noise on the accuracy of voltage sampling.

[0040] Although the embodiments are described and illustrated separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that the embodiments can be replaced and integrated. If the content is not clearly recorded in one of the embodiments, reference can be made to another recorded embodiment.

[0041] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A low-power voltage sampling circuit, characterized in that: The invention comprises a first sampling circuit, an active clamping circuit, a second sampling circuit and a holding capacitor, The active clamping circuit is connected between the first sampling circuit and the second sampling circuit; The input end of the first sampling circuit is connected to the sampling port, the output end of the second sampling circuit is connected to the holding capacitor, and the voltage on the holding capacitor is the voltage sampling signal output by the voltage sampling circuit; Wherein, during the voltage sampling period, when the sampling control signal is valid, the first sampling circuit and the second sampling circuit are turned on, and the active clamping circuit is not enabled; when the sampling control signal is invalid, the first sampling circuit and the second sampling circuit are turned off, and the active clamping circuit is enabled; The sampling port is a pin port of an integrated circuit. A first resistor is connected between the sampling port and a reference ground, and a given first current flows through the first resistor.

2. The voltage sampling circuit according to claim 1, characterized in that: A current limiting resistor is also included, and the current limiting resistor is connected between the sampling port and the clamping circuit.

3. The voltage sampling circuit according to claim 1, characterized in that: When the sampling control signal is invalid, the active clamping circuit clamps the voltage at the connection end of the first sampling circuit and the second sampling circuit, so that the on-voltage of the second sampling circuit does not reach the threshold voltage and the second sampling circuit remains off.

4. The voltage sampling circuit according to claim 1, characterized in that: The first sampling circuit includes a first sampling switch tube, and the second sampling circuit includes a second sampling switch tube.

5. The voltage sampling circuit according to claim 4, characterized in that: The first sampling switch tube and the second sampling switch tube respectively include one or more switch tubes; if the first sampling switch tube and the second sampling switch tube respectively include multiple switch tubes, the multiple switch tubes are connected in parallel.

6. The voltage sampling circuit according to claim 4, characterized in that: The first sampling switch tube and the second sampling switch tube respectively include two switch tubes, and the two switch tubes are connected in parallel.

7. The voltage sampling circuit according to claim 6, characterized in that: The two switch tubes include a PMOS tube and an NMOS tube.

8. The voltage sampling circuit according to claim 6, characterized in that: The two switch tubes include two NMOS tubes.

9. The voltage sampling circuit according to claim 1, characterized in that: The active clamping circuit includes a clamping switch tube, a first end of the clamping switch tube is connected to a connection end of the first sampling circuit and the second sampling circuit, and a second end of the clamping switch tube receives a clamping voltage.

10. The voltage sampling circuit according to claim 9, characterized in that: The clamping voltage is greater than or equal to a zero reference voltage and less than or equal to a preset voltage value.

11. The voltage sampling circuit according to claim 10, characterized in that: When the clamping voltage is equal to the zero reference voltage, setting the clamping switch tube to a PMOS tube; When the clamping voltage is equal to a preset voltage value, the clamping switch tube is set to be an NMOS tube.

12. An integrated chip, comprising a sampling port, characterized in that: It also includes the low-power voltage sampling circuit described in any one of claims 1-11, and the voltage sampling circuit is used to sample the signal of the sampling port on the integrated chip.

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