Current sampling circuit and control circuit applying same
By setting a circuit structure where the voltage difference value is equal to the first voltage between the gates of the first transistor and the second transistor, the problem of poor current sampling accuracy in the prior art is solved, and high-precision current sampling in the saturation region is achieved , ensure the accuracy of the current proportional coefficient flowing through the transistor.
Patent Information
- Application Number
- CN202420915697.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-28
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-04-28
AI Technical Summary
When the transistor is in the saturation region, the drain-source voltage changes greatly, resulting in a deterioration in the current sampling accuracy and unable to effectively limit the current.
By setting a first voltage generation circuit between the gates of the first transistor and the second transistor, the difference between the gate voltage of the second transistor and the gate voltage of the first transistor is equal to the first voltage, thereby reducing the gate source voltage. The difference value improves the current sampling accuracy.
When setting the difference between the first voltage and the sampling voltage equals zero or close to zero, ensure that the gate and source voltage of the second transistor is always equal or close to equal to the gate and source voltage of the first transistor, greatly improving the current sampling accuracy, especially when the transistor is operated. Maintain high-precision current sampling in the saturation zone.
Smart Images
Figure CN222319363U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power electronics, in particular to a current sampling circuit and a control circuit using the same. Background Art
[0002] In some application scenarios, such as Figure 1 , the drain-source voltage of transistor M0 varies in a large range, for example, it varies between 30V and 0V. When transistor M0 is fully turned on and the drain-source voltage becomes larger, transistor M0 transitions from the linear region to the saturation region, and the current i0 flowing through transistor M0 becomes very large. In order to protect transistor M0, the control circuit of transistor M0 needs to limit the current i0 by reducing the gate-source voltage of transistor M0 when the current i0 is too large. For example, resistor R0 can be used to receive the sampling current i0′ representing the current i0 flowing through transistor M0, and then the error amplifier U1 is used to amplify the error between the reference voltage Vref and the voltage of resistor R0, and the output end of the error amplifier U1 is connected to the gate of transistor M0. Therefore, the control circuit requires a current sampling circuit to sample the current flowing through transistor M0. The current sampling circuit needs to maintain a high current sampling accuracy when transistor M0 is in the saturation region and its drain-source voltage varies in a large range.
[0003] like Figure 2 As shown, a current sampling circuit 100 in the prior art includes a mirror tube M11 and a sampling resistor Rs. The mirror tube M11 and the transistor M0 form a current mirror structure. The sampling resistor Rs is connected in series with the mirror tube M11. The current sampling circuit 100 generates a sampling current i0′ according to the voltage of the sampling resistor Rs. The current flowing through the mirror tube M11 is approximately proportional to the current flowing through the transistor M0. Therefore, the current i0 flowing through the transistor M0 can be approximately inferred according to the voltage of the sampling resistor Rs or according to the sampling current i0′. However, due to the voltage dividing effect of the sampling resistor Rs, the gate-source voltage of the mirror tube M11 and the gate-source voltage of the transistor M0 will be different, which will cause the proportionality coefficient between the current actually flowing through the mirror tube M11 and the current flowing through the transistor M1 to deviate from the designed proportionality coefficient, which will deteriorate the current sampling accuracy. Utility Model Content
[0004] In view of this, an object of the present invention is to provide a current sampling circuit and a control circuit using the same, so as to solve the technical problem of poor current sampling accuracy in the prior art.
[0005] The technical solution of the utility model is, in a first aspect, to provide a current sampling circuit for sampling a current flowing through a first transistor, the state of the first transistor being controlled by a control circuit, and the current sampling circuit comprising:
[0006] a second transistor, forming a first current mirror with the first transistor;
[0007] a sampling resistor, connected in series with the second transistor, one end of which is connected to the source of the second transistor, so as to generate a sampling voltage representing the current flowing through the first transistor;
[0008] a first voltage generating circuit, receiving the sampled voltage and connected to the gate of the first transistor and the gate of the second transistor, to generate a first voltage according to the sampled voltage, so that a difference between the gate voltage of the second transistor and the gate voltage of the first transistor is equal to the first voltage;
[0009] Wherein, the voltage of the sampling resistor is the sampling voltage.
[0010] Optionally, a difference between the first voltage and the sampled voltage is equal to zero or close to zero.
[0011] Optionally, when the first transistor operates in a saturation region, the current sampling circuit samples the current flowing through the first transistor.
[0012] Optionally, the first voltage generating circuit includes:
[0013] A first current generating circuit, generating a first current according to the sampled voltage;
[0014] a first resistor, a first end of which is connected to the gate of the first transistor, a second end of which is connected to the gate of the second transistor, and the first resistor receives the first current;
[0015] The first current flows from the second end of the first resistor to the first end of the first resistor, and the voltage of the first resistor is the first voltage.
[0016] Optionally, the first current generating circuit includes:
[0017] a second current mirror including a third transistor and a fourth transistor;
[0018] A second resistor connected in series with the third transistor;
[0019] an operational amplifier, wherein a first input terminal receives the sampled voltage, a second input terminal receives the voltage of the second resistor, and an output terminal is connected to the gate of the third transistor and the gate of the fourth transistor;
[0020] The first current generating circuit outputs the first current according to the current flowing through the fourth transistor.
[0021] Optionally, a current flowing through the fourth transistor is used as the first current;
[0022] Alternatively, the current flowing through the fourth transistor is mirrored to obtain the first current.
[0023] Optionally, the current sampling circuit further includes:
[0024] The sampling current generating circuit generates a sampling current representing a current flowing through the first transistor according to the sampling voltage.
[0025] Optionally, the current sampling circuit includes a sampling current generating circuit, and the sampling current generating circuit includes:
[0026] The fifth transistor forms a third current mirror with the third transistor to generate a sampling current representing the current flowing through the first transistor.
[0027] Optionally, the first transistor and the second transistor are NMOS transistors.
[0028] Optionally, the control circuit further includes:
[0029] A third resistor, receiving the sampled current;
[0030] An error amplifier, wherein a first input terminal receives a first reference voltage, a second input terminal receives a voltage of the third resistor, and an output terminal is connected to a gate of the first transistor or to a gate of the second transistor.
[0031] Optionally, when the output end of the error amplifier is connected to the gate of the first transistor, the second end of the first resistor is connected to the first current generating circuit to receive the first current;
[0032] When the output terminal of the error amplifier is connected to the gate of the second transistor, the first terminal of the first resistor is connected to the first current generating circuit to receive the first current.
[0033] Optionally, the control circuit includes:
[0034] A first switch, a first end of which is connected to the gate of the first transistor, and a second end of which is connected to a reference ground;
[0035] A comparator has a first input terminal receiving the sampled voltage, a second input terminal receiving a second reference voltage, and an output terminal connected to the control terminal of the first switch.
[0036] In a second aspect, the utility model further provides a control circuit, wherein the control circuit includes the current sampling circuit, and the control circuit controls the first transistor according to a signal generated by the current sampling circuit.
[0037] The circuit structure of the utility model has the following advantages compared with the prior art: a first voltage generating circuit for generating a first voltage according to a voltage of a sampling resistor is provided between the gate of the first transistor and the gate of the second transistor, so that the difference between the gate voltage of the second transistor and the gate voltage of the first transistor is equal to the first voltage, which can reduce the difference between the gate-source voltage of the first transistor and the gate-source voltage of the second transistor, thereby improving the current sampling accuracy; when the difference between the first voltage and the sampling voltage is set to be equal to zero or close to zero, the gate-source voltage of the second transistor and the gate-source voltage of the first transistor can be always equal or close to equal, thereby greatly improving the current sampling accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A circuit structure schematic diagram of a transistor control circuit;
[0039] Figure 2 A schematic diagram of the circuit structure of a current sampling circuit in the prior art;
[0040] Figure 3 A circuit block diagram of an embodiment of a current sampling circuit of the utility model;
[0041] Figure 4 Based on Figure 3 A schematic diagram of the circuit structure of a first embodiment of a current sampling circuit;
[0042] Figure 5 Based on Figure 3 A circuit structure diagram of a second embodiment of a current sampling circuit. DETAILED DESCRIPTION
[0043] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitution, modification, equivalent method and scheme made within the spirit and scope of the present invention.
[0044] In order to enable the public to have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, and those skilled in the art can fully understand the present invention without these detailed descriptions.
[0045] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all simplified and not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0046] Figure 3The circuit block diagram of the current sampling circuit 200 of the utility model is shown. The current sampling circuit 200 is used to sample the current i0 flowing through the first transistor M0. In some implementations, the current sampling circuit 200 includes a second transistor M21, a sampling resistor Rs and a first voltage generating circuit 201. The second transistor M21 and the first transistor M0 form a first current mirror. The sampling resistor Rs is connected in series with the second transistor M21. One end of the sampling resistor Rs is connected to the source of the second transistor M21 to generate a sampling voltage Vs representing the current flowing through the first transistor, wherein the voltage of the sampling resistor Rs, that is, the voltage difference between the two ends of the sampling resistor Rs, is the sampling voltage Vs. The first voltage generating circuit 201 is connected to the gate of the first transistor M0 and the gate of the second transistor M21, receives the sampling voltage Vs, and generates a first voltage according to the sampling voltage Vs, so that the difference between the gate voltage of the second transistor M21 and the gate voltage of the first transistor M0 is equal to the first voltage. In some other implementations, the current sampling circuit 200 further includes a sampling current generating circuit 202, and the sampling current generating circuit 202 generates a sampling current i0′ representing the current i0 flowing through the first transistor according to the sampling voltage Vs. In a preferred embodiment, the difference between the first voltage and the sampling voltage Vs can be set to be equal to zero or close to zero. In one embodiment, it can be set that when the first transistor M0 operates in the saturation region, the current sampling circuit 200 samples the current flowing through the first transistor M0. Specifically, in one embodiment, the first transistor M0 and the second transistor M21 are, for example, NMOS tubes, and the drain of the first transistor M0 and the drain of the second transistor M21 are both connected to the high potential end, wherein the drain of the first transistor M0 and the drain of the second transistor M21 can be as follows Figure 3 The first transistor M0 and the second transistor M21 are connected as shown, or they may not be connected, and the present invention does not limit this. The source of the first transistor M0 is connected to the reference ground, and the sampling resistor Rs is connected between the source of the second transistor M21 and the reference ground, wherein the mirror ratio coefficient of the first current mirror formed by the second transistor M21 and the first transistor M0 can be set arbitrarily. Preferably, the ratio of the width-to-length ratio of the first transistor M0 to the width-to-length ratio of the second field effect transistor 22 can be set to k:1, where k is a natural number greater than 1. It should be noted that the present invention Figures 3 to 5 The first transistor M0 and the second transistor M21 are introduced as NMOS transistors, but the types of the first transistor M0 and the second transistor M21 of the utility model are not limited thereto, and can also be any other type of field effect transistors, such as GaN transistors, SiC transistors, etc.
[0047] The current sampling circuit 200 of the present invention sets a first voltage generating circuit 201 between the gate of the first transistor M0 and the gate of the second transistor M21, so that the difference between the gate voltage of the second transistor M21 and the gate voltage of the first transistor M0 is equal to the first voltage, which can reduce the difference between the gate-source voltage of the first transistor M0 and the gate-source voltage M11 of the second transistor, thereby reducing the deviation between the proportionality coefficient between the current actually flowing through the second transistor M21 and the current flowing through the first transistor M0 and the designed proportionality coefficient, thereby improving the sampling voltage Vs and / or the sampling current i0′ representing the current flowing through the first transistor M0. The accuracy of the current i0 of the transistor M0 is improved, and the current sampling accuracy is improved; in a preferred embodiment in which the difference between the first voltage and the sampling voltage Vs is set to be zero or close to zero, the gate-source voltage of the second transistor M21 and the gate-source voltage of the first transistor M0 can be always equal or close to equal, further improving the current sampling accuracy, wherein, when the drain-source voltage of the first transistor M0 changes within a voltage range that enables the first transistor M0 to operate in a saturation region, the proportionality coefficient between the current actually flowing through the mirror tube M11 and the current flowing through the transistor M1 is always equal or close to equal to the designed proportionality coefficient, which can ensure extremely high current sampling accuracy.
[0048] Please continue to refer to Figure 3 , Figure 3A circuit structure diagram of a control circuit for controlling the state of the first transistor is also shown, and the control circuit controls the first transistor according to the signal generated by the current sampling circuit 200. In one embodiment, the control circuit controls the first transistor according to the sampling current i0′ and the sampling voltage Vs generated by the current sampling circuit 200. Specifically, the control circuit includes a third resistor R0, an error amplifier U1, a first switch S1, and a comparator U3, wherein the third resistor R0 receives the sampling current i0′, the first input terminal of the error amplifier U1 receives the first reference voltage Vref1, the second input terminal receives the voltage of the third resistor R0, and the output terminal is connected to the gate of the first transistor M0. Of course, in another embodiment, the output terminal of the error amplifier U1 can also be set to be connected to the gate of the second transistor M21. Further, the first input terminal of the error amplifier U1 is a positive phase input terminal, and the second input terminal is a negative phase input terminal. When the current i0 flowing through the first transistor M0 increases, the sampling current i0′ increases accordingly, and the voltage of the third resistor R0 increases. Accordingly, the output voltage of the error amplifier U1 decreases, and the gate voltage of the first transistor M0 is controlled to decrease, so that the gate-source voltage of the first transistor M0 is reduced. The voltage drop is reduced, thereby limiting the current i0 flowing through the first transistor M0. Since the current sampling accuracy of the current sampling circuit 200 is high, the control circuit of this embodiment can realize high-precision control of the current flowing through the first transistor M0; the first end of the first switch S1 is connected to the gate of the first transistor, and the second end is connected to the reference ground; the first input end of the comparator U3 receives the sampling voltage, the second input end receives the second reference voltage Vref2, and the output end is connected to the control end of the first switch S1. Further, the first input end of the comparator U3 is a positive input end, and the second input end is a negative input end. When the current i0 flowing through the first transistor M0 increases to make the voltage of the third resistor R0 reach the second reference voltage Vref2, the output level of the comparator U3 jumps, controls the first switch S1 to be turned on, and pulls the gate of the first transistor M0 to the reference ground, thereby realizing a fast overcurrent protection function. Since the current sampling accuracy of the current sampling circuit 200 is high, the control circuit of this embodiment can realize high-precision overcurrent protection. In another embodiment, the control circuit may also include a third resistor R0 and an error amplifier U1, but does not include the first switch S1 and the comparator U3. Accordingly, the control circuit of this embodiment controls the gate voltage of the first transistor according to the sampling current i0′ generated by the current sampling circuit 200, thereby controlling the current i0 flowing through the first transistor.In another embodiment, the control circuit may include a first switch S1 and a comparator U3, but not a third resistor R0 or an error amplifier U1. Accordingly, the control circuit of this embodiment controls the turning off and on of the first switch S1 according to the sampling voltage Vs generated by the current sampling circuit 200, thereby controlling the first transistor M0 to work normally, or pulling its gate down to the reference ground to achieve overcurrent protection. It is easy to understand that in this embodiment, the current sampling circuit 200 may not include the sampling current generating circuit 202. In other embodiments, the control circuit may not include the third resistor R0, and the first input terminal of the error amplifier U1 may receive the sampling voltage Vs (not shown in the figure), which can also achieve high-precision control of the current i0 flowing through the first transistor. It is easy to understand that in these embodiments, the current sampling circuit 200 may not include the sampling current generating circuit 202.
[0049] Combine the following Figure 3 and Figure 4, the circuit structure of the first embodiment of the current sampling circuit 200 of the utility model is introduced. In this embodiment, the current sampling circuit 200 includes a second transistor M21, a sampling resistor Rs, a first voltage generating circuit 201 and a sampling current generating circuit 202, wherein the first voltage generating circuit 201 includes a first resistor R1 and a first current generating circuit 2011, and the first current generating circuit 2011 generates a first current i1 according to the sampling voltage Vs; the first end of the first resistor R1 is connected to the gate of the first transistor M0, and the second end is connected to the gate of the second transistor M21, and the first resistor R1 receives the first current i1; wherein, the first current i1 flows from the second end of the first resistor R1 to the first end of the first resistor R1, and the voltage of the first resistor R1, that is, the voltage difference between the second end and the first end of the first resistor R1, is the first voltage. Specifically, the output end of the error amplifier U1 in the control circuit is connected to the gate of the first transistor M0, and the second end of the first resistor R1 is connected to the first current generating circuit 2011 to receive the first current i1. In this embodiment, the output end of the error amplifier U1 is connected to the gate of the first transistor M0, and the gate voltage of the second transistor M21 is pulled up to achieve a difference between the gate voltage of the second transistor M21 and the gate voltage of the first transistor M0 that is equal to the first voltage. By way of example, the first current generating circuit 2011 includes a second current mirror, a second resistor R22 and an operational amplifier U2, wherein the second current mirror includes a third transistor M22 and a fourth transistor M23; the second resistor R22 is connected in series with the third transistor M22; the first input terminal of the operational amplifier U2 receives a sampling voltage Vs, the second input terminal receives the voltage of the second resistor R22, and the output terminal is connected to the gate of the third transistor M22 and the gate of the fourth transistor M23; the first current generating circuit 2011 outputs the first current i4 according to the current flowing through the fourth transistor M23; in this embodiment, the current flowing through the fourth transistor M23 is used as the first current i1. According to the "virtual short" characteristic of the operational amplifier U2, the voltage of the second resistor R22 is equal to the sampling voltage Vs, so the current flowing through the third transistor M22 is equal to Vs / R22, and the fourth transistor M23 obtains the first current i1 after mirroring the current flowing through the third transistor M22. The first voltage generated by the first resistor R1 receiving the first current i1 is equal to i1·R1. Therefore, in an embodiment where the difference between the first voltage and the sampling voltage Vs needs to be set to zero or close to zero, it is necessary to set the mirror ratio coefficient of the second current mirror formed by the third transistor M22 and the fourth transistor M23 according to the resistance ratio between the second resistor R22 and the first resistor R1.As a further example, the sampling current generating circuit 202 includes a fifth transistor M24, which forms a third current mirror with the third transistor M22, and generates a sampling current i0′ representing the current flowing through the first transistor by mirroring the current flowing through the third transistor M22, wherein the mirror proportional coefficient of the third current mirror can be set arbitrarily. In this embodiment, the sampling current generating circuit 202 reuses part of the circuit structure of the first current generating circuit 2011, thereby simplifying the system circuit.
[0050] Figure 5 The circuit structure diagram of the second embodiment of the current sampling circuit 200 of the utility model is shown. The circuit structure of the second embodiment of the current sampling circuit 200 is basically the same as the circuit structure of the first embodiment. The main difference is that in this embodiment, the output end of the error amplifier U1 in the control circuit is connected to the gate of the second transistor M21, and the difference between the gate voltage of the second transistor M21 and the gate voltage of the first transistor M0 is equal to the first voltage by pulling down the gate voltage of the first transistor M0. Specifically, the first current generating circuit 2011 in this embodiment also includes a fourth current mirror, which mirrors the current flowing through the fourth transistor M23 to obtain the first current i1, and the first end of the first resistor R1 is connected to the first current generating circuit 2011 to receive the first current i1. By way of example, the fourth current mirror includes a sixth transistor M25 and a seventh transistor M26. Similarly, in an embodiment where the difference between the first voltage and the sampling voltage Vs needs to be set equal to zero or close to zero, it is necessary to set the mirror proportional coefficient of the second current mirror formed by the third transistor M22 and the fourth transistor M23, and the mirror proportional coefficient of the fourth current mirror according to the resistance ratio between the second resistor R22 and the first resistor R1.
[0051] It should also be noted that the first and second embodiments of the present application are merely examples of the specific circuit structures of the current sampling circuit 200 and the control circuit using the same, and are not intended to limit the circuit structures thereof. The current sampling circuit 200 and the control circuit using the same may also sample other types of circuit structures. For example, the first voltage generating circuit 201 in the current sampling circuit 200 may also adopt any other type of voltage-controlled voltage source circuit structure to generate a first voltage according to the sampling voltage; when the current sampling circuit 200 includes a sampling current generating circuit 202, the sampling current generating circuit 202 may also adopt any other type of voltage-controlled current source circuit structure to generate a sampling current according to the sampling voltage; for another example, the control circuit may also be a circuit that generates a switch control signal according to a signal generated by the current sampling circuit 200, and controls the on and off of the first transistor according to the switch control signal.
[0052] In summary, the current sampling circuit 200 of the present invention sets the first voltage generating circuit 201 between the gate of the first transistor M0 and the gate of the second transistor M21, so that the difference between the gate voltage of the second transistor M21 and the gate voltage of the first transistor M0 is equal to the first voltage, which can reduce the difference between the gate-source voltage of the first transistor M0 and the gate-source voltage M11 of the second transistor, and improve the current sampling accuracy; when the difference between the first voltage and the sampling voltage is set to be equal to zero or close to zero, the gate-source voltage of the second transistor M21 and the gate-source voltage of the first transistor M0 can be always equal or close to equal, further improving the current sampling accuracy, wherein, when the drain-source voltage of the first transistor M0 changes within the voltage range that can make the first transistor M0 work in the saturation region, the proportionality coefficient between the current actually flowing through the mirror tube M11 and the current flowing through the transistor M1 is always equal or close to equal to the designed proportionality coefficient, which can ensure extremely high current sampling accuracy. In addition, the first voltage generating circuit 201 in the current sampling circuit 200 has lower design risk and difficulty in the low voltage domain. At the same time, since the current sampling circuit 200 has high current sampling accuracy, the control circuit using the current sampling circuit 200 can achieve high-precision control of the current flowing through the first transistor M0 and / or high-precision overcurrent protection.
[0053] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.
Claims
1. A current sampling circuit for sampling a current flowing through a first transistor, wherein the state of the first transistor is controlled by a control circuit, characterized in that: include: a second transistor, forming a first current mirror with the first transistor; a sampling resistor, connected in series with the second transistor, one end of which is connected to the source of the second transistor, so as to generate a sampling voltage representing the current flowing through the first transistor; a first voltage generating circuit, receiving the sampled voltage and connected to the gate of the first transistor and the gate of the second transistor, to generate a first voltage according to the sampled voltage, so that a difference between the gate voltage of the second transistor and the gate voltage of the first transistor is equal to the first voltage; Wherein, the voltage of the sampling resistor is the sampling voltage.
2. The current sampling circuit according to claim 1, characterized in that: A difference between the first voltage and the sampled voltage is equal to zero or close to zero.
3. The current sampling circuit according to claim 1, characterized in that: When the first transistor operates in a saturation region, the current sampling circuit samples the current flowing through the first transistor.
4. The current sampling circuit according to claim 1, characterized in that: The first voltage generating circuit comprises: A first current generating circuit, generating a first current according to the sampled voltage; a first resistor, a first end of which is connected to the gate of the first transistor, a second end of which is connected to the gate of the second transistor, and the first resistor receives the first current; The first current flows from the second end of the first resistor to the first end of the first resistor, and the voltage of the first resistor is the first voltage.
5. The current sampling circuit according to claim 4, characterized in that: The first current generating circuit comprises: a second current mirror including a third transistor and a fourth transistor; A second resistor connected in series with the third transistor; An operational amplifier, wherein a first input terminal receives the sampled voltage, a second input terminal receives the voltage of the second resistor, and an output terminal is connected to the gate of the third transistor and the gate of the fourth transistor; The first current generating circuit outputs the first current according to the current flowing through the fourth transistor.
6. The current sampling circuit according to claim 5, characterized in that: the current flowing through the fourth transistor is used as the first current; Alternatively, the current flowing through the fourth transistor is mirrored to obtain the first current.
7. The current sampling circuit according to claim 4, characterized in that: The current sampling circuit also includes: The sampling current generating circuit generates a sampling current representing a current flowing through the first transistor according to the sampling voltage.
8. The current sampling circuit according to claim 5, characterized in that: The current sampling circuit further includes a sampling current generating circuit, and the sampling current generating circuit includes: The fifth transistor forms a third current mirror with the third transistor to generate a sampling current representing the current flowing through the first transistor.
9. The current sampling circuit according to claim 1, characterized in that: The first transistor and the second transistor are NMOS transistors.
10. The current sampling circuit according to claim 7 or 8, characterized in that: The control circuit comprises: A third resistor, receiving the sampled current; An error amplifier, wherein a first input terminal receives a first reference voltage, a second input terminal receives a voltage of the third resistor, and an output terminal is connected to a gate of the first transistor or to a gate of the second transistor.
11. The current sampling circuit according to claim 10, characterized in that: When the output terminal of the error amplifier is connected to the gate of the first transistor, the second terminal of the first resistor is connected to the first current generating circuit to receive the first current; When the output terminal of the error amplifier is connected to the gate of the second transistor, the first terminal of the first resistor is connected to the first current generating circuit to receive the first current.
12. The current sampling circuit according to claim 1, characterized in that: The control circuit comprises: A first switch, a first end of which is connected to the gate of the first transistor, and a second end of which is connected to a reference ground; A comparator has a first input terminal receiving the sampled voltage, a second input terminal receiving a second reference voltage, and an output terminal connected to the control terminal of the first switch.
13. A control circuit, characterized in that: Comprising the current sampling circuit according to any one of claims 1 to 12, the control circuit controls the first transistor according to the signal generated by the current sampling circuit.