Interconnection system and computer server cluster

Abstract

The utility model provides an interconnection system and a computer server cluster, and relates to the technical field of computers, in particular to the technical field of interconnection. According to the specific implementation scheme, the interconnection system comprises a computing unit, a memory unit and a storage unit; the computing unit is arranged on the circuit board, and the circuit board is further provided with a plurality of high-speed interconnection interfaces; the memory unit comprises a plurality of memory subunits, and the memory unit is connected with at least one high-speed interconnection interface; the storage unit comprises a plurality of storage subunits, and the storage unit is connected with at least one high-speed interconnection interface; wherein the calculation unit, the memory unit and the storage unit are mutually decoupled; the number of the computing units is at least two, the at least two computing units are connected to the memory unit through the high-speed interconnection interface, and the at least two computing units are connected to the storage unit through the high-speed interconnection interface; and the at least two computing units share the memory subunit and the storage subunit.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of key interaction technology, and specifically to an interconnection system and a computer server cluster. Background Art

[0002] As the demand for computer computing units to improve business performance increases, the demand for overall memory and storage capacity is also increasing. In the prior art, the capacity of the memory unit and storage unit matching the computing unit is fixed. Although in some cases, the memory unit and storage unit can be expanded, their expandable capacity is limited due to the constraints of hardware conditions, and there is a problem of poor expansion performance. Utility Model Content

[0003] The present disclosure provides an interconnection system and a computer server cluster.

[0004] According to one aspect of the present disclosure, there is provided an interconnection system, comprising:

[0005] A computing unit, wherein the computing unit is disposed on a circuit board, and the circuit board is also provided with a plurality of high-speed interconnection interfaces;

[0006] A memory unit, the memory unit comprising a plurality of memory sub-units, the memory unit being connected to at least one of the high-speed interconnect interfaces;

[0007] A storage unit, the storage unit comprising a plurality of storage sub-units, the storage unit being connected to at least one of the high-speed interconnection interfaces;

[0008] Among them, the computing unit, the memory unit and the storage unit are decoupled from each other; the number of the computing units is at least two, at least two of the computing units are connected to the memory unit through the high-speed interconnection interface, and at least two of the computing units are connected to the storage unit through the high-speed interconnection interface; at least two of the computing units share the memory sub-unit and the storage sub-unit.

[0009] According to another aspect of the present disclosure, a computer service cluster is provided, comprising: an interconnection system as described in any embodiment of the present disclosure.

[0010] The use of the technical solution disclosed in the present invention is beneficial to improving the memory and storage expansion performance of the computing unit.

[0011] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0013] Figure 1 A schematic diagram of an interconnection system provided in an embodiment of the present disclosure;

[0014] Figure 2 for Figure 1 Detailed schematic diagram of area A in the middle;

[0015] Figure 3 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure;

[0016] Figure 4 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0017] Figure 5 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0018] Figure 6 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0019] Figure 7 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0020] Figure 8 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0021] Fig. 9 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0022] Fig.10 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0023] Fig.11 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0024] Fig.12 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0025] Fig.13 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0026] Fig.14 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0027] Fig.15 A schematic diagram of another interconnection system provided in an embodiment of the present disclosure;

[0028] Fig.16A schematic diagram of another interconnection system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0030] An embodiment of the present disclosure provides an interconnection system. Figure 1 A schematic diagram of an interconnection system provided in an embodiment of the present disclosure, Figure 2 for Figure 1 Detailed diagram of area A in the figure. Figure 1 and Figure 2 , the interconnected system includes:

[0031] Computational unit, Figure 1 exemplarily shows n computing units, namely a first computing unit 110, a second computing unit 120, ..., an nth computing unit 1n0, wherein n is a positive integer; each computing unit is arranged on a circuit board, and the circuit board is also provided with a plurality of high-speed interconnection interfaces; Figure 2 Taking the first computing unit 110 as an example, the first computing unit 110 is arranged on the circuit board 101, and the circuit board 101 is also provided with a plurality of high-speed interconnection interfaces. Exemplarily, the circuit board 101 is provided with eight high-speed interconnection interfaces, namely, a first high-speed interconnection interface 102, a second high-speed interconnection interface 103, a third high-speed interconnection interface 104, a fourth high-speed interconnection interface 105, a fifth high-speed interconnection interface 106, a sixth high-speed interconnection interface 107, a seventh high-speed interconnection interface 108 and an eighth high-speed interconnection interface 109;

[0032] Memory unit, Figure 1 and Figure 2 4 memory units are shown by way of example, namely, a first memory unit 210, a second memory unit 220, a third memory unit 230 and a fourth memory unit 240; wherein each memory unit includes a plurality of memory sub-units, and the memory unit is connected to at least one high-speed interconnect interface; taking the first memory unit 210 as an example, the first memory unit 210 includes a first memory sub-unit 211, a second memory sub-unit 212, a third memory sub-unit 213 and a fourth memory sub-unit 214, and the first memory unit 210 is connected to the first high-speed interconnect interface 102;

[0033] Storage unit 300, Figure 1 and Figure 24 storage units are exemplarily shown, namely, a first storage unit 310, a second storage unit 320, a third storage unit 330 and a fourth storage unit 340; wherein each storage unit includes a plurality of storage sub-units, and the storage unit is connected to at least one high-speed interconnection interface; taking the first storage unit 310 as an example, it includes a first storage sub-unit 311, a second storage sub-unit 312, a third storage sub-unit 313, a fourth storage sub-unit 314, a fifth storage sub-unit 315, a sixth storage sub-unit 316, a seventh storage sub-unit 317, an eighth storage sub-unit 318, a ninth storage sub-unit 319 and a tenth storage sub-unit 31A, and the first storage unit 310 is connected to the eighth high-speed interconnection interface 103;

[0034] Among them, the computing unit, the memory unit and the storage unit are decoupled from each other; the number of computing units is at least two (for example, a first computing unit 110, a second computing unit 120, ..., the nth computing unit 1n0), at least two computing units are connected to the memory unit through a high-speed interconnection interface (for example, a first memory unit 210, a second memory unit 220, a third memory unit 230 and a fourth memory unit 240), and at least two computing units are connected to the storage unit through a high-speed interconnection interface (for example, a first storage unit 310, a second storage unit 320, a third storage unit 330 and a fourth storage unit 340); at least two computing units share the use of the memory sub-unit in each memory unit and the storage sub-unit in each storage unit.

[0035] Among them, the computing unit refers to a unit that can complete a computing task by executing instructions. In some embodiments, the computing unit includes a central processing unit (CPU), which can also be called a microprocessor, etc. The memory unit is usually called a memory. Unlike a storage unit, the memory usually refers to a flash memory, which is used to temporarily store the calculation data in the computing unit. In some embodiments, the memory subunit includes a memory bar. Exemplarily, the memory bar is a dual-inline-memory-module (DIMM). The storage unit can be called an external memory relative to the memory, which is used to store the acquired data and the processing results of the computing unit, etc. In some embodiments, the storage subunit includes a hard disk. Exemplarily, the hard disk is a hard disk of the non-volatile memory host controller interface specification (Non-Volatile Memory Express, NVMe).

[0036] In some embodiments, the number of memory units is one; in other embodiments, the number of memory units is two; in still other embodiments, the number of memory units is multiple, which is not limited in the present disclosure. Figure 1 and Figure 2The number of memory cells shown in FIG. 4 is 4, which is only an exemplary representation.

[0037] In some embodiments, the number of storage units is one; in other embodiments, the number of storage units is two; in still other embodiments, the number of storage units is multiple, which is not limited in the present disclosure. Figure 1 and Figure 2 The number of storage units shown in FIG. 4 is 4, which is only an exemplary representation.

[0038] The circuit board can be a server motherboard or a motherboard designed for an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC) chip. The circuit board is not only provided with a computing unit, but also provided with a peripheral circuit of the computing unit. In the embodiment of the present disclosure, a high-speed interconnect interface is a peripheral circuit, and a high-speed interconnect interface refers to an interface that enables a computing unit to call resources of a memory unit and a storage unit. The high-speed interconnect interface can be referred to as a high-speed interconnect connector. Exemplarily, the high-speed interconnect interface includes a computing high-speed link interface (Compute Express Link, CXL). The high-speed interconnect interface is connected to the computing unit through wiring on the circuit board. It can be understood that the memory unit and the storage unit are also provided with corresponding high-speed interconnect interfaces to achieve interface matching.

[0039] The decoupling of the computing unit, the memory unit and the storage unit is relative to the related art. In the related art, the computing unit and the memory unit are arranged on a circuit board, or the computing unit, the memory unit and the storage unit are all arranged on a circuit board. Therefore, the capacity of the memory unit and the storage unit corresponding to the computing unit is usually fixed. Even if it can be expanded, the capacity expansion of the memory unit and the storage unit is limited by the size of the circuit board. The embodiment of the present disclosure decouples the computing unit, the memory unit and the storage unit from each other, which is conducive to separating the memory unit and / or the storage unit from the circuit board. Furthermore, at least two computing units share the use of the memory subunit and the storage subunit. Compared with the related art, the available capacity of the memory unit and the storage unit corresponding to a computing unit can be doubled. During the operation of the interconnected system, the capacity of the memory unit corresponding to a computing unit is flexible and adjustable, not fixed; and the capacity of the storage unit corresponding to the computing unit is flexible and adjustable, not fixed. Specifically, the capacity of the corresponding memory unit and the capacity of the storage unit can be flexibly adjusted according to the actual operation requirements of each computing unit. Furthermore, since there is no size limit on the circuit board, the capacity of the memory unit and the storage unit can be further expanded.

[0040] It can be seen that the interconnection system provided by the embodiments of the present disclosure can improve the expansion performance of the memory and storage corresponding to the computing unit, thereby helping to improve the utilization rate of large chips (for example, computing units in chip form).

[0041] Continue to see Figure 1 and Figure 2 In one embodiment, optionally, the computing unit and the memory unit are connected via a cable; the computing unit and the storage unit are connected via a cable. Preferably, the cable is a high-speed cable. Exemplarily, the cable selects a computing high-speed link interface bus, i.e., a CXL bus, and the CXL bus includes signal lines such as a receiving signal line RX[15:0], a transmitting signal line TX[15:0], a clock signal line CLOCK, and a reset signal line RESET. When a memory unit is connected to a CXL bus, since the receiving signal line and the transmitting signal line include multiple bits, multiple memory sub-units can be supported; similarly, when a storage unit is connected to a CXL bus, since the receiving signal line and the transmitting signal line include multiple bits, multiple storage sub-units can be supported.

[0042] It should be noted that the above embodiments exemplarily show a one-to-one correspondence between the memory unit and the CXL bus, which is not a limitation of the present disclosure. In other embodiments, the memory unit and the CXL bus may be set to a one-to-two or one-to-many relationship, which may be determined according to the number of memory sub-units set in the memory unit and the number of receiving signal lines and sending signal lines in the CXL bus.

[0043] Similarly, in the above embodiments, the storage unit and the CXL bus are exemplarily shown to be in a one-to-one correspondence relationship, which is not a limitation of the present disclosure. In other embodiments, the storage unit and the CXL bus can also be set to be in a one-to-two or one-to-many relationship, which can be specifically determined according to the number of storage sub-units set in the storage unit and the number of receiving signal lines and sending signal lines in the CXL bus.

[0044] The disclosed embodiments directly connect the computing unit and the memory unit through cables, and directly connect the computing unit and the storage unit through cables, so that during the data transmission process, only line loss but no other loss occurs, and the transmission delay is short, which is beneficial to improving the data transmission speed and transmission efficiency between the units; and further helps to improve the computing speed of the interconnected system.

[0045] Based on the above embodiments, the cables may optionally include copper cables and / or optical cables. In practical applications, in order to ensure consistency of data transmission of each memory unit, consistency of data transmission of each storage unit, or consistency of system design, all cables may be copper cables or all cables may be optical cables.

[0046] Based on the above embodiments, optionally, the high-speed interconnect interface (i.e., the high-speed interconnect connector) is a quad-channel small form-factor pluggable interface (Quad Small Form-factor Pluggable, QSFP), which can support copper cables or optical cables, and has higher versatility in practical applications. Specifically, a normal package type or a compact package type (QuadSmall Form Factor Pluggable-Double Density, QSFP-DD) can be selected.

[0047] It should be noted that Figure 2 It is exemplarily shown that each memory unit includes four memory sub-units, which is not a limitation of the present disclosure. In other embodiments, the number of memory sub-units in each memory unit can also be set to other numbers, for example, the number of memory sub-units in the memory unit is two, three, five, six or more. And, Figure 2 The example shows that the number of memory sub-units in each memory unit is equal, which is not a limitation of the present disclosure. In other embodiments, the number of memory sub-units in each memory unit may be unequal, or the number of memory sub-units in some memory units may be equal, while the number of memory sub-units in some memory units may be unequal.

[0048] Likewise, Figure 2 It is exemplarily shown that each storage unit includes ten storage subunits, which is not a limitation of the present disclosure. In other embodiments, the storage subunits in each storage unit can also be set to other numbers, for example, the number of storage subunits in the storage unit is two, three, five, six, seven, eight, nine, eleven, twelve or more. And, Figure 2 The example shows that the number of storage subunits in each storage unit is equal, which is not a limitation of the present disclosure. In other embodiments, the number of storage subunits in each storage unit may be unequal, or the number of storage subunits in some storage units may be equal, while the number of storage subunits in some storage units may be unequal.

[0049] Figure 3 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Figure 3 On the basis of the above embodiments, optionally, the circuit board 110 is further provided with a network interface 10A, and the network interface 10A is connected to the network through a network cable. In this way, the circuit board 110 can be connected to the network, thereby expanding the functions of the interconnected system.

[0050] In another embodiment of the present disclosure, the computing unit and the memory unit may be connected via a high-speed interconnection switch supporting a network; and / or, the computing unit and the storage unit may be connected via a high-speed interconnection switch supporting a network; and / or, at least two computing units may be connected via a high-speed interconnection switch supporting a network. Different interconnection system structures may be implemented according to different specific connection methods, and an exemplary description is given below.

[0051] Figure 4 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Figure 4 In some embodiments, the interconnection system may further include: a high-speed interconnection switch 400 supporting a network; each memory unit (e.g., the first memory unit 210, ..., the mth memory unit 2m0, where m is a positive integer) is connected to a high-speed interconnection interface corresponding to the computing unit through the high-speed interconnection switch 400 supporting a network; each storage unit (e.g., the first storage unit 310, ..., the pth memory unit 2p0, where p is a positive integer) is connected to a high-speed interconnection interface corresponding to the computing unit through the high-speed interconnection switch 400 supporting a network. Exemplarily, the high-speed interconnection switch 400 supporting a network may be a CXL switch supporting a network.

[0052] Optionally, the high-speed interconnection switch 400 supporting the network is a switch supporting Ethernet (Ethernet), a switch supporting Infiniband, or a switch supporting both Ethernet and Infiniband.

[0053] The embodiment of the present disclosure adopts a high-speed interconnection switch 400 supporting a network in the interconnection system. On the one hand, each memory unit and each storage unit does not need to be connected to each computing unit separately, and each memory unit and each storage unit can be directly connected to the high-speed interconnection switch 400 supporting a network, which is conducive to simplifying the wiring of the interconnection system; on the other hand, each computing unit can achieve two-to-two communication and networking of computing units through the high-speed interconnection switch 400 supporting a network, thereby expanding the functions of the interconnection system. Furthermore, a solution of applying a high-speed serial computer expansion bus standard (PCIE over Ethernet) on Ethernet can be realized; on the other hand, it is conducive to reducing network costs and improving network bandwidth.

[0054] In other embodiments, optionally, some memory units are connected to the high-speed interconnection interfaces corresponding to the computing units through a high-speed interconnection switch 400 supporting a network, and other memory units are directly connected to the high-speed interconnection interfaces corresponding to the computing units through cables.

[0055] In other embodiments, optionally, some storage units are connected to the high-speed interconnection interfaces corresponding to the computing units through a high-speed interconnection switch 400 that supports the network, and other storage units are directly connected to the high-speed interconnection interfaces corresponding to the computing units through cables.

[0056] Figure 5 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Figure 5 In other embodiments, optionally, at least two computing units (for example, the first computing unit 110, the second computing unit 120, ..., the nth computing unit 1n0) are connected to the high-speed interconnection switch 400 supporting the network through the high-speed interconnection interface to connect the computing units to the network. Different from the above-mentioned embodiment, in this embodiment, only each computing unit is connected to the high-speed interconnection switch 400 supporting the network. On the one hand, the computing unit is directly connected to the memory unit and the storage unit through the cable, so that the data has only line loss and no other loss during the transmission process, and the transmission delay is short, which is conducive to improving the transmission speed and transmission efficiency of the data between the units; and further helps to improve the computing speed of the interconnected system; on the other hand, each computing unit can realize two-to-two communication and networking of the computing units through the high-speed interconnection switch 400 supporting the network, which expands the function of the interconnected system. Further, it can also realize the solution of applying the high-speed serial computer expansion bus standard (PCIE over Ethernet) on Ethernet.

[0057] Based on the above embodiments, the embodiments of the present disclosure further limit the layout of each computing unit, memory unit and storage unit in the cabinet. At least one of the computing unit, memory unit and storage unit can be set in the corresponding chassis, which is exemplarily explained below.

[0058] Figure 6 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Figure 6 In some embodiments, optionally, the interconnection system further includes: at least two computing unit chassis, and at least two computing units are respectively arranged in the at least two computing unit chassis. Figure 6 The figure exemplarily shows that the interconnected system includes three computing unit chassis, namely a first computing unit chassis 610, a second computing unit chassis 620 and a third computing unit chassis 630. The first computing unit is set in the first computing unit chassis 610, the second computing unit is set in the second computing unit chassis 620, and the third computing unit is set in the third computing unit chassis 630.

[0059] Continue to see Figure 6 In some embodiments, optionally, the interconnection system further includes a memory unit chassis, and the memory unit is disposed in the memory unit chassis. Figure 6 It is exemplarily shown that the interconnection system includes a memory unit chassis, namely, a first memory unit chassis 710 , and the memory unit is arranged in the first memory unit chassis 710 .

[0060] Continue to see Figure 6 In some embodiments, optionally, the interconnection system further includes a storage unit chassis 800 , and the storage unit is disposed in the storage unit chassis 800 . Figure 6 It is exemplarily shown that the interconnection system includes a storage unit chassis, namely, a first storage unit chassis 810 , and the storage unit is arranged in the first storage unit chassis 810 .

[0061] In the related art, the computing unit, the memory unit and even the storage unit are all arranged on the same circuit board, which is usually called a server motherboard, and the circuit board is arranged in a chassis. Since the size of the circuit board and the size of the chassis are usually standard sizes in the field, their sizes are fixed, which limits the further expansion of the memory unit and the storage unit in the chassis.

[0062] The embodiment of the present disclosure decouples the computing unit, the memory unit, and the storage unit, and respectively sets the decoupled computing unit, the memory unit, and the storage unit in different chassis, so that the computing unit, the memory unit, and the storage unit can be set separately. Therefore, the expansion of the memory unit and the storage unit is not limited by the size of the circuit board and the chassis. Figure 7 As shown, in other embodiments, illustratively, when it is necessary to further expand memory and storage, a larger number of memory unit chassis and storage unit chassis can be set. Exemplarily, the interconnected system can further include a second memory unit chassis 720 and a third memory unit chassis 730, the first memory unit is arranged in the first memory unit chassis 710, the second memory unit is arranged in the second memory unit chassis 720, and the third memory unit is arranged in the third memory unit chassis 730. The interconnected system can further include a second storage unit chassis 820 and a third storage unit chassis 830, the first storage unit is arranged in the first storage unit chassis 810, the second storage unit is arranged in the second storage unit chassis 820, and the third storage unit is arranged in the third storage unit chassis 830. Therefore, the embodiment of the present disclosure improves the expansion performance of the memory and storage of the interconnected system, and the interconnected system can adapt to the business that has a demand for large memory and high-performance storage capacity.

[0063] It should be noted that, in the above-mentioned embodiments, it is exemplarily shown that the computing unit chassis and the computing units are in a one-to-one correspondence, which is not a limitation of the present disclosure. In other embodiments, the computing unit chassis and the computing units can also be set to be a one-to-two or a one-to-many relationship; and, in the above-mentioned embodiments, it is exemplarily shown that the memory unit chassis and the memory units are in a one-to-one correspondence, which is not a limitation of the present disclosure. In other embodiments, the memory unit chassis and the memory units can also be set to be a one-to-two or a one-to-many relationship; and, in the above-mentioned embodiments, it is exemplarily shown that the storage unit chassis and the storage units are in a one-to-one correspondence, which is not a limitation of the present disclosure. In other embodiments, the storage unit chassis and the storage units can also be set to be a one-to-two or a one-to-many relationship.

[0064] Continue to see Figure 6 and Figure 7 Optionally, the interconnection system further includes: a cabinet 10; a memory unit chassis (eg, Figure 6 The first memory unit in the chassis 710 or Figure 7 The first memory unit chassis 710, the second memory unit chassis 720 and the third memory unit chassis 730 in the storage unit chassis (for example, Figure 6 The first storage unit chassis 810 or Figure 7 The first storage unit chassis 810, the second storage unit chassis 820 and the third storage unit chassis 830) and at least two computing unit chassis (for example, the first computing unit chassis 610, the second computing unit chassis 620 and the third computing unit chassis 630) are dispersedly arranged in the cabinet 10. Such an arrangement is beneficial to the heat dissipation of the system compared with the related art. This is because, in the related art, the computing unit, the memory unit and even the storage unit are all arranged in the same chassis, and the computing unit is usually a device with serious heat generation, and the heat emitted by the computing unit will be transmitted to the memory unit and the storage unit, causing serious heat generation in the chassis, which is not conducive to heat dissipation. The embodiment of the present disclosure arranges the memory unit separately in the memory unit chassis, and the storage unit separately in the storage unit chassis, and the chassis are dispersedly arranged, so that the heat in the computing unit chassis is not easily transmitted to the memory unit chassis and the storage unit chassis, which is beneficial to the heat dissipation of the system.

[0065] Continue to see Figure 6In some embodiments, optionally, the computing unit chassis and the memory unit chassis are connected by cables; the computing unit chassis and the storage unit chassis are connected by cables. Exemplarily, the first computing unit chassis 610 is connected to the first memory unit chassis 710 by cables, and the first computing unit chassis 610 is connected to the first storage unit chassis 810 by cables; the second computing unit chassis 620 is connected to the first memory unit chassis 710 by cables, and the second computing unit chassis 620 is connected to the first storage unit chassis 810 by cables; the third computing unit chassis 630 is connected to the first memory unit chassis 710 by cables, and the third computing unit chassis 630 is connected to the first storage unit chassis 810 by cables. This arrangement ensures that data only has line loss but no other losses during transmission, and the transmission delay is short, which is conducive to improving the data transmission speed and transmission efficiency between units; and further helps to improve the computing speed of the interconnected system.

[0066] exist Figure 7 Although the cable connection is not shown, it can be understood that the first computing unit chassis 610 is connected to the first memory unit chassis 710 via a cable, and the first computing unit chassis 610 is connected to the first storage unit chassis 810 via a cable; the first computing unit chassis 610 is connected to the second memory unit chassis 720 via a cable, and the first computing unit chassis 610 is connected to the second storage unit chassis 820 via a cable; the first computing unit chassis 610 is connected to the third memory unit chassis 730 via a cable, and the first computing unit chassis 610 is connected to the third storage unit chassis 830 via a cable.

[0067] The second computing unit chassis 620 is connected to the first memory unit chassis 710 via cables, and the second computing unit chassis 620 is connected to the first storage unit chassis 810 via cables; the second computing unit chassis 620 is connected to the second memory unit chassis 720 via cables, and the second computing unit chassis 620 is connected to the second storage unit chassis 820 via cables; the second computing unit chassis 620 is connected to the third memory unit chassis 730 via cables, and the second computing unit chassis 620 is connected to the third storage unit chassis 830 via cables.

[0068] The third computing unit chassis 630 is connected to the first memory unit chassis 710 via cables, and the third computing unit chassis 630 is connected to the first storage unit chassis 810 via cables; the third computing unit chassis 630 is connected to the second memory unit chassis 720 via cables, and the third computing unit chassis 630 is connected to the second storage unit chassis 820 via cables; the third computing unit chassis 630 is connected to the third memory unit chassis 730 via cables, and the third computing unit chassis 630 is connected to the third storage unit chassis 830 via cables.

[0069] Figure 8 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Figure 8 In other embodiments, the cabinet 10 may further include a high-speed interconnection switch 910, and each computing unit chassis (e.g., the first computing unit chassis 610, the second computing unit chassis 620, and the third computing unit chassis 630), each memory unit chassis (e.g., the first memory unit chassis 710, the second memory unit chassis 720, and the third memory unit chassis 730), and each storage unit chassis (e.g., the first storage unit chassis 810, the second storage unit chassis 820, and the third storage unit chassis 830) are all connected to the high-speed interconnection switch 910. By using the high-speed interconnection switch 910, each memory unit chassis and each storage unit chassis do not need to be connected to each computing unit chassis respectively, and each memory unit chassis and each storage unit chassis can be directly connected to the high-speed interconnection switch 910, which is conducive to simplifying the wiring of the interconnection system.

[0070] Optionally, the high-speed interconnection switch 910 is a high-speed interconnection switch that supports the network, and specifically can be a switch that supports Ethernet, a switch that supports Infiniband, or a switch that supports both Ethernet and Infiniband. Exemplarily, the high-speed interconnection switch 910 that supports the network can be a CXL switch that supports the network. This arrangement further enables each computing unit chassis to communicate with each other through the high-speed interconnection switch that supports the network, as well as networking of the computing unit chassis, thereby expanding the functions of the interconnection system, and further, can also implement a solution for applying the high-speed serial computer expansion bus standard (PCIE over Ethernet) on Ethernet.

[0071] Fig. 9 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Fig. 9In other embodiments, optionally, each computing unit chassis (for example, the first computing unit chassis 610, the second computing unit chassis 620, and the third computing unit chassis 630) is connected to a high-speed interconnection switch 910 supporting a network through a high-speed interconnection interface to connect each computing unit chassis to a network. Different from the above-mentioned embodiment, in this embodiment, only each computing unit chassis is connected to a high-speed interconnection switch 910 supporting a network. On the one hand, the computing unit chassis is directly connected to the memory unit chassis and the storage unit chassis through a cable, so that the data has only line loss and no other loss during the transmission process, and the transmission delay is short, which is conducive to improving the data transmission speed and transmission efficiency between each unit; and further helps to improve the computing speed of the interconnected system; on the other hand, each computing unit chassis can realize two-to-two communication and networking of the computing unit chassis through the high-speed interconnection switch 910 supporting the network, which expands the function of the interconnected system. Further, it can also realize the solution of applying the high-speed serial computer expansion bus standard (PCIE over Ethernet) on Ethernet.

[0072] It should be noted that the interconnection system provided in the embodiment of the present disclosure decouples the computing unit, the memory unit and the storage unit, and the number of each unit can be flexibly set. Therefore, the embodiment of the present disclosure does not limit the number of each unit. Figure 6 and Fig. 9 As shown, illustratively, three computing unit chassis, one memory unit chassis and one storage unit chassis are set in a cabinet 10; Figure 7 and Figure 8 As shown, three computing unit chassis, three memory unit chassis and three storage unit chassis are arranged in one cabinet 10. In other embodiments, a larger number of computing unit chassis, memory unit chassis and storage unit chassis can also be arranged, and the number ratio thereof can be adjusted.

[0073] On the basis of the above embodiments, optionally, the embodiment of the present disclosure further provides a solution for interconnection across cabinets, which is exemplarily described below.

[0074] Fig.10 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Fig.10 In some embodiments, optionally, the interconnection system further comprises at least two cabinets. Fig.10 The example includes two cabinets, namely a first cabinet 11 and a second cabinet 12. The number of computing unit chassis is at least two. Fig.10Six computing unit chassis are exemplarily shown, namely, a first computing unit chassis 610, a second computing unit chassis 620, a third computing unit chassis 630, a fourth computing unit chassis 640, a fifth computing unit chassis 650 and a sixth computing unit chassis 660; the number of memory unit chassis is at least two, Fig.10 2 memory unit chassis are exemplarily shown, namely a first memory unit chassis 710 and a second memory unit chassis 720; the number of the memory unit chassis is at least two, Fig.10 Two storage unit chassis are exemplarily shown in FIG. 8 , namely a first storage unit chassis 810 and a second storage unit chassis 820 .

[0075] Among them, at least two computing unit chassis are respectively arranged in different cabinets, at least two memory unit chassis are respectively arranged in different cabinets, and at least two storage unit chassis are respectively arranged in different cabinets. Exemplarily, the first computing unit chassis 610, the second computing unit chassis 620, the third computing unit chassis 630, the first memory unit chassis 710 and the first storage unit chassis 810 are arranged in the first cabinet 11; the fourth computing unit chassis 640, the fifth computing unit chassis 650, the sixth computing unit chassis 660, the second memory unit chassis 720 and the second storage unit chassis 820 are arranged in the second cabinet 12.

[0076] In other embodiments, some cabinets may not be provided with a memory unit chassis, or some cabinets may not be provided with a storage unit chassis, etc. In actual applications, the number and ratio of various chassis in each cabinet may be flexibly set.

[0077] Continue to see Fig.10In some embodiments, optionally, at least part of the computing unit chassis is connected to the memory unit chassis across cabinets; and / or, at least part of the computing unit chassis is connected to the storage unit chassis across cabinets. Exemplarily, the first computing unit chassis 610 in the first cabinet 11 is connected across cabinets with the second memory unit chassis 720 in the second cabinet 12, and the first computing unit chassis 610 in the first cabinet 11 is connected across cabinets with the second storage unit chassis 820 in the second cabinet 12; the second computing unit chassis 620 in the first cabinet 11 is connected across cabinets with the second memory unit chassis 720 in the second cabinet 12, and the second computing unit chassis 620 in the first cabinet 11 is connected across cabinets with the second storage unit chassis 820 in the second cabinet 12; the third computing unit chassis 630 in the first cabinet 11 is connected across cabinets with the second memory unit chassis 720 in the second cabinet 12, and the third computing unit chassis 630 in the first cabinet 11 is connected across cabinets with the second storage unit chassis 820 in the second cabinet 12 The fourth computing unit chassis 640 in the second cabinet 12 is connected to the first memory unit chassis 710 in the first cabinet 11 across cabinets, and the fourth computing unit chassis 640 in the second cabinet 12 is connected to the first storage unit chassis 810 in the first cabinet 11 across cabinets; the fifth computing unit chassis 650 in the second cabinet 12 is connected to the first memory unit chassis 710 in the first cabinet 11 across cabinets, and the fifth computing unit chassis 650 in the second cabinet 12 is connected to the first storage unit chassis 810 in the first cabinet 11 across cabinets; the sixth computing unit chassis 660 in the second cabinet 12 is connected to the first memory unit chassis 710 in the first cabinet 11 across cabinets, and the sixth computing unit chassis 660 in the second cabinet 12 is connected to the first storage unit chassis 810 in the first cabinet 11 across cabinets.

[0078] With this arrangement, the interconnected system is not limited to the computing unit chassis in one cabinet sharing the memory unit chassis and the storage unit chassis; it also further enables the computing unit chassis in each cabinet to share the memory unit chassis and the storage unit chassis in other cabinets, thereby further improving the expansion performance of the memory and storage corresponding to the computing unit.

[0079] Similar to the connection between the chassis in the aforementioned embodiments, the connection between the cabinets can also be directly connected through cables or through high-speed interconnection switches.

[0080] Continue to see Fig.10 In some embodiments, optionally, the computing unit chassis and the memory unit chassis connected across cabinets are connected via cables; the computing unit chassis and the storage unit chassis connected across cabinets are connected via cables.

[0081] Fig.11 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Fig.11 In some other embodiments, optionally, the cabinet further includes a high-speed interconnect switch. Fig.11 exemplarily shows a first high-speed interconnection switch 910 located in the first cabinet 11. The computing unit chassis and the memory unit chassis connected across the cabinets are connected through the high-speed interconnection switch; the computing unit chassis and the storage unit chassis connected across the cabinets are connected through the high-speed interconnection switch. Among them, the high-speed interconnection switch can be set in one of the cabinets, for example, it can be set in the first cabinet 11, and it can also be set in the second cabinet 12. Exemplarily, the first high-speed interconnection switch 910 is set in the first cabinet 11, and the first computing unit chassis 610, the second computing unit chassis 620, the third computing unit chassis 630, the first memory unit chassis 710 and the first storage unit chassis 810 in the first cabinet 11 are all connected to the first high-speed interconnection switch 910 through cables; the fourth computing unit chassis 640, the fifth computing unit chassis 650, the sixth computing unit chassis 660, the second memory unit chassis 720 and the second storage unit chassis 820 in the second cabinet 12 are all connected to the first high-speed interconnection switch 910 through cables across the cabinets.

[0082] Fig.12 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Fig.12 In other embodiments, each cabinet optionally includes a high-speed interconnection switch. Exemplarily, the first high-speed interconnection switch 910 is arranged in the first cabinet 11, and the second high-speed interconnection switch 920 is arranged in the second cabinet 12. The first computing unit chassis 610, the second computing unit chassis 620, the third computing unit chassis 630, the first memory unit chassis 710 and the first storage unit chassis 810 in the first cabinet 11 are all connected to the first high-speed interconnection switch 910 through cables; the fourth computing unit chassis 640, the fifth computing unit chassis 650, the sixth computing unit chassis 660, the second memory unit chassis 720 and the second storage unit chassis 820 in the second cabinet 12 are all connected to the second high-speed interconnection switch 920 through cables; the first high-speed interconnection switch 910 and the second high-speed interconnection switch 920 are connected across cabinets.

[0083] On the basis of the above embodiments, optionally, the interconnected system further includes: a graphics processing unit. Among them, a graphics processing unit (GPU) refers to a unit that completes computing tasks by executing a large number of threads in parallel. In some embodiments, the graphics processing unit is specifically used for graphics processing and parallel computing, and its main function is to accelerate computing and graphics rendering operations. Compared with the CPU, the GPU has higher performance and efficiency in both parallel computing and graphics rendering. Setting a graphics processing unit in the interconnected system can further expand the business functions of the interconnected system, for example, to meet the application of artificial intelligence (AI) software.

[0084] In some embodiments, the connection method between the graphics processing unit and the computing unit can be similar to the connection method between the memory unit, the storage unit and the computing unit. Specifically, the graphics processing unit may include multiple graphics processing sub-units, and at least two computing units are connected to the graphics processing unit through a high-speed interconnect interface. Fig.13 and Fig.14 As shown, in some embodiments, exemplarily, the interconnected system includes n computing units, namely, a first computing unit 110, a second computing unit 120, ..., and an nth computing unit 1n0; and the interconnected system includes q graphics processing units, namely, a first graphics processing unit 510, ..., and a qth graphics processing unit 5q0, where n and q are positive integers. Each computing unit is connected to each graphics processing unit via a cable. exemplarily, the first computing unit 110 is connected to the first graphics processing unit 510, ..., and the qth graphics processing unit 5q0 via cables, the second computing unit 120 is connected to the first graphics processing unit 510, ..., and the qth graphics processing unit 5q0 via cables, and the nth computing unit 120 is connected to the first graphics processing unit 510, ..., and the qth graphics processing unit 5q0 via cables. Fig.15 As shown, in some other embodiments, exemplarily, each graphics processing unit (e.g., the first graphics processing unit 510, ..., the qth graphics processing unit 5q0) is connected to a high-speed interconnect switch 400 supporting a network, and each computing unit (e.g., the first computing unit 110, the second computing unit 120, ..., the nth computing unit 1n0) is connected to the graphics processing unit via the high-speed interconnect switch 400 supporting the network.

[0085] Fig.16 A schematic diagram of another interconnection system provided by an embodiment of the present disclosure. Fig.16In some other embodiments, the computing unit and the graphics processing unit are arranged on the same circuit board, and the computing unit and the graphics processing unit in the interconnected system share the memory subunit and the storage subunit. Exemplarily, the first computing unit 110 and the first graphics processing unit 510 are arranged on the same circuit board 101.

[0086] In summary, the interconnected system provided by the embodiments of the present disclosure can improve the scalability of memory and storage corresponding to the computing unit and the graphics processing unit. Therefore, the embodiments of the present disclosure can adapt to the quarterly growth rate of the parameters of the large model, as well as the requirements of the model for hardware computing power to adapt to the development of model parameters, and meet the application of AI software.

[0087] The embodiment of the present disclosure also provides a computer server cluster, which includes: an interconnection system as provided in any embodiment of the present disclosure, and has corresponding beneficial effects.

[0088] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution provided by this disclosure can be achieved, and this document does not limit this.

[0089] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An interconnection system, comprising: A computing unit, wherein the computing unit is disposed on a circuit board, and the circuit board is also provided with a plurality of high-speed interconnection interfaces; A memory unit, the memory unit comprising a plurality of memory sub-units, the memory unit being connected to at least one of the high-speed interconnect interfaces; A storage unit, the storage unit comprising a plurality of storage sub-units, the storage unit being connected to at least one of the high-speed interconnection interfaces; Among them, the computing unit, the memory unit and the storage unit are decoupled from each other; the number of the computing units is at least two, at least two of the computing units are connected to the memory unit through the high-speed interconnection interface, and at least two of the computing units are connected to the storage unit through the high-speed interconnection interface; at least two of the computing units share the memory sub-unit and the storage sub-unit.

2. The interconnection system according to claim 1, wherein: The computing unit is connected to the memory unit via a cable; And / or, the computing unit and the storage unit are connected via a cable.

3. The interconnection system according to claim 2, wherein: The cables include copper cables and / or optical cables.

4. The interconnection system according to claim 1, wherein: The circuit board is also provided with a network interface, and the network interface is connected to the network via a network cable.

5. The interconnection system according to claim 1, wherein: The interconnection system also includes: a high-speed interconnection switch supporting the network; The memory unit is connected to the high-speed interconnect interface via a high-speed interconnect switch of the supporting network; And / or, the storage unit is connected to the high-speed interconnection interface via a high-speed interconnection switch of the supporting network.

6. The interconnection system according to claim 1, wherein: The interconnection system also includes: a high-speed interconnection switch supporting the network; At least two of the computing units are connected to the high-speed interconnection switch supporting the network through the high-speed interconnection interface to network the computing units.

7. The interconnection system according to claim 5 or 6, wherein: The high-speed interconnection switch supporting the network is a switch supporting Ethernet, a switch supporting broadband network, or a switch supporting both Ethernet and broadband network.

8. The interconnection system according to claim 1, wherein: The interconnection system further comprises: at least two computing unit chassis, wherein at least two computing units are respectively arranged in the at least two computing unit chassis; And / or, the interconnection system further comprises a memory unit chassis, wherein the memory unit is arranged in the memory unit chassis; And / or, the interconnection system further includes a storage unit chassis, and the storage unit is arranged in the storage unit chassis.

9. The interconnection system according to claim 8, wherein: The interconnection system further includes: a cabinet; The memory unit chassis, the storage unit chassis and at least two computing unit chassis are dispersedly arranged in the cabinet.

10. The interconnection system according to claim 9, wherein: The computing unit chassis and the memory unit chassis are connected via cables; the computing unit chassis and the storage unit chassis are connected via cables; Alternatively, the cabinet further includes a high-speed interconnection switch, and the computing unit chassis, the memory unit chassis, and the storage unit chassis are all connected to the high-speed interconnection switch.

11. The interconnection system according to claim 9, wherein: The number of the memory unit chassis is at least two and / or the number of the storage unit chassis is at least two.

12. The interconnection system according to claim 8, wherein: The interconnection system also includes at least two cabinets; The number of the memory unit chassis is at least two, and the number of the storage unit chassis is at least two; At least two of the computing unit chassis are respectively arranged in different cabinets, at least two of the memory unit chassis are respectively arranged in different cabinets, and / or at least two of the storage unit chassis are respectively arranged in different cabinets.

13. The interconnection system according to claim 12, wherein: At least part of the computing unit chassis and the memory unit chassis are connected across cabinets; And / or, at least part of the computing unit chassis and the storage unit chassis are connected across cabinets.

14. The interconnection system according to claim 13, wherein: The computing unit chassis connected across cabinets and the memory unit chassis are connected via cables; the computing unit chassis connected across cabinets and the storage unit chassis are connected via cables; Alternatively, the cabinet further includes a high-speed interconnection switch, and the computing unit chassis and the memory unit chassis connected across the cabinets are connected via the high-speed interconnection switch; the computing unit chassis and the storage unit chassis connected across the cabinets are connected via the high-speed interconnection switch.

15. The interconnection system according to any one of claims 1-6 and 8-14, wherein: The interconnection system further comprises: a graphics processing unit, the graphics processing unit comprising a plurality of graphics processing sub-units, at least two of the computing units being connected to the graphics processing unit via the high-speed interconnection interface; And / or, the circuit board is further provided with a graphics processing unit; the computing unit and the graphics processing unit share the memory subunit and the storage subunit; And / or, the computing unit includes a central processing unit; And / or, the memory subunit includes a memory bar; And / or, the storage subunit includes a hard disk; And / or, the high-speed interconnect interface includes a computing high-speed link interface.

16. A computer server cluster, comprising: An interconnection system as claimed in any one of claims 1 to 15.

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