Level transfer circuit structure with clamping function
By introducing a clamping circuit into the level transfer circuit, the problem of failure of the level transfer function in the low-voltage domain is solved, and the level conversion function under the low-voltage power supply conditions is realized to ensure that the circuit works normally in the low-voltage domain.
Patent Information
- Application Number
- CN202420599010.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-26
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-03-26
AI Technical Summary
The existing low-level to high-level scheme fails when the voltage in the low-voltage domain is less than the threshold voltage of the high-voltage tube and cannot work normally.
A level transfer circuit structure with clamping function was designed. By introducing clamping circuits into the level transfer circuit, including PMOS and NMOS tubes in the low-voltage and high-voltage domains, as well as resistors and NMOS tubes in the clamping circuit, Ensure that the leakage voltage of the NMOS tube is within the safe range, and use medium and low threshold voltage tubes to achieve level conversion.
When the low-voltage power supply voltage is less than the high-voltage tube threshold voltage, the level shift function is successfully implemented to ensure that the circuit can work normally in the low-voltage domain.
Smart Images
Figure CN222321507U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuits, in particular to a level transfer circuit structure with a clamping function. Background Art
[0002] The existing low-level to high-level solution is to use a low-voltage domain inverter (low-voltage tube mp1, mn1) to output an inverted signal vn. Both vn and the input signal vp are square wave signals in the low-voltage domain. These two complementary signals are cross-coupled to form a load for the NMOS mn2, mn3 in the high-voltage domain and the PMOS mp2 and mp3 in the high-voltage domain. The defect is that when the voltage VDD_LV in the low-voltage domain is very low, so low that it is lower than the threshold voltage of the high-voltage tube, it is difficult for the low-end NMOS mn2 and mn3 to turn on, and the level transfer function of this structure is likely to fail and cannot work normally. Utility Model Content
[0003] 1. Technical problems to be solved by the utility model
[0004] The technical problem to be solved by the utility model is to provide a level transfer circuit structure with a clamping function, which solves the problem of failure of the level transfer function when the voltage in the low voltage domain is less than the threshold voltage of the high voltage tube.
[0005] 2. Technical solution
[0006] In order to solve the above problems, the technical solution provided by the utility model is:
[0007] A level transfer circuit structure with a clamping function comprises a level transfer circuit and a clamping circuit. The clamping circuit is connected to the level transfer circuit. The level transfer circuit comprises a low voltage domain and a high voltage domain.
[0008] Further, the low voltage domain includes a first PMOS tube and a first NMOS tube, and an input control signal VP, a low level;
[0009] The low level is connected to the source of the first PMOS tube, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, the input control signal VP is connected to the gates of the first PMOS tube and the first NMOS tube, and the drain of the first PMOS tube also outputs an output inverting signal VN.
[0010] Furthermore, the high-voltage domain includes a second PMOS tube, a third PMOS tube, a second NMOS tube, a third NMOS tube, a clamping circuit, and a first high level, and the clamping circuit is respectively connected in series between the second PMOS tube and the second NMOS tube and between the third PMOS tube and the third NMOS tube.
[0011] Furthermore, the first high level is connected to the source of the second PMOS tube and the third PMOS tube respectively, the drain of the second PMOS tube and the third PMOS tube is connected to the drain of the second NMOS tube and the third NMOS tube respectively through the clamping circuit, the drain of the second PMOS tube is connected to the gate of the third PMOS tube, the drain of the third PMOS tube is connected to the gate of the second PMOS tube, and the source of the second NMOS tube and the third NMOS tube is grounded.
[0012] Furthermore, the output inverted signal VN is connected to the gate of the second NMOS tube, and the input control signal VP is connected to the gate of the third NMOS tube.
[0013] Furthermore, the drain of the second PMOS tube and the drain of the third PMOS tube respectively output differential amplification signals.
[0014] Furthermore, the clamping circuit includes a fourth NMOS tube and a fifth NMOS tube and a second high level, a first resistor and a second resistor, the drain of the fourth NMOS tube is connected to the drain of the second PMOS tube, the source of the fourth NMOS tube is connected to the drain of the second NMOS tube, the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, and the source of the fifth NMOS tube is connected to the drain of the third NMOS tube.
[0015] Further, the second high level is connected to the first resistor, the first resistor is connected to the second resistor, the second resistor is grounded, and the first resistor is connected in parallel to the gates of the fourth NMOS tube and the fifth NMOS tube.
[0016] 3. Beneficial effects
[0017] Compared with the prior art, the technical solution provided by the utility model has the following beneficial effects:
[0018] The technical solution provided by the utility model adds a clamping function to the level transfer circuit. Through the clamping circuit, the level transfer circuit can realize the conversion of low voltage level to high voltage level. When the voltage gap between the high and low voltage domains is too large, that is, when the power supply voltage of the low voltage domain is lower than the threshold voltage of the high voltage tube in the high voltage domain, the level transfer function can also be successfully realized, which is convenient and fast. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a schematic diagram of the principle of the utility model;
[0020] Figure 2 This is a specific circuit structure diagram of the utility model. DETAILED DESCRIPTION
[0021] In order to further understand the content of the utility model, the utility model is described in detail in conjunction with the accompanying drawings and embodiments.
[0022] Combined with Figure 1-2 A level transfer circuit structure with a clamping function includes a level transfer circuit and a clamping circuit, wherein the clamping circuit is connected to the level transfer circuit, and the level transfer circuit includes a low voltage domain and a high voltage domain.
[0023] The low-voltage domain includes a first PMOS tube and a first NMOS tube, an input control signal VP, a low level, the high-voltage domain includes a second PMOS tube and a third PMOS tube and a second NMOS tube, a third NMOS tube and a clamping circuit, a first high level, the clamping circuit is respectively connected in series between the second PMOS tube and the second NMOS tube and between the third PMOS tube and the third NMOS tube, the clamping circuit includes a fourth NMOS tube and a fifth NMOS tube and a second high level, a first resistor R1 and a second resistor R2.
[0024] The low level is connected to the source of the first PMOS tube, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, and the input control signal VP is connected to the gates of the first PMOS tube and the first NMOS tube.
[0025] The first high level is connected to the source of the second PMOS tube and the third PMOS tube respectively, the drain of the second PMOS tube and the third PMOS tube is connected to the drain of the second NMOS tube and the third NMOS tube respectively through the clamping circuit, the drain of the second PMOS tube is connected to the gate of the third PMOS tube, the drain of the third PMOS tube is connected to the gate of the second PMOS tube, and the source of the second NMOS tube and the third NMOS tube is grounded.
[0026] The drain output inverting signal VN of the first PMOS tube is connected to the gate of the second NMOS tube, and the input control signal VP is connected to the gate of the third NMOS tube.
[0027] The drain of the second PMOS tube and the drain of the third PMOS tube output differential amplification signals VOUTP and VOUTN respectively.
[0028] The drain of the fourth NMOS tube is connected to the drain of the second PMOS tube, the source of the fourth NMOS tube is connected to the drain of the second NMOS tube, the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, and the source of the fifth NMOS tube is connected to the drain of the third NMOS tube.
[0029] The second high level is connected to the first resistor R1, the first resistor R1 is connected to the second resistor R2, the second resistor R2 is grounded, and the first resistor R1 is connected in parallel to the gates of the fourth NMOS transistor and the fifth NMOS transistor.
[0030] The circuit principle is: in the load that converts low level to high level, in addition to the original PMOS cross-coupling pair, a clamping circuit is added. The clamping circuit can protect the leakage voltage of the bottom NMOS tube within a certain safety range, so that the low-end NMOS can use a tube with a lower threshold voltage and a lower voltage resistance, so that the low-voltage domain signal can turn on the NMOS (because the voltage of the low-voltage domain is greater than the threshold voltage of the low-end NMOS), thereby realizing normal function.
[0031] Note: The function of the clamp circuit is to limit the drain voltage of the NMOS tubes (the second NMOS tube and the third NMOS tube) to a low voltage range, so that these two low-end NMOS tubes can use tubes with medium and low threshold voltages. Therefore, VDD_LV can be greater than their threshold voltages, turning them on, and thus realizing the function of level conversion.
[0032] The clamping circuit is composed of resistors R1, R2, and the fourth NMOS tube and the fifth NMOS tube;
[0033] The clamping principle is as follows: resistor voltage division, point a voltage = VDD_HV·R2 / (R2+R1); point a voltage provides gate voltage to nmos (the fourth NMOS tube and the fifth NMOS tube). Since the drain voltage of the low-end tubes, the second NMOS tube and the third NMOS tube, will not exceed the value of the voltage at point a minus a threshold voltage of the fourth NMOS tube / the fifth NMOS tube, the second NMOS tube and the third NMOS tube can use medium and low voltage tubes, and the threshold voltage of these tubes is lower than that of high-voltage tubes. In this way, the low level VDD_LV of vn, vp can be higher than the threshold voltage of the second NMOS tube and the third NMOS tube, which can turn on the second NMOS tube and the third NMOS tube, thereby achieving successful level conversion.
[0034] The above schematically describes the present invention and its implementation methods, which are not restrictive. The drawings show only one implementation method of the present invention, and the actual structure is not limited thereto. Therefore, if ordinary technicians in this field are inspired by it and design structural methods and embodiments similar to the technical solution without creativity without departing from the purpose of the present invention, they should all fall within the protection scope of the present invention.
Claims
1. A level shifting circuit structure with a clamping function, characterized in that: It includes a level transfer circuit and a clamp circuit, wherein the clamp circuit is connected to the level transfer circuit, and the level transfer circuit includes a low voltage domain and a high voltage domain; The low voltage domain includes a first PMOS tube and a first NMOS tube, and an input control signal VP, a low level; The low level is connected to the source of the first PMOS tube, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, the input control signal VP is connected to the gates of the first PMOS tube and the first NMOS tube, and the drain of the first PMOS tube also outputs an output inverting signal VN; The high-voltage domain includes a second PMOS tube, a third PMOS tube, a second NMOS tube, a third NMOS tube, a clamping circuit, and a first high level. The clamping circuit is respectively connected in series between the second PMOS tube and the second NMOS tube and between the third PMOS tube and the third NMOS tube.
2. The level shifting circuit structure with clamping function according to claim 1, characterized in that: The first high level is connected to the source of the second PMOS tube and the third PMOS tube respectively, the drain of the second PMOS tube and the third PMOS tube is connected to the drain of the second NMOS tube and the third NMOS tube respectively through the clamping circuit, the drain of the second PMOS tube is connected to the gate of the third PMOS tube, the drain of the third PMOS tube is connected to the gate of the second PMOS tube, and the source of the second NMOS tube and the third NMOS tube is grounded.
3. The level shifting circuit structure with clamping function according to claim 1, characterized in that: The output inverted signal VN is connected to the gate of the second NMOS tube, and the input control signal VP is connected to the gate of the third NMOS tube.
4. The level shifting circuit structure with clamping function according to claim 1, characterized in that: The drain of the second PMOS tube and the drain of the third PMOS tube respectively output differential amplification signals.
5. The level shifting circuit structure with clamping function according to claim 3, characterized in that: The clamping circuit includes a fourth NMOS tube and a fifth NMOS tube and a second high level, a first resistor and a second resistor, the drain of the fourth NMOS tube is connected to the drain of the second PMOS tube, the source of the fourth NMOS tube is connected to the drain of the second NMOS tube, the drain of the fifth NMOS tube is connected to the drain of the third PMOS tube, and the source of the fifth NMOS tube is connected to the drain of the third NMOS tube.
6. The level shifting circuit structure with clamping function according to claim 5, characterized in that: The second high level is connected to the first resistor, the first resistor is connected to the second resistor, the second resistor is grounded, and the first resistor is connected in parallel to the gates of the fourth NMOS tube and the fifth NMOS tube.