Bidirectional anti-backflow circuit, protection chip and adapter plate

Abstract

The utility model provides a bidirectional anti-backflow circuit, a protection chip and an adapter plate. The bidirectional anti-backflow circuit comprises at least one anti-backflow module, each anti-backflow module comprises two anti-backflow branches with the same circuit structure, and each anti-backflow branch comprises a first control circuit, an isolation circuit, an IO circuit and a second control circuit. Wherein the first end of the first control circuit of one anti-backflow branch is coupled with the first end of the second control circuit of the other anti-backflow branch to form a first IO node, and the first end of the second control circuit of the anti-backflow branch is coupled with the first end of the first control circuit of the other anti-backflow branch to form a second IO node; wherein the control end of the first control circuit and the control end of the second control circuit of one anti-backflow branch are both coupled with a first driving signal, and the control end of the first control circuit and the control end of the second control circuit of the other anti-backflow branch are both coupled with a second driving signal. According to the utility model, bidirectional transmission and isolation protection between chips can be realized with low cost.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit design, in particular to a bidirectional anti-backflow circuit, a protection chip and a switching board. Background Art

[0002] With the continuous advancement and improvement of science and technology, the core voltage and output voltage of the FPGA (field programmable logic array) used to establish the chip model are getting lower and lower (for example, as low as 1.8V), and the rate is getting higher and higher. The output IO level of the MCU (microcontroller) used in the relevant technology is usually 3.3V or 5V. Therefore, when verifying the chip model, the FPGA development board + adapter board is usually used to verify its function. Since the output IO level of the FPGA development board is different from the output IO level of the functional sub-board, an adapter board with a level conversion chip is required to convert the output IO level of the FPGA development board to the output IO level of the MCU (for example, converting 1.8V to 3.3V). The output IO level of the MCU is input-output type, so the level conversion chip on the adapter board is required to be a bidirectional level conversion chip.

[0003] The bidirectional level conversion chip in the related technology usually does not have the anti-backflow isolation function. However, during the functional verification operation using the test verification system, if the MCU side (3.3V) is accidentally touched, the output IO level of the MCU will flow back into the output IO of the FPGA development board, which may burn the power supply of the FPGA development board at the least, or even cause the FPGA development board to short-circuit or even damage in serious cases. FPGA development boards are usually expensive, so this will not only cause unnecessary waste of resources, but also increase the manpower and material costs of rebuilding the test verification system.

[0004] It should be noted that the information disclosed in the background technology section of the utility model is only intended to deepen the understanding of the general background technology of the utility model, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Utility Model Content

[0005] The main purpose of the utility model is to provide a bidirectional anti-backflow circuit and a transfer board to address the technical problem that the bidirectional level conversion chip in the prior art does not have an isolation function and is prone to IO level backflow and chip damage. The bidirectional anti-backflow circuit provided by the utility model can realize bidirectional transmission and isolation protection between chips at a relatively low cost. It can not only effectively prevent IO level backflow without affecting IO transmission, but also has a simple circuit structure and is easy to implement.

[0006] To achieve the above object, the utility model is implemented by the following technical solutions: a bidirectional anti-backflow circuit, the bidirectional anti-backflow circuit includes at least one anti-backflow module, the anti-backflow module includes two anti-backflow branches with the same circuit structure and opposite anti-backflow directions, each of the anti-backflow branches includes a first control circuit, an isolation circuit, an IO circuit and a second control circuit coupled in sequence;

[0007] The two anti-backflow branches are respectively a first direction anti-backflow branch and a second direction anti-backflow branch, and the first end of the first control circuit of the first direction anti-backflow branch is coupled to the first end of the second control circuit of the second direction anti-backflow branch to form a first IO node, and the first IO node is configured to couple a first signal level; the first end of the second control circuit of the first direction anti-backflow branch is coupled to the first end of the first control circuit of the second direction anti-backflow branch to form a second IO node, and the second IO node is configured to couple a second signal level; the control end of the first control circuit of the first direction anti-backflow branch and the control end of the second control circuit are both configured to couple a first drive signal, and the control end of the first control circuit of the second direction anti-backflow branch and the control end of the second control circuit are both configured to couple a second drive signal;

[0008] The bidirectional anti-backflow circuit is configured such that when the first signal level is transmitted from the first IO node to the second IO node, the first drive signal controls the first direction anti-backflow branch to be turned on and the second drive signal controls the second direction anti-backflow branch to be turned off; and when the second signal level is transmitted from the second IO node to the first IO node, the second drive signal controls the second direction anti-backflow branch to be turned on and the first drive signal controls the first direction anti-backflow branch to be turned off.

[0009] Optionally, the first IO node is further configured to be coupled to a first power supply voltage; and the second IO node is further configured to be coupled to a second power supply voltage.

[0010] Optionally, the first control circuit includes a first MOS transistor, a gate terminal of the first MOS transistor of the first direction anti-backflow branch is configured to couple the first drive signal, and a gate terminal of the first MOS transistor of the second direction anti-backflow branch is configured to couple the second drive signal;

[0011] And / or the second control circuit includes a second MOS tube, the gate end of the second MOS tube of the first direction anti-backflow branch is configured to couple the first drive signal, and the gate end of the second MOS tube of the second direction anti-backflow branch is configured to couple the second drive signal.

[0012] Optionally, the isolation circuit includes a first operational amplifier, an isolation device, and a second operational amplifier; a power pin of the first operational amplifier of the first direction anti-backflow branch and a power pin of the second operational amplifier of the second direction anti-backflow branch are configured to be connected to a first power supply voltage, and a power pin of the second operational amplifier of the first direction anti-backflow branch and a power pin of the first operational amplifier of the second direction anti-backflow branch are configured to be connected to the second power supply voltage;

[0013] One of the input terminals of the first operational amplifier is coupled to the second terminal of the first control circuit, the other input terminal of the first operational amplifier is grounded, the output terminal of the first operational amplifier is coupled to the first terminal of the isolation device, the second terminal of the isolation device is coupled to one of the input terminals of the second operational amplifier, the other input terminal of the second operational amplifier is grounded, and the output terminal of the second operational amplifier is coupled to the first terminal of the IO circuit.

[0014] Optionally, the isolation device includes an optocoupler isolation device or an electromagnetic isolation device.

[0015] Optionally, the IO circuit includes a push-pull pair of transistors including a third MOS transistor and a fourth MOS transistor; a gate end of the third MOS transistor and a gate end of the fourth MOS transistor are connected together to form a first end of the IO circuit and coupled to the isolation circuit, a first end of the third MOS transistor of the first direction anti-backflow branch is configured to couple to a second power supply voltage, and a first end of the third MOS transistor of the second direction anti-backflow branch is configured to couple to a first power supply voltage; a second end of the third MOS transistor and a first end of the fourth MOS transistor are connected together to couple to a first end of the second control circuit, and a second end of the fourth MOS transistor is grounded.

[0016] Optionally, the bidirectional anti-backflow circuit is used for a verification test system, which includes a first chip, an adapter board and a second chip; the bidirectional anti-backflow circuit is arranged on the adapter board, the first IO node of the bidirectional anti-backflow circuit is configured to couple the first signal level of the first chip, and the second IO node of the bidirectional anti-backflow circuit is configured to couple the second signal level of the second chip; the third end of the first direction anti-backflow branch is configured to couple the first drive signal of the verification test system; the third end of the second direction anti-backflow branch is configured to couple the second drive signal of the verification test system.

[0017] Optionally, the bidirectional anti-backflow circuit further includes a level conversion circuit, a first end of the level conversion circuit is configured to be coupled to the first chip to access the first signal level, and a second end of the level conversion circuit is coupled to the first IO node.

[0018] Optionally, the IO circuit further includes a third MOS transistor and a fourth MOS transistor coupled in an open-drain form.

[0019] In order to achieve the above object, the utility model further provides a protection chip, wherein the protection chip integrates any of the above-mentioned bidirectional anti-backflow circuits.

[0020] In order to achieve the above-mentioned purpose, the utility model further provides an adapter board, on which the bidirectional anti-backflow circuit as described in any one of the above items or the above-mentioned protection chip is arranged.

[0021] Compared with the prior art, the bidirectional anti-backflow circuit, protection chip and adapter board provided by the utility model have the following beneficial effects:

[0022] The bidirectional anti-backflow circuit provided by the utility model includes at least one anti-backflow module, each of which includes two anti-backflow branches with the same circuit structure and opposite anti-backflow directions, and each of the anti-backflow branches includes a first control circuit, an isolation circuit, an IO circuit and a second control circuit coupled in sequence. The two anti-backflow branches are respectively a first direction anti-backflow branch and a second direction anti-backflow branch, and when the first signal level is transmitted from the first IO node to the second IO node, the first drive signal controls the first direction anti-backflow branch to be turned on and the second drive signal controls the second direction anti-backflow branch to be disconnected, thereby preventing the second signal level from the second IO node to the first IO node from backflowing; and when the second signal level is transmitted from the second IO node to the first IO node, the second drive signal controls the second direction anti-backflow branch to be turned on and the first drive signal controls the first direction anti-backflow branch to be disconnected, thereby preventing the first signal level from the first IO node to the second IO node from backflowing. With such a configuration, the bidirectional anti-backflow circuit provided by the utility model realizes bidirectional transmission and isolation protection between chips without affecting IO transmission. It can not only effectively prevent IO level backflow without affecting IO transmission, thereby realizing isolation protection between chips, but also has a simple circuit structure and is easy to implement.

[0023] Since the protection chip and adapter board provided by the utility model belong to the same inventive concept as the bidirectional anti-backflow circuit provided by the utility model, the protection chip and adapter board provided by the utility model at least have all the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model. For details, please refer to the relevant description of the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model in the above text. Therefore, the beneficial effects of the protection chip and adapter board provided by the utility model will not be described one by one here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic structural diagram of an anti-backflow module of a bidirectional anti-backflow circuit provided in a first embodiment of the utility model;

[0025] Figure 2 A circuit diagram of a specific example of an anti-backflow module of a bidirectional anti-backflow circuit provided in the first embodiment of the utility model;

[0026] Figure 3 A schematic diagram of one application scenario of a bidirectional anti-backflow circuit provided in the first embodiment of the utility model;

[0027] The reference numerals are described as follows:

[0028] Anti-backflow module-100, level conversion circuit-200;

[0029] First control circuit-111, 112; isolation circuit-121, 122; IO circuit-131, 132; second control circuit-141, 142;

[0030] First MOS tube-Q11, Q12; second MOS tube-Q21, Q22; third MOS tube-Q31, Q32; fourth MOS tube-Q41, Q42;

[0031] First operational amplifier-U11, U12; isolation devices-1211, 1221; second operational amplifier-U21, U22;

[0032] Optocoupler transmitting tube-T11, T12; Optocoupler receiving tube-R11, R12;

[0033] First direction backflow prevention branch-B1, second direction backflow prevention branch-B2, level conversion circuit-LS;

[0034] First chip 310, second chip 320, adapter board 400;

[0035] First IO node-P1, second IO node-P2;

[0036] First signal level -VI1, second signal level -VO1, first drive signal -C1, second drive signal C2;

[0037] First power supply voltage-VCC1, second power supply voltage-VCC2, resistors-R1, R2. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and features of the utility model clearer, the bidirectional anti-backflow circuit, protection chip and adapter board proposed in the utility model are further described in detail in conjunction with the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiment of the utility model. It should be understood that the drawings in the specification do not necessarily show the specific structure of the utility model in proportion, and the illustrative features used to illustrate certain principles of the utility model in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the utility model disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. Where appropriate, these terms used in this way are interchangeable.

[0039] It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements.

[0040] The core idea of ​​the utility model is to provide a bidirectional anti-backflow circuit and a transfer board at a relatively low cost. The bidirectional anti-backflow circuit provided by the utility model can realize bidirectional transmission and isolation protection between chips at a relatively low cost. It can not only effectively prevent IO level backflow without affecting IO transmission, but also has a simple circuit structure and is easy to implement.

[0041] In order to realize the above core idea, the first embodiment of the present utility model provides a bidirectional anti-backflow circuit, and the bidirectional anti-backflow circuit includes at least one anti-backflow module. For example, see Figure 1 and Figure 2 ,in, Figure 1 A schematic structural diagram of an anti-backflow module of a bidirectional anti-backflow circuit provided in a first embodiment of the utility model; Figure 2 A circuit diagram of a specific example of an anti-backflow module of a bidirectional anti-backflow circuit provided in the first embodiment of the utility model. Figure 1 and Figure 2It can be seen that the anti-backflow module includes two anti-backflow branches with the same circuit structure and opposite anti-backflow directions, and each of the anti-backflow branches includes a first control circuit, an isolation circuit, an IO circuit and a second control circuit coupled in sequence. Furthermore, the two anti-backflow branches are respectively a first direction anti-backflow branch B1 and a second direction anti-backflow branch B2, and a first end (not shown in the figure) of the first control circuit 111 of the first direction anti-backflow branch B1 and a first end (not shown in the figure) of the second control circuit 142 of the second direction anti-backflow branch B2 are coupled to form a first IO node P1, and the first IO node P1 is configured to couple a first signal level VI1; a first end of the second control circuit 141 of the first direction anti-backflow branch B1 and a first end of the first control circuit 112 of the second direction anti-backflow branch B2 are coupled to form a second IO node P2, and the second IO node P2 is configured to couple a second signal level VO1; a control end of the first control circuit 111 of the first direction anti-backflow branch B1 and a control end of the second control circuit 141 are both configured to couple a first drive signal C1, and a control end of the first control circuit 112 of the second direction anti-backflow branch B2 and a control end of the second control circuit 142 are both configured to couple a second drive signal C2. Furthermore, the bidirectional backflow prevention circuit is configured such that when the first signal level VI1 is transmitted from the first IO node P1 to the second IO node P2, the first drive signal C1 controls the first direction backflow prevention branch B1 to be turned on and the second drive signal C2 controls the second direction backflow prevention branch B2 to be turned off; and when the second signal level VO1 is transmitted from the second IO node P2 to the first IO node P1, the second drive signal C2 controls the second direction backflow prevention branch B2 to be turned on and the first drive signal C1 controls the first direction backflow prevention branch B1 to be turned off.

[0042] It can be seen that the bidirectional anti-backflow circuit provided by the utility model includes at least one anti-backflow module 100, each anti-backflow module 100 includes two anti-backflow branches with the same circuit structure and opposite anti-backflow directions, and when the first signal level VI1 is transmitted from the first IO node P1 to the second IO node P2, the first drive signal C1 controls the first direction anti-backflow branch B1 to be turned on and the second drive signal C2 controls the second direction anti-backflow branch B2 to be disconnected, thereby preventing the second signal level VO1 from being backflowed from the second IO node P2 to the first IO node P1; and when the second signal level VO1 is transmitted from the second IO node P2 to the first IO node P1, the second drive signal C2 controls the second direction anti-backflow branch B2 to be turned on and the first drive signal C1 controls the first direction anti-backflow branch B1 to be disconnected, thereby preventing the first signal level VI1 from being backflowed from the first IO node P1 to the second IO node P2. With such a configuration, the utility model realizes bidirectional transmission and isolation protection between chips without affecting IO transmission. It can not only effectively prevent IO level backflow without affecting IO transmission, thereby realizing isolation protection between chips, but also has a simple circuit structure and is easy to implement.

[0043] It should be noted that, as can be understood by those skilled in the art, the bidirectional anti-backflow circuit provided by the present invention does not limit the specific number of anti-backflow modules 100. When the bidirectional anti-backflow circuit provided by the present invention is specifically implemented, the bidirectional anti-backflow circuit may include 1 anti-backflow module 100, and the bidirectional anti-backflow circuit may include 2 anti-backflow modules 100, 3 anti-backflow modules 100 or more anti-backflow modules 100. Further, according to the description herein, it is not difficult for those skilled in the art to understand that each anti-backflow module 100 of the bidirectional anti-backflow circuit provided by the present invention corresponds to a pair of IO interfaces for IO signal level interaction. If there are multiple pairs of IO interfaces that need anti-backflow isolation, the number of anti-backflow modules 100 can be reasonably set according to the number of IO interfaces that need IO signal interaction. Further, according to the description above, it is not difficult for those skilled in the art to understand that for a bidirectional anti-backflow circuit having multiple anti-backflow modules 100, the multiple anti-backflow modules 100 are independent of each other.

[0044] In order to make it easier to understand the present invention, before further describing the bidirectional anti-backflow circuit provided by the present invention, the application scenario of the bidirectional anti-backflow circuit provided by the present invention is described. For example, the bidirectional anti-backflow circuit is used to verify the test system. For details, see Figure 3 , Figure 3A schematic diagram of one application scenario of a bidirectional anti-backflow circuit provided for the first embodiment of the utility model. The verification test system includes a first chip 310, an adapter board 400, and a second chip 320; the bidirectional anti-backflow circuit is arranged on the adapter board 400, the first IO node P1 of the bidirectional anti-backflow circuit is configured to couple the first signal level VI1 of the first chip 310, and the second IO node P2 of the bidirectional anti-backflow circuit is configured to couple the second signal level VO1 of the second chip 320; the third end of the first direction anti-backflow branch B1 is configured to couple the first drive signal C1 of the verification test system; the third end of the second direction anti-backflow branch B2 is configured to couple the second drive signal C2 of the verification test system.

[0045] It can be seen that by coupling the first IO node P1 of the bidirectional anti-backflow circuit provided by the utility model to the first signal level VI1 of the first chip 310, and the second IO node P2 to the second signal level VO1 of the second chip 320; and the third end of the first direction anti-backflow branch B1 is coupled to the first drive signal C1 of the verification test system, and the third end of the second direction anti-backflow branch B2 is coupled to the second drive signal C2 of the verification test system, not only can the bidirectional transmission of the level signal between the first chip 310 and the second chip 320 be realized, but also backflow can be avoided when the first chip 310 and the second chip 320 transmit the level signal, thereby realizing isolation protection between the first chip 310 and the second chip 320, and avoiding short circuit or damage of the first chip 310 or the second chip 320 caused by level backflow, thereby laying a solid foundation for improving the safety and service life of the verification test system.

[0046] According to the description herein, it can be known that the IO signal levels of the first chip 310 and the second chip 320 that are isolated and protected by the bidirectional anti-backflow circuit provided by the utility model are different. For example, in some embodiments, the IO signal level of the first chip 310 (i.e., the first signal level VI1) can be higher than the IO signal level of the second chip 320 (i.e., the second signal level VO1); in other embodiments, the IO signal level of the first chip 310 can be lower than the IO signal level of the second chip 320. Furthermore, the bidirectional anti-backflow circuit provided by the utility model does not limit the specific values ​​of the IO signal level of the first chip 310 and the IO signal level of the second chip 320.

[0047] In addition, it should be noted that, as those skilled in the art can understand, although this article uses the transmission of IO signal levels in a verification test system as an example to illustrate the bidirectional anti-backflow circuit provided by the utility model, it should be understood that the utility model does not limit the specific application scenarios of the bidirectional anti-backflow circuit. For example, the bidirectional anti-backflow circuit provided by the utility model can also be used to prevent the backflow of power supply signals. Furthermore, the utility model does not impose any limitations on the first chip 310 and the second chip 320 of the verification test system. For example, in one exemplary embodiment, the first chip 310 can be an FPGA development board, and the second chip 320 can be a functional sub-board. Furthermore, the present invention does not limit the specific uses of the first chip 310 and the second chip 320. For example, the first chip 310 and / or the second chip 320 can be used in, including but not limited to, video products such as televisions, video recorders and digital cameras, communication products such as mobile phones, communication switching equipment and communication transmission equipment, learning assistance products such as translators, learning machines and electronic dictionaries, and medical equipment products such as medical imaging equipment and medical testing equipment.

[0048] Please continue to see Figure 3 Exemplarily, the bidirectional anti-backflow circuit further includes a level conversion circuit LS, a first end of the level conversion circuit LS is configured to couple the first chip 310 to access the first signal level VI1, and a second end of the level conversion circuit LS is coupled to the first IO node P1. Thus, by setting the level conversion circuit LS, the applicability of the bidirectional anti-backflow circuit provided by the utility model can be further improved.

[0049] Please continue to see Figure 2 ,from Figure 2 It can be seen that in some preferred implementations, the first IO node P1 is also configured to couple the first power supply voltage VCC1; the second IO node P2 is also configured to couple the second power supply voltage VCC2. It can be seen that the utility model further improves the safety and applicability of the bidirectional anti-backflow circuit provided by the utility model by adopting the design mode of coupling the first IO node P1 to the first power supply voltage VCC1 and coupling the second IO node P2 to the second power supply voltage VCC2.

[0050] It should be noted that, as those skilled in the art can understand, the present invention does not limit the specific values ​​of the first power supply voltage VCC1 and the second power supply voltage VCC2. Preferably, the values ​​of the first power supply voltage VCC1 and the second power supply voltage VCC2 are the same.

[0051] For example, please see Figure 3 ,like Figure 3 As shown, the first chip 310 (such as an FPGA development board) outputs a 1.8V signal which is first converted into a 3.3V (or 5V) level signal by a level conversion circuit LS. The signal is connected to the left side of the bidirectional anti-backflow circuit (the direction shown in the figure, the power supply of the FPGA development board can be used), and the right side of the bidirectional anti-backflow circuit (the direction shown in the figure, an independent power supply can be used to provide the first power supply voltage VCC1 and the second power supply voltage VCC2) is connected to the second chip 320 (such as a functional sub-board that needs to be verified).

[0052] Furthermore, in one exemplary embodiment, the anti-backflow branch also includes a current limiting resistor. Specifically, the first end of the second control circuit 141 of the first direction anti-backflow branch B1 is connected in series with the resistor R2 and is configured to be connected to the first power supply voltage VCC1; the first end of the second control circuit 142 of the second direction anti-backflow branch B2 is connected in series with the resistor R2 and is configured to be connected to the second power supply voltage VCC2. Thus, by setting the current limiting resistor, the current can be stabilized, thereby preventing the first direction anti-backflow branch B1 and the other components of the second direction anti-backflow branch B2 from being damaged due to excessive current, thereby improving the service life of the bidirectional anti-backflow circuit provided by the utility model.

[0053] As mentioned above, since the circuit structures of the two anti-backflow branches in opposite directions of the anti-backflow module are the same, for the sake of ease of understanding and description, unless otherwise specified, the following text uses the first control circuit 111, isolation circuit 121, IO circuit 131 and second control circuit 141 of the first direction anti-backflow branch B1 as examples to illustrate the circuit structure of the anti-backflow branch.

[0054] Please continue to see Figure 2 ,like Figure 2As shown, in some preferred embodiments, the first control circuit includes a first MOS tube, the gate end of the first MOS tube Q11 of the first direction anti-backflow branch B1 is configured to couple the first drive signal C1, and the gate end of the first MOS tube Q12 of the second direction anti-backflow branch B2 is configured to couple the second drive signal C2. Further, the second control circuit includes a second MOS tube, the gate end of the second MOS tube Q21 of the first direction anti-backflow branch B1 is configured to couple the first drive signal C1, and the gate end of the second MOS tube Q22 of the second direction anti-backflow branch B2 is configured to couple the second drive signal C2. Therefore, the bidirectional anti-backflow circuit provided by the utility model, by using the first MOS tube to implement the first control circuit and the second MOS tube to implement the second control circuit, improves the response speed of the bidirectional anti-backflow circuit provided by the utility model based on the fast response performance of the MOS tube; further, the MOS tube is easy to obtain and low in price, therefore, the bidirectional anti-backflow circuit provided by the utility model is easy to implement and has low cost. Furthermore, the design method in which the first control circuit adopts the first MOS tube and the second control circuit adopts the second MOS tube will not change the impedance of the IO port of the first chip 310 coupled to the first IO node P1 and the IO port of the second chip 320 coupled to the second IO node P2, thereby further improving the protection effect of the first chip 310 and the second chip 320.

[0055] Exemplarily, when the first signal level VI1 is transmitted from the first IO node P1 to the second IO node P2, the first MOS transistor Q11 and the second MOS transistor Q22 of the first direction anti-backflow branch B1 can be controlled to be turned on by the first drive signal C1, and the first MOS transistor Q12 and the second MOS transistor Q22 of the second direction anti-backflow branch B2 can be controlled to be turned off by the second drive signal C2, so as to prevent the second signal level VO1 from backflowing from the second IO node P2 to the first IO node P1, thereby achieving the effect of isolating and protecting the chip coupled to the first IO node P1.

[0056] It should be noted that those skilled in the art should be able to understand that although this article uses the first MOS tube as the first control circuit and the second MOS tube as the second control circuit to illustrate the bidirectional anti-backflow circuit provided by the utility model, it is not a limitation of the utility model, and the utility model does not limit the specific implementation method of the first control circuit and the second control circuit. When implementing the bidirectional anti-backflow circuit provided by the utility model, other types of switching devices other than MOS tubes can also be used to implement the first control circuit and / or the second control circuit. For a more detailed description of the switching devices, please refer to the relevant technologies known to those skilled in the art for understanding, and they are not listed one by one here.

[0057] Please continue to see Figure 2 ,like Figure 2 As shown, in some preferred embodiments, the isolation circuit includes a first operational amplifier, an isolation device, and a second operational amplifier. The power pin of the first operational amplifier U11 of the first direction anti-backflow branch B1 and the power pin of the second operational amplifier U22 of the second direction anti-backflow branch B2 are configured to be connected to the first power supply voltage VCC1, and the power pin of the second operational amplifier U21 of the first direction anti-backflow branch B1 and the power pin of the first operational amplifier U12 of the second direction anti-backflow branch B2 are configured to be connected to the second power supply voltage VCC2. Taking the isolation circuit 121 of the first direction anti-backflow branch B1 as an example, one of the input terminals of the first operational amplifier U11 is coupled to the second terminal of the first control circuit 111, the other input terminal of the first operational amplifier U11 is grounded, the output terminal of the first operational amplifier U11 is coupled to the first terminal of the isolation device 1211, the second terminal of the isolation device 1211 is coupled to one of the input terminals of the second operational amplifier U21, the other input terminal of the second operational amplifier U21 is grounded, and the output terminal of the second operational amplifier U21 is coupled to the first terminal of the IO circuit 131.

[0058] Configured in this way, the isolation circuit of the bidirectional anti-backflow circuit provided by the utility model only adopts the design method of the first operational amplifier, the isolation device and the second operational amplifier, which not only facilitates the effective transmission of the IO signal level and the unidirectional isolation; the isolation circuit adopts the design method of the first operational amplifier, the isolation device and the second operational amplifier, and the logic is clear and the circuit structure is simple, and the operational amplifier and the isolation device are inexpensive and easy to obtain.

[0059] For example, Figure 2 As shown, still taking the isolation circuit 121 of the first direction anti-backflow branch B1 as an example, the non-inverting input terminal of the first operational amplifier U11 of the first direction anti-backflow branch B1 is coupled to the second terminal of the first control circuit 111, the inverting input terminal of the first operational amplifier U11 is grounded, the output terminal of the first operational amplifier U11 is coupled to the first terminal of the isolation device 1211, the second terminal of the isolation device 1211 is coupled to the non-inverting input terminal of the second operational amplifier U21, and the inverting input terminal of the second operational amplifier U21 is grounded.

[0060] It should be noted that, as can be understood by those skilled in the art, the design of the isolation circuit described herein using the first operational amplifier, the isolation device, and the second operational amplifier is only an exemplary description, and is not a limitation of the present invention. For example, in some other embodiments, the isolation circuit may also use the design of the first comparator, the isolation device, and the second comparator. For more detailed information about the operational amplifier and the comparator, please refer to the related technology known to those skilled in the art. Due to space limitations, this article will not elaborate on the working principles of the operational amplifier and the comparator.

[0061] Furthermore, the bidirectional anti-backflow circuit provided by the utility model does not limit the isolation device. Exemplarily, the isolation device can be, but is not limited to, an optocoupler isolation device and an electromagnetic isolation device. Preferably, the isolation device is an optocoupler device. Using an optocoupler device as an isolation device can not only prevent signal interference and noise transmission, improve the safety of the circuit, and prevent electrical shocks and voltage surges between circuits; it can also improve the performance of the circuit, improve the stability and reliability of the circuit, and reduce the complexity and cost of the circuit.

[0062] Exemplarily, continuing to take the isolation circuit 121 of the first direction anti-backflow branch B1 as an example, the optocoupler device includes an optocoupler transmitting tube T11 and an optocoupler receiving tube R11. Further, the anode of the optocoupler transmitting tube T11 is connected to the output end of the first operational amplifier U11, the cathode of the optocoupler transmitting tube T11 is grounded, the anode of the optocoupler receiving tube R11 is grounded, and the cathode of the optocoupler receiving tube R11 is coupled to one of the input ends of the second operational amplifier U21 ( Figure 2 Take the example of connecting the non-inverting input terminal).

[0063] Please continue to see Figure 1 and Figure 2 Continuing with the example of the isolation circuit 121 of the first direction anti-backflow branch B1, Figure 2It can be seen that in some preferred embodiments, the IO circuit includes a push-pull pair of transistors having a third MOS transistor and a fourth MOS transistor; the gate end of the third MOS transistor and the gate end of the fourth MOS transistor are connected together to form the first end of the IO circuit and coupled to the isolation circuit. The first end of the third MOS transistor Q31 of the first direction anti-backflow branch B1 is configured to couple the second power supply voltage VCC2, and the first end of the third MOS transistor Q32 of the second direction anti-backflow branch B2 is configured to couple the first power supply voltage VCC1. The second end of the third MOS transistor Q31 and the first end of the fourth MOS transistor Q41 are connected together to couple the first end of the second control circuit 141, and the second end of the fourth MOS transistor Q41 is grounded. Therefore, the bidirectional anti-backflow circuit provided by the utility model, the IO circuit of its anti-backflow branch adopts the design of a push-pull pair of transistors, which not only has low power loss, but also can make the circuit operation more stable and has better linearity.

[0064] In order to facilitate the understanding of the present invention, the following Figure 2 The specific working process of the bidirectional anti-backflow circuit provided by the utility model is exemplarily described as follows:

[0065] When the first chip 310 transmits the first signal level VI1 to the second IO node P2 through the first IO node P1 as the second signal level VO1: the first drive signal C1 drives the first MOS transistor Q11 and the second MOS transistor Q21 of the first direction anti-backflow branch B1 to turn on; the second drive signal C2 turns off the first MOS transistor Q12 and the second MOS transistor Q22 of the second direction anti-backflow branch B2. Further, when the first signal level VI1 is at a high level, the first operational amplifier U11 compares the first signal level VI1 with the GND signal and outputs a high level to drive the optocoupler transmitting tube T11 to generate current. After the optocoupler transmitting tube T11 generates current, it is transmitted to the optocoupler receiving tube R11 through the optocoupler effect, resulting in a voltage signal at the non-inverting input terminal of the second operational amplifier U21. After comparison, the second operational amplifier U21 outputs a high level to turn on the third MOS transistor Q31, and the second signal level VO1 output by the second IO node P2 is at a high level. When the first signal level VI1 is at a low level, the first operational amplifier U11 compares the first signal level VI1 with the GND signal and outputs a low level, the optocoupler transmitting tube T11 does not generate current, and the optocoupler receiving tube R11 also does not receive current, so that the second operational amplifier U21 outputs a low level after comparison to drive the fourth MOS tube Q41 to turn on, and the second signal level VO1 output by the second IO node P2 is at a low level.

[0066] When the second chip 320 transmits the second signal level VO1 to the first IO node P1 through the second IO node P2 as the first signal level VI1: at this time, the second drive signal C2 drives the first MOS transistor Q12 and the second MOS transistor Q22 of the second direction anti-backflow branch B2 to turn on; the first drive signal C2 drives the first MOS transistor Q11 and the second MOS transistor Q21 of the first direction anti-backflow branch B1 to turn off. Further, when the second signal level VO1 is at a high level, the first operational amplifier U12 compares the second signal level VO1 with the GND signal and outputs a high level to drive the optocoupler transmitting tube T12 to generate current. After the optocoupler transmitting tube T12 generates current, it is transmitted to the optocoupler receiving tube R12 through the optocoupler effect, resulting in a voltage signal at the non-inverting input terminal of the second operational amplifier U22. After comparison, the second operational amplifier U22 outputs a high level to turn on the third MOS tube Q32, and the first signal level VI1 output by the first IO node P1 is a high level. When the second signal level VO1 is at a low level, the first operational amplifier U12 compares the second signal level VO1 with the GND signal and outputs a low level, the optocoupler transmitting tube T12 does not generate current, and the optocoupler receiving tube R12 also cannot receive current, so that the second operational amplifier U22 outputs a low level after comparison to drive the fourth MOS tube Q42 to turn on, and the first signal level VI1 output by the first IO node P1 is at a low level.

[0067] It can be seen that the bidirectional anti-backflow circuit provided by the utility model can not only effectively prevent IO level backflow without affecting IO transmission, thereby realizing isolation protection between chips; but also the required components are inexpensive and easy to obtain, and the circuit structure is simple and easy to implement.

[0068] The second embodiment of the utility model provides another bidirectional anti-backflow circuit. The circuit structure of the anti-backflow module of the bidirectional anti-backflow circuit provided by the second embodiment is basically the same as the circuit structure of the anti-backflow module of the bidirectional anti-backflow circuit provided by the first embodiment, that is, each of the anti-backflow modules of the bidirectional anti-backflow circuit provided by the second embodiment includes two anti-backflow branches with the same circuit structure and opposite anti-backflow directions, and each of the anti-backflow branches also includes a first control circuit, an isolation circuit, an IO circuit and a second control circuit coupled in sequence. The difference between the bidirectional anti-backflow circuit provided by the second embodiment and the first embodiment is that the IO circuits of the anti-backflow branches of the two are different. In order to avoid redundancy and facilitate understanding, only the differences are explained below. For the specific circuit structure and working principle of the bidirectional anti-backflow circuit in the second embodiment that are not described in detail, please refer to the corresponding part of the bidirectional anti-backflow circuit provided by the first embodiment for adaptive understanding.

[0069] Exemplarily, the IO circuit includes a third MOS transistor and a fourth MOS transistor coupled in an open-drain form. Thus, the IO current adopts the design mode of the third MOS transistor and the fourth MOS transistor coupled in an open-drain form, which can better realize the wired-AND function.

[0070] It should be noted that, as can be understood by those skilled in the art, when the bidirectional anti-backflow circuit provided by the utility model is specifically applied, the bidirectional anti-backflow circuit provided by the first embodiment or the bidirectional anti-backflow circuit provided by the second embodiment should be reasonably selected according to actual needs. In addition, for more detailed information about push-pull output and open-drain output, please refer to the relevant technologies known to those skilled in the art, and no further explanation will be given here.

[0071] The bidirectional anti-backflow circuit of the utility model can be implemented as a PCB circuit (i.e., discrete components) outside the package of a chip; in addition, the third embodiment of the utility model provides a protection chip, the protection chip is integrated with a bidirectional anti-backflow circuit as described in any implementation of the first embodiment of the utility model or the second embodiment, for example, the aforementioned bidirectional anti-backflow circuit can also be implemented inside the package outside the die of the chip. Since the protection chip provided by the utility model is integrated with the bidirectional anti-backflow circuit provided by the utility model, the protection chip provided by the utility model at least has all the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model. For details, please refer to the relevant description of the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model in the above text, so the beneficial effects of the protection chip provided by the utility model will not be repeated here.

[0072] The fourth embodiment of the utility model provides an adapter board, on which is disposed a bidirectional anti-backflow circuit as described in any implementation mode of the first embodiment of the utility model or the second embodiment, or a protection chip provided by the third embodiment of the utility model.

[0073] Since the adapter board provided by the utility model is provided with the bidirectional anti-backflow circuit provided by the utility model, the adapter board provided by the utility model at least has all the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model. For details, please refer to the relevant description of the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model in the above text, so the beneficial effects of the adapter board provided by the utility model will not be described one by one here. In addition, it should be noted that, as can be understood by those skilled in the art, the adapter board has a wide range of applications in the fields of embedded system development, communication equipment connection, and sensor connection. The utility model does not make any limitation on the specific application field of the adapter board. For more detailed contents such as the specific structure of the adapter board, please refer to the relevant technologies known to those skilled in the art, and will not be elaborated here.

[0074] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0075] Compared with the prior art, the bidirectional anti-backflow circuit, protection chip and adapter board provided by the utility model have the following beneficial effects:

[0076] The bidirectional anti-backflow circuit provided by the utility model includes at least one anti-backflow module, each of which includes two anti-backflow branches with the same circuit structure and opposite anti-backflow directions, and each of the anti-backflow branches includes a first control circuit, an isolation circuit, an IO circuit and a second control circuit coupled in sequence. The two anti-backflow branches are respectively a first direction anti-backflow branch and a second direction anti-backflow branch, and when the first signal level is transmitted from the first IO node to the second IO node, the first drive signal controls the first direction anti-backflow branch to be turned on and the second drive signal controls the second direction anti-backflow branch to be disconnected, thereby preventing the second signal level from the second IO node to the first IO node from backflowing; and when the second signal level is transmitted from the second IO node to the first IO node, the second drive signal controls the second direction anti-backflow branch to be turned on and the first drive signal controls the first direction anti-backflow branch to be disconnected, thereby preventing the first signal level from the first IO node to the second IO node from backflowing. With such a configuration, the bidirectional anti-backflow circuit provided by the utility model realizes bidirectional transmission and isolation protection between chips without affecting IO transmission. It can not only effectively prevent IO level backflow without affecting IO transmission, thereby realizing isolation protection between chips, but also has a simple circuit structure and is easy to implement.

[0077] Since the protection chip and adapter board provided by the utility model belong to the same inventive concept as the bidirectional anti-backflow circuit provided by the utility model, the protection chip and adapter board provided by the utility model at least have all the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model. For details, please refer to the relevant description of the beneficial effects of the bidirectional anti-backflow circuit provided by the utility model in the above text. Therefore, the beneficial effects of the protection chip and adapter board provided by the utility model will not be described one by one here.

[0078] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0079] In summary, the above embodiments provide detailed descriptions of the different configurations of the bidirectional anti-backflow circuit, protection chip and adapter board provided by the utility model. Of course, the above description is only a description of the preferred embodiments of the utility model, and is not any limitation on the scope of the utility model. The utility model includes but is not limited to the configurations listed in the above implementations. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the utility model based on the above disclosures shall fall within the scope of protection of the claims.

Claims

1. A bidirectional anti-backflow circuit, characterized in that: The bidirectional backflow prevention circuit includes at least one backflow prevention module, the backflow prevention module includes two backflow prevention branches with the same circuit structure and opposite backflow prevention directions, each of the backflow prevention branches includes a first control circuit, an isolation circuit, an IO circuit and a second control circuit coupled in sequence; The two anti-backflow branches are respectively a first direction anti-backflow branch and a second direction anti-backflow branch, and a first end of a first control circuit of the first direction anti-backflow branch is coupled to a first end of a second control circuit of the second direction anti-backflow branch to form a first IO node, and the first IO node is configured to couple a first signal level; The first end of the second control circuit of the first direction anti-backflow branch and the first end of the first control circuit of the second direction anti-backflow branch are coupled to form a second IO node, and the second IO node is configured to couple a second signal level; the control end of the first control circuit of the first direction anti-backflow branch and the control end of the second control circuit are both configured to couple a first drive signal, and the control end of the first control circuit of the second direction anti-backflow branch and the control end of the second control circuit are both configured to couple a second drive signal; The bidirectional anti-backflow circuit is configured such that when the first signal level is transmitted from the first IO node to the second IO node, the first drive signal controls the first direction anti-backflow branch to be turned on and the second drive signal controls the second direction anti-backflow branch to be turned off; and when the second signal level is transmitted from the second IO node to the first IO node, the second drive signal controls the second direction anti-backflow branch to be turned on and the first drive signal controls the first direction anti-backflow branch to be turned off.

2. The bidirectional anti-backflow circuit according to claim 1, characterized in that: The first IO node is further configured to be coupled to a first power supply voltage; and the second IO node is further configured to be coupled to a second power supply voltage.

3. The bidirectional anti-backflow circuit according to claim 2, characterized in that: The first control circuit includes a first MOS transistor, a gate terminal of the first MOS transistor of the first direction anti-backflow branch is configured to couple the first drive signal, and a gate terminal of the first MOS transistor of the second direction anti-backflow branch is configured to couple the second drive signal; And / or the second control circuit includes a second MOS tube, the gate end of the second MOS tube of the first direction anti-backflow branch is configured to couple the first drive signal, and the gate end of the second MOS tube of the second direction anti-backflow branch is configured to couple the second drive signal.

4. The bidirectional anti-backflow circuit according to claim 1, characterized in that: The isolation circuit includes a first operational amplifier, an isolation device, and a second operational amplifier; the power pin of the first operational amplifier of the first direction anti-backflow branch and the power pin of the second operational amplifier of the second direction anti-backflow branch are configured to be connected to a first power supply voltage, and the power pin of the second operational amplifier of the first direction anti-backflow branch and the power pin of the first operational amplifier of the second direction anti-backflow branch are configured to be connected to a second power supply voltage; One of the input terminals of the first operational amplifier is coupled to the second terminal of the first control circuit, the other input terminal of the first operational amplifier is grounded, the output terminal of the first operational amplifier is coupled to the first terminal of the isolation device, the second terminal of the isolation device is coupled to one of the input terminals of the second operational amplifier, the other input terminal of the second operational amplifier is grounded, and the output terminal of the second operational amplifier is coupled to the first terminal of the IO circuit.

5. The bidirectional anti-backflow circuit according to claim 4, characterized in that: The isolation device includes an optocoupler isolation device or an electromagnetic isolation device.

6. The bidirectional anti-backflow circuit according to claim 1, characterized in that: The IO circuit includes a push-pull pair of transistors including a third MOS transistor and a fourth MOS transistor; a gate end of the third MOS transistor and a gate end of the fourth MOS transistor are connected together to form a first end of the IO circuit and coupled to the isolation circuit; a first end of the third MOS transistor of the first direction anti-backflow branch is configured to be coupled to a second power supply voltage, and a first end of the third MOS transistor of the second direction anti-backflow branch is configured to be coupled to a first power supply voltage; a second end of the third MOS transistor and a first end of the fourth MOS transistor are connected together to couple to a first end of the second control circuit, and a second end of the fourth MOS transistor is grounded.

7. The bidirectional anti-backflow circuit according to any one of claims 1 to 6, characterized in that: The bidirectional anti-backflow circuit is used for verifying a test system, and the verification test system includes a first chip, a transfer board, and a second chip; the bidirectional anti-backflow circuit is arranged on the transfer board, and a first IO node of the bidirectional anti-backflow circuit is configured to couple a first signal level of the first chip, and a second IO node of the bidirectional anti-backflow circuit is configured to couple a second signal level of the second chip; The third end of the first direction backflow prevention branch is configured to couple the first driving signal of the verification test system; The third end of the second direction backflow prevention branch is configured to be coupled to a second driving signal of the verification test system.

8. The bidirectional anti-backflow circuit according to claim 7, characterized in that: The bidirectional anti-backflow circuit further includes a level conversion circuit, a first end of the level conversion circuit is configured to be coupled to the first chip to access the first signal level, and a second end of the level conversion circuit is coupled to the first IO node.

9. The bidirectional anti-backflow circuit according to claim 1, characterized in that: The IO circuit further includes a third MOS transistor and a fourth MOS transistor coupled in an open-drain form.

10. A protection chip, characterized in that: The protection chip is integrated with the bidirectional anti-backflow circuit as claimed in any one of claims 1 to 9.

11. An adapter plate, characterized in that: The adapter board is provided with a bidirectional anti-backflow circuit as described in any one of claims 1 to 9 or a protection chip as described in claim 10.

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