Power management circuit of DDR (Double Data Rate) memory and NAS (Network Attached Storage) equipment
By using a two-stage control to enable or turn off the power management chip in the DDR memory power management circuit, the problem that the DDR memory power supply method in the prior art is not conducive to energy saving, and the power supply cut-off is achieved in the sleep state of the device. Extend the service life of the equipment.
Patent Information
- Application Number
- CN202421172485.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-23
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-05-23
AI Technical Summary
In the prior art, the power supply method of DDR memory is not conducive to saving energy when the device is in a power-on or sleep state, resulting in a decrease in the service life of the DDR memory and the applied equipment.
A power management circuit for DDR memory is designed, including a power management chip, a main control chip, a primary switching unit, a secondary switching unit and a communication unit. The power management chip is enabled or turned off through precise two-stage control, and turned on or off. The buck unit operates, thereby cutting off the power supply of the DDR memory while the device is in a dormant state.
It realizes the power supply of DDR memory in the sleep state, saves energy, and improves the service life of DDR memory and NAS devices.
Smart Images
Figure CN222337926U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power management circuits, in particular to a power management circuit of a DDR memory and a NAS device. Background Art
[0002] DDR (Double Data Rate Random Access Memory) memory is a common random access memory used to temporarily store data and instructions. DDR memory is usually used in desktop computers, laptops, servers, NAS devices and other devices. Especially NAS devices. NAS devices are network attached storage devices. Network Attached Storage (NAS) literally means a device connected to the network with data storage function, so it is also called "network storage". It is a dedicated data storage server. It is data-centric, completely separates storage devices from servers, and centrally manages data, thereby freeing up bandwidth, improving performance, and reducing costs.
[0003] NAS devices or other devices using DDR memory usually include DDR memory and a power supply module, and the power supply module supplies power to the DDR memory to enable it to work normally. In the prior art, the power supply module supplies power to the DDR memory when the device is in the power-on state or the sleep state, which is not conducive to energy saving and reduces the service life of the DDR memory and the device to which it is applied. Utility Model Content
[0004] The embodiment of the utility model provides a power management circuit of a DDR memory and a NAS device, so as to solve the problem that the power supply mode of the DDR memory in the prior art is not conducive to energy saving and reduces the service life of the DDR memory and the applied equipment.
[0005] The utility model discloses a power management circuit of a DDR memory, comprising:
[0006] A power management chip, which is provided with an enable terminal, a power input terminal and a power output control terminal, wherein the power input terminal is used to input power;
[0007] A step-down unit, connected to the power output control terminal and the external DDR memory respectively;
[0008] Main control chip, used to output level signals;
[0009] A primary switch unit, wherein a control end of the primary switch unit is electrically connected to the main control chip, and a second end of the primary switch unit is grounded;
[0010] A secondary switch unit, wherein a control end of the secondary switch unit is connected to a power supply, a first end of the secondary switch unit is connected to the power supply and an enable end of the power management chip, and a second end is grounded;
[0011] A connecting unit is provided between the first end of the primary switch unit and the control end of the secondary switch unit, and is used to connect the first end of the primary switch unit and the control end of the secondary switch unit;
[0012] The main control chip outputs a level signal to control the on or off of the primary switch unit, so as to turn on or off the secondary switch unit, thereby enabling the power management chip to be turned on or off.
[0013] Among them, a preferred solution is that the connectivity unit includes a normal switch unit, the control end of the normal switch unit is used to receive a high-level signal from an external system controller hub, the first end is connected to the power supply and the control end of the secondary switch unit, and the second end is connected to the first end of the primary switch unit.
[0014] Among them, a preferred solution is that the primary switch unit includes a first NMOS tube, the gate of the first NMOS tube is electrically connected to the main control chip, the drain is connected to the second end of the normal switch unit, and the source is grounded.
[0015] Among them, a preferred solution is that the secondary switch unit includes a second NMOS tube, the gate of the second NMOS tube is connected to the power supply and the first end of the normal switch unit, the drain is connected to the power supply and the enable end of the power management chip, and the source is grounded.
[0016] Among them, a preferred solution is that the normal switch unit includes a third NMOS tube, the gate of the third NMOS tube is used to receive a high-level signal from an external system controller hub, the drain is connected to the power supply and the gate of the second NMOS tube, and the source is connected to the drain of the first NMOS tube.
[0017] Among them, a preferred solution is that the power management circuit also includes a first pull-up resistor, a first end of the first pull-up resistor is connected to the power supply, and a second end is connected to the drain of the second NMOS tube and the enable end of the power management chip.
[0018] Among them, a preferred solution is that the power management circuit also includes a filter capacitor, a first end of the filter capacitor is connected to the second end of the first pull-up resistor, and the second end of the filter capacitor is grounded.
[0019] Among them, a preferred solution is that the power management circuit also includes a second pull-up resistor, a first end of the second pull-up resistor is connected to the power supply, and a second end is connected to the drain of the third NMOS tube and the gate of the second NMOS tube.
[0020] Among them, a preferred solution is that the connecting unit includes a first resistor, a first end of the first resistor is connected to the control end and the power supply of the secondary switch unit, and a second end is connected to the first end of the primary switch unit.
[0021] The utility model also discloses a NAS device, comprising a DDR memory and a power management circuit of the DDR memory as described above, wherein a voltage reduction unit of the power management circuit is connected to the DDR memory.
[0022] Compared with the prior art, the beneficial effects of the power management circuit of the DDR memory and the NAS device provided by the embodiments of the utility model are as follows: by setting a power management chip, a main control chip, a primary switch unit, a secondary switch unit and a connecting unit, the control end of the primary switch unit is electrically connected to the main control chip, and the second end is grounded, the control end of the secondary switch unit is connected to the power supply, the first end of the secondary switch unit is connected to the power supply and the enable end of the power management chip, and the second end is grounded, and the connecting unit is set between the first end of the primary switch unit and the control end of the secondary switch unit. The circuit of the connecting unit can be set according to needs to realize ordinary control or more precise two-stage control to enable the power management chip to be turned on or off, and the step-down unit to be turned on or off, thereby turning on or off the power supply to the DDR memory, and cutting off the power supply of the DDR memory when the applied device is in a dormant state, saving energy, and improving the service life of the DDR memory and the NAS device. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The technical solution of the utility model will be further described in detail below with reference to the accompanying drawings and embodiments, in which:
[0024] Figure 1 It is a structural block diagram of a power management circuit of a DDR memory provided by an embodiment of the utility model;
[0025] Figure 2 It is a partial circuit diagram of the power management chip provided by the embodiment of the utility model;
[0026] Figure 3 This is a circuit diagram of enabling the power management chip provided in the first embodiment of the utility model;
[0027] Figure 4 This is a circuit diagram of enabling the power management chip provided in the second embodiment of the present utility model;
[0028] Figure 5 It is a structural block diagram of the NAS device provided in the third embodiment of the present utility model.
[0029] The reference numerals in the figures are:
[0030] 10. Power management circuit of DDR memory;
[0031] 110, power management chip; 111, enable terminal; 112, power input terminal; 113, power output control terminal; 120, main control chip; 130, primary switch unit; 140, secondary switch unit; 150, connection unit; 151, normal switch unit; 160, step-down unit;
[0032] 100. NAS device; 20. DDR memory;
[0033] Q1, a first NMOS transistor; Q2, a second NMOS transistor; Q3, a third NMOS transistor; R1, a first pull-up resistor; R2, a second pull-up resistor; R3, a first resistor; C1, a filter capacitor. DETAILED DESCRIPTION
[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. Now, in conjunction with the accompanying drawings, a preferred embodiment of the present utility model is described in detail.
[0035] Embodiment 1
[0036] The present utility model embodiment provides a power management circuit 10 of a DDR memory, such as Figures 1 to 3 As shown, the power management circuit 10 of the DDR memory includes a power management chip 110, a main control chip 120, a primary switch unit 130, a secondary switch unit 140, a connecting unit 150 and a voltage reduction unit 60.
[0037] The power management chip 110 is provided with an enable terminal 111 , a power input terminal 112 , and a power output control terminal 113 . The power input terminal 112 is used to input power, and the power output control terminal 113 is used to output a control signal.
[0038] The voltage reduction unit 160 is connected to the power output control terminal 113 and the external DDR memory respectively. Under the control of the control signal output by the power output control terminal 113, the voltage reduction unit 160 reduces the voltage to supply power to the DDR memory.
[0039] The main control chip 120 is used to output a level signal.
[0040] A control end of the primary switch unit 130 is electrically connected to the main control chip 120 , and a second end is grounded.
[0041] The control end of the secondary switch unit 140 is connected to the power supply, the first end of the secondary switch unit 140 is connected to the power supply and the enable end 111 of the power management chip 110, and the second end is grounded.
[0042] The connecting unit 150 is disposed between the first end of the primary switch unit 130 and the control end of the secondary switch unit 140 , and is used to connect the first end of the primary switch unit 130 and the control end of the secondary switch unit 140 .
[0043] The main control chip 120 outputs a level signal to control the on or off of the primary switch unit 130 to turn on or off the secondary switch unit 140 to enable the power management chip 110 to turn on or off.
[0044] The present application sets a power management chip 110, a main control chip 120, a primary switch unit 130, a secondary switch unit 140 and a connecting unit 150. The control end of the primary switch unit 130 is electrically connected to the main control chip 120, and the second end is grounded. The control end of the secondary switch unit 140 is connected to the power supply. The first end of the secondary switch unit 140 is connected to the power supply and the enable end 111 of the power management chip 110, and the second end is grounded. The connecting unit 150 is set between the first end of the primary switch unit 130 and the control end of the secondary switch unit 140. The circuit of the connecting unit 150 can be set according to requirements to realize ordinary control or more precise two-stage control to enable the power management chip 110 to be turned on or off, and the step-down unit 160 to be turned on or off, thereby turning on or off the power supply to the DDR memory 20, and cutting off the power supply of the DDR memory 20 when the applied device is in a dormant state, saving energy, and increasing the service life of the DDR memory 20.
[0045] Among them, the level signal output by the main control chip 120 can be a high level signal or a low level signal. The level signal output by the main control chip 120 can output a high level signal or a low level signal according to whether the DDR memory 20 is working, that is, whether the device applied by the DDR memory 20 is in sleep mode. For example, if the NAS device applied by the DDR memory 20 is in sleep mode, and the DDR memory 20 does not need to work, then the main control chip 120 outputs a corresponding level signal based on the sleep mode of the NAS device, and enables the power management chip 110 to be turned off through the primary switch unit 130 and the secondary switch unit 140, and no control signal is output to the step-down unit 160, so as to disconnect the power supply of the DDR memory 20. The main control chip 120 adopts an existing chip, which can be an existing chip on the applied NAS device, and outputs a level signal. The software implementation program of the output level signal does not belong to the improvement of the present utility model.
[0046] The power management chip 110 may specifically be an RT8237E chip, which is usually used in notebook computers and other portable devices to manage power supply and charging functions. The RT8237E has efficient power management capabilities, which can help extend the life of the applied device and improve the overall performance of the device.
[0047] refer to Figures 1 to 3 In this embodiment, the connectivity unit 150 includes a normal switch unit 151, a control end of the normal switch unit 151 is used to receive a high-level signal from an external system controller hub, a first end is connected to a power supply and a control end of the secondary switch unit 140, and a second end is connected to a first end of the primary switch unit 130.
[0048] By setting a normal switch unit 151, the control end of the normal switch unit 151 receives a high-level signal from the external system controller hub, maintains a normally on state, and turns on the path between the first end of the primary switch unit 130 and the control end of the secondary switch unit 140. The main control chip 120 controls the on or off of the primary switch unit 130, and further controls the on or off of the secondary switch unit 140.
[0049] In the case where the main control chip 120 outputs a high-level signal, when the overall system corresponding to the external system controller hub is in a sleep state, the normal switch unit 151 will not receive the high-level signal, and the path between the first end of the primary switch unit 130 and the control end of the secondary switch unit 140 will be disconnected; when the overall system corresponding to the external system controller hub enters the boot process from the sleep state, the external system controller hub management outputs a high-level signal, thereby adapting to the startup sequence management of the external overall system, outputting a high-level signal at the right time to guide the normal switch unit 151, and then turning on the path between the primary switch unit 130 and the secondary switch unit 140, enabling the power management chip 110 to be turned on at the right time to power the DDR memory 20, so as to ensure that the DDR memory 20 can operate normally and achieve optimal performance, thereby realizing two-level precise control.
[0050] Among them, the high-level signal output by the external system controller hub is implemented through an existing software program. If the high-level signal itself is used for other work-related controls of the external overall system, its software implementation program does not belong to the improvement of the present utility model.
[0051] refer to Figures 1 to 3 In this embodiment, the primary switch unit 130 includes a first NMOS transistor Q1, a control end of the first NMOS transistor Q1 is electrically connected to the main control chip 120, a drain is connected to the second end of the normal switch unit 151, and a source is grounded.
[0052] By setting the first NMOS transistor Q1, the gate of the first NMOS transistor Q1 receives the level signal of the main control chip 120 to realize turning on or off, thereby turning on or off the secondary switch unit 140. The first NMOS transistor Q1 has a faster switching speed, is smaller and has less noise than a mechanical switch, and its compact appearance is conducive to the miniaturization of the overall circuit.
[0053] In other embodiments, the primary switch unit 130 may use a switch device such as a relay.
[0054] refer to Figure 3 In this embodiment, the secondary switch unit 140 includes a second NMOS tube Q2, the gate of the second NMOS tube Q2 is connected to the power supply and the first end of the normal switch unit 151, the drain is connected to the power supply and the enable end 111 of the power management chip 110, and the source is grounded.
[0055] By setting the second NMOS transistor Q2, the path between the enable terminal 111 of the power management chip 110 and the ground terminal is turned on or off, so that the enable terminal 111 of the power management chip 110 is at a high level or a low level, the power management chip 110 is turned on or off, and the power supply of the DDR memory 20 is turned on or off. The second NMOS transistor Q2 has a faster switching speed, is smaller and has less noise than a mechanical switch, and its compact appearance is conducive to the miniaturization of the overall circuit.
[0056] In other embodiments, the secondary switch unit 140 may use a switch device such as a relay.
[0057] refer to Figure 3 In this embodiment, the normal switch unit 151 includes a third NMOS tube Q3, the gate of the third NMOS tube Q3 is used to receive a high-level signal from the external system controller hub, the drain is connected to the power supply and the gate of the second NMOS tube Q2, and the source is connected to the drain of the first NMOS tube Q1.
[0058] By providing the third NMOS transistor Q3, the gate of the third NMOS transistor Q3 receives the high level signal of the external system controller hub, and conducts the path between the drain of the first NMOS transistor Q1 and the gate of the second NMOS transistor Q2. The third NMOS transistor Q3 has a faster switching speed, is smaller and has less noise than a mechanical switch, and its compact appearance is conducive to the miniaturization of the overall circuit.
[0059] In other embodiments, the normal switch unit 151 may use a switch device such as a relay.
[0060] refer to Figure 2 and Figure 3 In this embodiment, the power management circuit further includes a first pull-up resistor R1, a first end of the first pull-up resistor R1 is connected to the power supply, and a second end is connected to the drain of the second NMOS tube Q2 and the enable terminal 111 of the power management chip 110.
[0061] By setting the first pull-up resistor R1, when the second NMOS tube Q2 is in the cut-off state, the first pull-up resistor R1 pulls up the enable terminal 111 of the power management chip 110 to clamp it at the power level, which is in a high level state, so that the level of the enable terminal 111 of the power management chip 110 remains stable, enabling the power management chip 110 to be turned on and supply power to the DDR memory 20. Specifically, the power level can be 5V.
[0062] Furthermore, the power management circuit further includes a filter capacitor C1, a first end of the filter capacitor C1 is connected to a second end of the first pull-up resistor R1, and a second end of the filter capacitor C1 is grounded. The filter capacitor C1 cooperates with the first pull-up resistor R1 to form an RC circuit, which plays a role of time delay, so that the level waveform of the enable terminal 111 is smooth.
[0063] refer to Figure 2 and Figure 3 In this embodiment, the power management circuit further includes a second pull-up resistor R2, a first end of the second pull-up resistor R2 is connected to the power supply, and a second end is connected to the drain of the third NMOS tube Q3 and the gate of the second NMOS tube Q2.
[0064] By setting the second pull-up resistor R2, when the first NMOS transistor Q1 and the third NMOS transistor Q3 are in the cut-off state, the second pull-up resistor R2 pulls up the gate of the second NMOS transistor Q2 to clamp it at the power supply level, which is in a high level state, turning on the second NMOS transistor Q2, and then pulling down the level of the enable terminal 111 of the power management chip 110, turning off the power management chip 110, and disconnecting the power supply of the DDR memory 20.
[0065] In this embodiment, the specific working principle of the power management circuit 10 of the DDR memory is as follows:
[0066] The main control chip 120 outputs a high-level signal, the first NMOS tube Q1 is turned on, and the gate of the third NMOS tube Q3 receives a high-level signal from the external system controller hub to be turned on. The turning on of the first NMOS tube Q1 and the turning on of the third NMOS tube Q3 pulls the level of the gate of the second NMOS tube Q2 down to a low level, and the second NMOS tube Q2 is turned off. The enable terminal 111 of the power management chip 110 is pulled up to the level of the power supply through the first pull-up resistor R1 by the power supply and is in a high-level state, enabling the power management chip 110 to be turned on, and the power output control terminal 113 of the power management chip 110 controls the power supply to the DDR memory 20. The main control chip 120 outputs a low-level signal, the first NMOS tube Q1 is turned off, and the gate of the third NMOS tube Q3 receives a high-level signal from the external system controller hub to be turned on. Since the first NMOS tube Q1 is turned off, the path between the third NMOS tube Q3 and the ground terminal is disconnected, the source of the third NMOS tube Q3 is suspended, and the level of the gate of the second NMOS tube Q2 is pulled up to a high-level state through the second pull-up resistor R2. The second NMOS tube Q2 is turned on, and the enable terminal 111 of the power management chip 110 is pulled down to a low level by the power supply, enabling the power management chip 110 to be turned off. The power output control terminal 113 of the power management chip 110 does not output control, and the power supply of the DDR memory 20 is disconnected, so that the power supply is cut off when the DDR memory 20 does not need to work, saving energy, and increasing the service life of the DDR memory 20 and the NAS device.
[0067] Embodiment 2
[0068] The difference between this embodiment and the first embodiment is that in this embodiment, reference Figure 1 , Figure 2 and Figure 4 The connecting unit 150 includes a first resistor R3 , a first end of the first resistor R3 is connected to the control end and the power supply of the secondary switch unit 140 , and a second end is connected to the first end of the primary switch unit 130 .
[0069] By setting the first resistor R3, the control end of the secondary switch unit 140 is connected to the power supply, and the second end is connected to the path between the first end of the primary switch unit 130. When the main control chip 120 outputs a high-level signal, the primary switch unit 130 is turned on, and the level of the control end of the secondary switch unit 140 is pulled down to a low level, the secondary switch unit 140 is disconnected, the enable end 111 of the power management chip 110 is connected to the power supply and is in a high-level state, and the power output control end 113 of the power management chip 110 controls the power supply to the DDR memory 20. When the main control chip 120 outputs a low-level signal, the primary switch unit 130 is turned off, the control end of the secondary switch unit 140 is connected to the power supply and is in a high-level state, the secondary switch unit 140 is turned on, and the enable end 111 of the power management chip 110 is pulled down to a low level by the power supply, enabling the power management chip 110 to be turned off, and the power output control end 113 of the power management chip 110 does not output control, and the power supply of the DDR memory 20 is disconnected.
[0070] In this embodiment, the control end and the power supply of the secondary switch unit 140 are connected through the first resistor R3, and the second end is connected to the first end of the primary switch unit 130. The power management chip 110 is enabled to be turned on or off at a relatively low cost, thereby turning on or off the power supply to the DDR memory 20. When the DDR memory 20 does not need to work, the power supply is cut off, thereby saving energy and increasing the service life of the DDR memory 20.
[0071] Further, when the primary switch unit 130 includes a first NMOS transistor Q1 and the secondary switch unit 140 includes a second NMOS transistor Q2, a first end of the first resistor R3 is connected to the gate of the second NMOS transistor Q2 and a power source, and a second end is connected to the drain of the first NMOS transistor Q1.
[0072] Embodiment 3
[0073] This embodiment provides a NAS device 100, referring to Figure 5 The NAS device 100 includes a DDR memory 20 and the aforementioned power management circuit 10 of the DDR memory, and a voltage reduction unit 160 of the power management circuit is connected to the DDR memory 20 .
[0074] The power management circuit 10 of the DDR memory in the NAS device 100 of this embodiment is provided with a power management chip 110, a main control chip 120, a primary switch unit 130, a secondary switch unit 140 and a connecting unit 150. The control end of the primary switch unit 130 is electrically connected to the main control chip 120, and the second end is grounded. The control end of the secondary switch unit 140 is connected to the power supply. The first end of the secondary switch unit 140 is connected to the power supply and the enable end 111 of the power management chip 110, and the second end is grounded. The connecting unit 150 is provided between the first end of the primary switch unit 130 and the control end of the secondary switch unit 140. The circuit of the connecting unit 150 can be provided as required to realize common control or more accurate two-stage control to enable the power management chip 110 to be turned on or off, and to turn on or off the work of the step-down unit 160, thereby turning on or off the power supply to the DDR memory 20, and cutting off the power supply to the DDR memory 20 when the applied device is in a dormant state, thereby saving energy and prolonging the service life of the DDR memory 20 and the NAS device 100.
[0075] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present utility model rather than to limit it. For those skilled in the art, the technical solutions described in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents; and all these modifications and replacements should fall within the scope of protection of the claims attached to the present utility model.
Claims
1. A power management circuit for a DDR memory, characterized in that: include: A power management chip, which is provided with an enable terminal, a power input terminal and a power output control terminal, wherein the power input terminal is used to input power, and the power output control terminal is used to output a control signal; A step-down unit, connected to the power output control terminal and the external DDR memory respectively; Main control chip, used to output level signals; A primary switch unit, wherein a control end of the primary switch unit is electrically connected to the main control chip, and a second end of the primary switch unit is grounded; A secondary switch unit, wherein a control end of the secondary switch unit is connected to a power supply, a first end of the secondary switch unit is connected to the power supply and an enable end of the power management chip, and a second end is grounded; A connecting unit is provided between the first end of the primary switch unit and the control end of the secondary switch unit, and is used to connect the first end of the primary switch unit and the control end of the secondary switch unit; The main control chip outputs a level signal to control the on or off of the primary switch unit, so as to turn on or off the secondary switch unit, thereby enabling the power management chip to be turned on or off.
2. The power management circuit of the DDR memory according to claim 1, characterized in that: The connectivity unit comprises a normal switch unit, a control end of which is used to receive a high level signal from an external system controller hub, a first end of which is connected to a power supply and the control end of the secondary switch unit, and a second end of which is connected to a first end of the primary switch unit.
3. The power management circuit of the DDR memory according to claim 2, characterized in that: The primary switch unit comprises a first NMOS tube, a gate of the first NMOS tube is electrically connected to the main control chip, a drain is connected to the second end of the normal switch unit, and a source is grounded.
4. The power management circuit of the DDR memory according to claim 3, characterized in that: The secondary switch unit includes a second NMOS tube, the gate of the second NMOS tube is connected to the power supply and the first end of the normal switch unit, the drain is connected to the power supply and the enable end of the power management chip, and the source is grounded.
5. The power management circuit of the DDR memory according to claim 4, characterized in that: The normal switch unit includes a third NMOS tube, the gate of the third NMOS tube is used to receive a high level signal from an external system controller hub, the drain is connected to a power supply and the gate of the second NMOS tube, and the source is connected to the drain of the first NMOS tube.
6. The power management circuit of the DDR memory according to claim 4, characterized in that: The power management circuit also includes a first pull-up resistor, a first end of the first pull-up resistor is connected to a power source, and a second end is connected to the drain of the second NMOS tube and an enable end of the power management chip.
7. The power management circuit of the DDR memory according to claim 6, characterized in that: The power management circuit further includes a filter capacitor, a first end of the filter capacitor is connected to the second end of the first pull-up resistor, and a second end of the filter capacitor is grounded.
8. The power management circuit of the DDR memory according to claim 5, characterized in that: The power management circuit further includes a second pull-up resistor, a first end of the second pull-up resistor is connected to a power source, and a second end of the second pull-up resistor is connected to a drain of the third NMOS transistor and a gate of the second NMOS transistor.
9. The power management circuit of the DDR memory according to claim 2, characterized in that: The connection unit includes a first resistor, a first end of the first resistor is connected to the control end of the secondary switch unit and a power supply, and a second end of the first resistor is connected to the first end of the primary switch unit.
10. A NAS device, characterized in that: The invention comprises a DDR memory and a power management circuit of the DDR memory as claimed in any one of claims 1 to 9, wherein a voltage reduction unit of the power management circuit is connected to the DDR memory.