Chip packaging structure

Abstract

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package on and electrically connected to the wiring substrate. The chip package structure includes a first anti-warp structure bonded to the wiring substrate. The first anti-warping structure is made of a semiconductor material, and the first anti-warping structure is electrically insulated from a wiring structure of the chip package and wiring substrate. The chip package structure includes a heat dissipation structure on the wiring substrate and surrounding the chip package and the first anti-warping structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to a chip packaging structure, and more particularly to an anti-warping structure contained therein. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing integrated circuits.

[0003] In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit chip area) generally increases as the geometry size (i.e., the smallest component or circuit that can be produced by the manufacturing process used) decreases. The shrinking process size is conducive to increasing production capacity and reducing related costs.

[0004] However, the continued reduction in structure size has made the manufacturing process increasingly difficult, and thus, forming reliable semiconductor devices with increasingly smaller sizes has become a major challenge. Utility Model Content

[0005] In some embodiments, a chip packaging structure is provided. The chip packaging structure includes a wiring substrate. The chip packaging structure includes a chip package located on the wiring substrate and electrically connected to the wiring substrate. The chip packaging structure includes a first anti-warping structure bonded to the wiring substrate. The first anti-warping structure is composed of a semiconductor material, and the first anti-warping structure is electrically insulated from the chip package and the wiring structure of the wiring substrate. The chip packaging structure includes a heat dissipation structure located on the wiring substrate and surrounding the chip package and the first anti-warping structure.

[0006] In some embodiments, the chip packaging structure further includes an adhesive layer located between the first anti-warping structure and the wiring substrate.

[0007] In some embodiments, the chip packaging structure further includes a second anti-warping structure bonded to the wiring substrate, wherein the second anti-warping structure is electrically insulated from the wiring structure of the wiring substrate, the chip packaging, and the first anti-warping structure, and the heat dissipation structure further surrounds the second anti-warping structure.

[0008] In some embodiments, the first anti-warping structure is thicker than the second anti-warping structure.

[0009] In some embodiments, the first anti-warping structure is wider than the second anti-warping structure.

[0010] In some embodiments, the first anti-warpage structure surrounds a first corner portion of the chip package.

[0011] In some embodiments, the chip package has a side wall, the first corner portion and a second corner portion of the chip package are located on opposite sides of the side wall, the second anti-warping structure is located between the first corner portion and the second corner portion and extends along the side wall, and the second anti-warping structure is separated from the chip package.

[0012] In some embodiments, the first anti-warping structure is L-shaped.

[0013] In some embodiments, a chip packaging structure is provided. The chip packaging structure includes a wiring substrate. The chip packaging structure includes a chip package located on the wiring substrate and electrically connected to the wiring substrate. The chip packaging structure includes a first anti-warping structure bonded to the wiring substrate. The first anti-warping structure is electrically insulated from the chip package. The chip packaging structure includes a second anti-warping structure bonded to the wiring substrate. The second anti-warping structure is electrically insulated from the chip package and the first anti-warping structure, and the second anti-warping structure is thinner than the first anti-warping structure. The chip packaging structure includes a heat dissipation structure located on the wiring substrate and surrounding the chip package, the first anti-warping structure, and the second anti-warping structure.

[0014] In some embodiments, the second anti-warping structure is narrower than the first anti-warping structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1A to 1D FIG. 1 is a cross-sectional view of various stages of a process for forming a chip package structure in some embodiments.

[0016] Figure 1A-1 to Figure 1D-1 In some embodiments, Figures 1A to 1D A top view of a chip packaging structure.

[0017] Figure 2A is a cross-sectional view of a chip packaging structure in some embodiments.

[0018] Figure 2B In some embodiments, Figure 2A A top view of a chip packaging structure.

[0019] Figure 3A is a cross-sectional view of a chip packaging structure in some embodiments.

[0020] Figure 3B In some embodiments, Figure 3A A top view of a chip packaging structure.

[0021] Figure 4A is a cross-sectional view of a chip packaging structure in some embodiments.

[0022] Figure 4B In some embodiments, Figure 4A A top view of a chip packaging structure.

[0023] Figure 5A FIG. 4 is a top view of a chip packaging structure in some embodiments.

[0024] Figure 5B In some embodiments, the chip packaging structure is along Figure 5A Cross-sectional view along the section line II'.

[0025] Figure 5C In some embodiments, the chip packaging structure is along Figure 5A Cross-sectional view along the section line II-II'.

[0026] Figure 5D In some embodiments, the chip packaging structure is along Figure 5A Cross-sectional view along section line III-III'.

[0027] Figure 5E In some embodiments, the chip packaging structure is along Figure 5A Cross-sectional view along section line IV-IV'.

[0028] Fig. 5F In some embodiments, the chip packaging structure is along Figure 5A Sectional view along the section line V-V'.

[0029] Figure 5G In some embodiments, the chip packaging structure is along Figure 5A Cross-sectional view along the section line VI-VI'.

[0030] Fig. 6A FIG. 4 is a top view of a chip packaging structure in some embodiments.

[0031] Figure 6B In some embodiments, the chip packaging structure is along Fig. 6A Cross-sectional view along the section line II'.

[0032] Figure 6C In some embodiments, the chip packaging structure is along Fig. 6A Cross-sectional view along the section line II-II'.

[0033] Fig. 7A is a cross-sectional view of a chip packaging structure in some embodiments.

[0034] Figure 7B In some embodiments, Fig. 7A A top view of a chip packaging structure.

[0035] Fig. 8A is a cross-sectional view of a chip packaging structure in some embodiments.

[0036] Figure 8B In some embodiments, Fig. 8A A top view of a chip packaging structure.

[0037] Fig. 9A is a cross-sectional view of a chip packaging structure in some embodiments.

[0038] Fig. 9B In some embodiments, Fig. 9A A top view of a chip packaging structure.

[0039] Fig. 10A is a cross-sectional view of a chip packaging structure in some embodiments.

[0040] Fig. 10B In some embodiments, Fig. 10A A top view of a chip packaging structure.

[0041] Fig.11A FIG. 4 is a top view of a chip packaging structure in some embodiments.

[0042] Fig. 11B In some embodiments, the chip packaging structure is along Fig.11A Cross-sectional view along the section line II'.

[0043] Fig. 11C In some embodiments, the chip packaging structure is along Fig.11A Cross-sectional view along the section line II-II'.

[0044] Fig.11D In some embodiments, the chip packaging structure is along Fig.11A Cross-sectional view along section line III-III'.

[0045] Fig.11E In some embodiments, the chip packaging structure is along Fig.11A Cross-sectional view along section line IV-IV'.

[0046] Fig.11F In some embodiments, the chip packaging structure is along Fig.11A Sectional view along the section line V-V'.

[0047] Fig.11G In some embodiments, the chip packaging structure is along Fig.11A Cross-sectional view along the section line VI-VI'.

[0048] Fig. 12A FIG. 4 is a top view of a chip packaging structure in some embodiments.

[0049] Fig. 12B In some embodiments, the chip packaging structure is along Fig. 12A Cross-sectional view along the section line II'.

[0050] Fig. 12C In some embodiments, the chip packaging structure is along Fig. 12A Cross-sectional view along the section line II-II'.

[0051] The reference numerals are described as follows:

[0052] A: Heat dissipation structure

[0053] C: Corner part

[0054] D1: Distance

[0055] G1: Clearance

[0056] I-I', II-II', III-III', IV-IV', V-V', VI-VI': hatching line

[0057] L161, L163, L164: Length

[0058] T161, T162, T167, T169: thickness

[0059] W161, W164: Width

[0060] W167, W169: Line width

[0061] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200: chip packaging structure

[0062] 110: Wiring substrate

[0063] 111, 121a: lower surface

[0064] 112: Wiring layer

[0065] 114: Conductive vias

[0066] 116: Dielectric layer

[0067] 117: Bonding pad

[0068] 118: Dummy bonding pad

[0069] 119: Wiring structure

[0070] 120: Chip packaging

[0071] 121: Intermediate substrate

[0072] 122, 123: Chip

[0073] 124,710: Conductive bumps

[0074] 125: Insulation structure

[0075] 125a, 140, 720: bottom fill layer

[0076] 125b: Forming layer

[0077] 126: Sidewall

[0078] 130, 230: Solder bumps

[0079] 150, 170, 190, 210, 510: Adhesive layer

[0080] 161, 162, 163, 164, 167, 169: Anti-warping structure

[0081] 161a, 162a: bottom surface of semiconductor

[0082] 167a, 169a, 169b: Partial

[0083] 172, 182: Opening

[0084] 180: Ring structure

[0085] 220: Cover DETAILED DESCRIPTION

[0086] The following detailed description may be accompanied by drawings to facilitate understanding of various aspects of the present invention. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common practice in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for clarity of description.

[0087] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. These specific examples are not intended to limit the embodiments of the present invention. For example, if the embodiment of the present invention describes that a first structure is formed on a second structure, it means that the first structure may be in direct contact with the second structure, or an additional structure may be formed between the first structure and the second structure so that the first structure is not in direct contact with the second structure. In addition, multiple examples of the present invention may be repeatedly labeled to simplify the description or make the description clear, which does not mean that structures with the same labels in multiple embodiments and / or settings have the same relative relationship.

[0088] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or the like are used to describe the relationship of some elements or structures to another element or structure in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated in a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted based on the orientation.

[0089] Some embodiments of the present invention are described. Additional steps may be provided before, during, and / or after the stages described in these embodiments. Different embodiments may replace or omit some of the stages described. Additional structures may be added to the semiconductor device structure. Different embodiments may replace or omit some of the structures described below. Although some embodiments perform steps in a specific order, these steps may be performed in any logical order.

[0090] Figures 1A to 1D are cross-sectional views of various stages of a process for forming a chip package structure in some embodiments. Figure 1A-1 to Figure 1D-1 In some embodiments, Figures 1A to 1D A top view of a chip packaging structure. Figures 1A to 1D In some embodiments, the semiconductor device structure is along Figure 1A-1 to Figure 1D-1 Cross-sectional view along section line I-I'.

[0091] like Figure 1A and Figure 1A-1 In some embodiments shown, a wiring substrate 110 is provided. In some embodiments, the wiring substrate 110 includes a wiring layer 112, a conductive via 114, a dielectric layer 116, and a bonding pad 117. In some embodiments, the wiring layer 112 and the conductive via 114 are formed in the dielectric layer 116.

[0092] In some embodiments, the bonding pad 117 is located on the dielectric layer 116. Figure 1A In some embodiments shown, the conductive vias 114 are electrically connected between different wiring layers 112, and between the wiring layers 112 and the bonding pads 117. In some embodiments, to simplify the drawings, Figure 1A Only two wiring layers 112 are shown.

[0093] In some embodiments, the dielectric layer 116 is composed of an insulating material such as a polymer material (eg, polybenzoxazole, polyimide, or photosensitive material), a nitride (eg, silicon nitride), an oxide (eg, silicon oxide), silicon oxynitride, or the like.

[0094] In some embodiments, the dielectric layer 116 may be formed by a deposition process (such as a chemical vapor deposition process or a physical vapor deposition process), a photolithography process, and an etching process.

[0095] In some embodiments, the wiring layer 112 may be composed of a conductive material such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. In some embodiments, the conductive via 114 may be composed of a conductive material such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof. In some embodiments, the conductive pads such as the bonding pad 117 may be composed of a conductive material such as a metal (e.g., copper, aluminum, or tungsten) or an alloy thereof.

[0096] In some embodiments, the conductive pads such as the bonding pad 117, the wiring layer 112, and the conductive via 114 are made of the same material. In some other embodiments, the conductive pads such as the bonding pad 117, the wiring layer 112, and the conductive via 114 are made of different materials.

[0097] like Figure 1A and Figure 1A-1 Some embodiments shown provide a chip package 120. The chip package 120 includes an interposer substrate 121, chips 122 and 123, conductive bumps 124, an underfill layer 125a, and a molding layer 125b.

[0098] In some embodiments, the interposer substrate 121 includes a semiconductor substrate (not shown), two interconnect structures (not shown) respectively located above and below the semiconductor substrate, and a conductive via (not shown) passing through the semiconductor substrate.

[0099] In some embodiments, each interconnect structure includes a wiring layer, a conductive via, a bonding pad, and a dielectric layer. In some embodiments, the wiring layer and the conductive via are formed in the dielectric layer. In some embodiments, the bonding pad is located on the dielectric layer. In some embodiments, the conductive via is electrically connected between different wiring layers and bonding pads.

[0100] In some embodiments, the dielectric layer is composed of an insulating material such as a polymer material (eg, polybenzoxazole, polyimide, or photosensitive material), a nitride (eg, silicon nitride), an oxide (eg, silicon oxide), silicon oxynitride, or the like.

[0101] In some embodiments, the dielectric layer may be formed by a deposition process (such as a chemical vapor deposition process or a physical vapor deposition process), a photolithography process, and an etching process. In some embodiments, the wiring layer, the conductive vias, and the bonding pads are made of a conductive material such as a metal (such as copper, aluminum, or tungsten) or an alloy thereof.

[0102] In some embodiments, the chips 122 and 123 are bonded to the bonding pads of the interposer substrate 121 via the conductive bumps 124. In some embodiments, the chips 122 and 123 are separated from each other by a gap G1. The chips 122 and 123 may be different chips with different functions.

[0103] In some embodiments, conductive bumps 124 are physically and electrically connected between chips 122 and 123 and interposer substrate 121. Chips 122 and 123 include system on chip (SoC), high-performance computing chips, or another suitable chip.

[0104] In some embodiments, each of the chips 122 and 123 includes a semiconductor substrate and an interconnect structure on the semiconductor substrate. In some embodiments, the semiconductor substrate is made of semiconductor element materials, such as silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0105] In some other embodiments, the semiconductor substrate is composed of a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), a semiconductor alloy (such as silicon germanium or gallium arsenide phosphide), or a combination thereof. The semiconductor substrate may also include a multi-layer semiconductor, a semiconductor on an insulating layer (such as silicon on an insulating layer or germanium on an insulating layer), or a combination thereof.

[0106] In some embodiments, the semiconductor substrate includes a plurality of device units. In some embodiments, the plurality of device units are formed in and / or on the semiconductor substrate. The device units are not shown in the drawings for simplicity and clarity.

[0107] Examples of various device units include active devices, passive devices, other suitable units, or combinations thereof. Active devices may include transistors or diodes (not shown) formed on the surface of a semiconductor substrate. Passive devices include resistors, capacitors, or other suitable passive devices.

[0108] For example, the transistor may be a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor transistor, a bipolar junction transistor, a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor, or the like.

[0109] Various processes such as front-end semiconductor manufacturing processes may be performed to form various device units. The front-end semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other possible processes, or a combination thereof.

[0110] In some embodiments, an isolation structure (not shown) is formed in the semiconductor substrate. The isolation structure is used to define an active region and electrically isolate various devices in and / or on the semiconductor substrate in the active region. In some embodiments, the isolation structure includes a shallow trench isolation structure, a local silicon oxide structure, other suitable isolation structures, or a combination thereof.

[0111] In some embodiments, the conductive bump 124 is made of a conductive material such as copper, aluminum, tungsten, cobalt, nickel, or tin. In some embodiments, the conductive bump 124 can be formed by a plating process such as an electroplating process.

[0112] In some embodiments, the chip package 120 may be formed by a chip-on-wafer-on-substrate process (CoWoS). The chip package 120 may be a chip package of the type of wafer-on-wafer-on-substrate-silicon-substrate (CoWoS-S), but the embodiments of the present invention are not limited thereto. The chip package 120 may be other types of chip packages. For example, the intermediate substrate 121 may be replaced with a redistribution substrate to form a chip package of the type of wafer-on-wafer-on-substrate-redistribution (CoWoS-R). In some embodiments, a chip (not shown) is formed in a redistribution substrate to form a chip package of the type of wafer-on-wafer-on-substrate-local-silicon-interconnect (CoWoS-LSI). In some embodiments, the chip package 120 is replaced with an integrated fan-out (InFO) chip package.

[0113] like Figure 1A In some embodiments shown, the underfill layer 125a is formed between the chips 122 and 123 and the interposer substrate 121. In some embodiments, the underfill layer 125a surrounds the conductive bumps 124 and the chips 122 and 123.

[0114] In some embodiments, the underfill layer 125a extends to the gap G1. In some embodiments, the underfill layer 125a fills the gap G1. In some embodiments, the underfill layer 125a is made of an insulating material such as a polymer material.

[0115] like Figure 1A In some embodiments shown, the molding layer 125b is formed on the interposer substrate 121. In some embodiments, the molding layer 125b surrounds the chips 122 and 123, the conductive bumps 124, and the underfill layer 125a.

[0116] In some embodiments, the molding layer 125 b is made of an insulating material such as a polymer material (such as epoxy). In some embodiments, the molding layer 125 b and the underfill layer 125 a are made of different materials. In some embodiments, the molding layer 125 b and the underfill layer 125 a together form the insulating structure 125 .

[0117] like Figure 1A In some embodiments shown, solder bumps 130 are formed on the lower surface 121a of the interposer substrate 121. In some embodiments, the solder bumps 130 are made of tin or another suitable conductive material. In some embodiments, the solder bumps 130 are formed by a plating process such as an electroplating process.

[0118] like Figure 1A and Figure 1A-1In some embodiments shown, the chip package 120 is bonded to the wiring substrate 110 via solder bumps 130. In some embodiments, the chip package 120 is electrically connected to the wiring substrate 110 via solder bumps 130. In some embodiments, the solder bumps 130 are bonded to the bonding pads 117 of the wiring substrate 110.

[0119] like Figure 1B and Figure 1B-1 In some embodiments shown, the underfill layer 140 is formed between the chip package 120 and the wiring substrate 110. In some embodiments, the underfill layer 140 surrounds the solder bumps 130 and the chip package 120. In some embodiments, the underfill layer 140 is made of an insulating material such as a polymer material.

[0120] like Figure 1B and Figure 1B-1 In some embodiments shown, the adhesive layer 150 is formed on the wiring substrate 110. In some embodiments, the adhesive layer 150 is composed of a polymer material such as epoxy or silicone.

[0121] like Figure 1B and Figure 1B-1 In some embodiments shown, the anti-warping structure 161 is bonded to the wiring substrate 110 via the adhesive layer 150. In some embodiments, the adhesive layer 150 is located between the anti-warping structure 161 and the wiring substrate 110. In some embodiments, the anti-warping structure 161 is electrically insulated from the wiring substrate 110 and the chip package 120.

[0122] In some embodiments, the anti-warping structure 161 has a semiconductor lower surface 161 a, and the adhesive layer 150 contacts the semiconductor lower surface 161 a. In some embodiments, a distance D1 between the anti-warping structure 161 and the chip package 120 is about 500 microns to about 2000 microns.

[0123] In some embodiments, if the distance D1 is greater than 2000 microns, the distance D1 is too large to reduce the size of the overall chip package structure. In some embodiments, if the distance D1 is less than 500 microns, the distance D1 is too small to cause the anti-warping structure 161 and the chip package 120 to interfere with each other.

[0124] In some embodiments, the anti-warping structure is composed of a semiconductor material. In some embodiments, all anti-warping structures 161 are composed of a semiconductor material. The semiconductor material includes semiconductor element materials such as silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0125] In some other embodiments, the anti-warping structure 161 is composed of a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), a semiconductor alloy (such as silicon germanium or gallium arsenide phosphide), or a combination thereof. The anti-warping structure 161 may also include a multi-layer semiconductor, a semiconductor on an insulating layer (such as silicon on an insulating layer or germanium on an insulating layer), or a combination thereof.

[0126] In some embodiments, if the anti-warping structure 161 is composed of semiconductor material, the thermal expansion coefficient of the anti-warping structure 161 is similar to or substantially the same as the thermal expansion coefficient of the semiconductor substrate of chips 122 and 123, which can reduce the difference in thermal expansion coefficients between the anti-warping structure 161 and chips 122 and 123, thereby reducing the warping of the wiring substrate 110.

[0127] In some other embodiments, the thermal expansion coefficient of the material of the anti-warping structure 161 is smaller than the thermal expansion coefficient of the wiring substrate 110. For example, in some embodiments, the anti-warping structure 161 is made of metal.

[0128] like Figure 1C and Figure 1C-1 In some embodiments shown, the adhesive layer 170 is formed on the wiring substrate 110. In some embodiments, the adhesive layer 170 has an opening 172. In some embodiments, the chip package 120 is located in the opening 172. In some embodiments, the adhesive layer 170 is composed of a polymer material such as epoxy or silicone.

[0129] like Figure 1C and Figure 1C-1 In some embodiments shown, the annular structure 180 is located on the adhesive layer 170. Figure 1C and Figure 1C-1 In some embodiments shown, the ring structure 180 has an opening 182. In some embodiments, the opening 182 is substantially rectangular.

[0130] like Figure 1C and Figure 1C-1 In some embodiments shown, the opening 172 of the adhesive layer 170 is below the opening 182. Figure 1C and Figure 1C-1 In some embodiments shown, the chip package 120 is located in the opening 182. In some embodiments, the ring structure 180 surrounds the chip package 120 and the anti-warping structure 161.

[0131] In some embodiments, the ring structure 180 is made of a rigid material such as metal (e.g., copper or iron), an alloy thereof (e.g., stainless steel), or another suitable material, which is more rigid than the wiring substrate 110. In some embodiments, the ring structure 180 is made of a highly thermally conductive material such as metal.

[0132] like Figure 1D and Figure 1D-1 In some embodiments shown, an adhesive layer 190 is formed on the annular structure 180. In some embodiments, the adhesive layer 190 is composed of a polymer material such as epoxy or silicone.

[0133] like Figure 1D and Figure 1D-1 In some embodiments shown, the adhesive layer 210 is formed on the chip package 120. In some embodiments, the adhesive layer 210 is composed of a polymer material (such as epoxy or silicone) and a high thermal conductivity material. The high thermal conductivity material includes a metal material such as silver, gold, or another suitable material.

[0134] like Figure 1D and Figure 1D-1 In some embodiments shown, cover 220 is located on adhesive layers 190 and 210. In some embodiments, cover 220 is made of a rigid material such as metal (such as copper or iron), alloys thereof (such as stainless steel), or another suitable material, which is more rigid than wiring substrate 110.

[0135] In some embodiments, the cover 220 is made of a highly thermally conductive material such as metal. In some embodiments, the annular structure 180 , the adhesive layer 190 , and the cover 220 together form a heat dissipation structure A.

[0136] like Figure 1D and Figure 1D-1 In the illustrated embodiment, the solder bumps 230 are formed on the lower surface 111 of the wiring substrate 110 . In some embodiments, the solder bumps 230 are electrically connected to the wiring layer 112 and the conductive vias 114 .

[0137] In some embodiments, the solder bump 230 is made of tin or another suitable conductive material. In some embodiments, the solder bump 230 is formed by a plating process such as an electroplating process. In some embodiments, this step substantially forms the chip package structure 100.

[0138] Figure 2A is a cross-sectional view of a chip package structure 200 in some embodiments. Figure 2B In some embodiments, Figure 2A FIG. 1 is a top view of the chip package structure 200 . Figure 2A In some embodiments, the chip package structure 200 is arranged along Figure 2B Cross-sectional view along the section line II'.

[0139] like Figure 2A and Figure 2B In some embodiments shown in FIG. 1 , the chip package structure 200 is Figure 1D and Figure 1D-1The chip package structure 200 is similar to the chip package structure 100 , except that the chip package structure 200 further includes an anti-warping structure 162 . In some embodiments, the anti-warping structure 162 is bonded to the wiring substrate 110 via an adhesive layer 150 .

[0140] In some embodiments, the anti-warping structure 162 is separated from the anti-warping structure 161. In some embodiments, the anti-warping structures 161 and 162 are located on opposite sides of the chip package 120. In some embodiments, the anti-warping structures 161 and 162 are separated from the chip package 120. In some embodiments, the anti-warping structures 161 and 162 have the same thickness.

[0141] In some embodiments, the anti-warping structure 162 is made of semiconductor material. In some embodiments, all anti-warping structures 162 are made of semiconductor material. Semiconductor material includes semiconductor element material such as silicon or germanium in single crystal structure, polycrystalline structure, or amorphous structure.

[0142] In some other embodiments, the anti-warping structure 162 is made of a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), a semiconductor alloy (such as silicon germanium or gallium arsenide phosphide), or a combination thereof.

[0143] The anti-warping structure 162 may also include multi-layer semiconductors, semiconductors on insulating layers (such as silicon on insulating layers or germanium on insulating layers), or combinations thereof. In some other embodiments, the anti-warping structure 162 is made of metal.

[0144] In some embodiments, the anti-warping structures 161 and 162 are made of the same material. In some embodiments, the anti-warping structures 161 and 162 are made of different materials.

[0145] Figure 3A is a cross-sectional view of a chip package structure 300 in some embodiments. Figure 3B In some embodiments, Figure 3A FIG. 1 is a top view of a chip package structure 300 . Figure 3A In some embodiments, the chip package structure 300 is arranged along Figure 3B Cross-sectional view along the section line II'.

[0146] like Figure 3A and Figure 3B In some embodiments shown in FIG. 1 , the chip package structure 300 is Figure 2A and Figure 2B The chip package structure 300 is similar to the chip package structure 200 , except that the thickness T162 of the anti-warping structure 162 in the chip package structure 300 is smaller than the thickness T161 of the anti-warping structure 161 .

[0147] In some embodiments, the anti-warping capability of the thicker anti-warping structure 161 is greater than the anti-warping capability of the thinner anti-warping structure 162. In some embodiments, the anti-warping structure 161 is located on a first portion of the wiring substrate 110, and the first portion is originally prone to large warping. In some embodiments, the anti-warping structure 162 is located on a second portion of the wiring substrate 110, and the second portion is originally prone to small warping. Therefore, in some embodiments, the configuration of the anti-warping structures 161 and 162 can locally reduce the warping of the wiring substrate 110, which can improve the coplanarity of the solder bump 230. In some embodiments, the formation of the anti-warping structures 161 and 162 can improve design flexibility.

[0148] Figure 4A is a cross-sectional view of a chip package structure 400 in some embodiments. Figure 4B In some embodiments, Figure 4A FIG. 4 is a top view of a chip package structure 400 . Figure 4A In some embodiments, the chip package structure 400 is arranged along Figure 4B Cross-sectional view along the section line II'.

[0149] like Figure 4A and Figure 4B In some embodiments shown in FIG. 4 , the chip package structure 400 is Figure 3A and Figure 3B The chip package structure 400 is similar to the chip package structure 300, except that the chip package structure 400 further includes anti-warping structures 163 and 164. In some embodiments, the sizes of the anti-warping structures 161 (or 162), 163, and 164 are different from each other.

[0150] For example, in some embodiments, the length L161 of the anti-warping structure 161 is greater than the length L164 of the anti-warping structure 164, and the length L164 is greater than the length L163 of the anti-warping structure 163. In some embodiments, the width W164 of the anti-warping structure 164 is greater than the width W161 of the anti-warping structure 161.

[0151] In some embodiments, the larger the anti-warping structure, the stronger the anti-warping capability. Therefore, in some embodiments, the configuration of the anti-warping structures 161, 162, 163, and 164 can be adjusted to minimize the warping of the wiring substrate 110 according to the different warping possibilities of different parts of the wiring substrate 110, which can improve the coplanarity of the solder bumps 230. In some embodiments, the anti-warping structures 163 and 164 are composed of semiconductor materials or metal materials.

[0152] Figure 5A FIG. 5 is a top view of the chip package structure 500 in some embodiments. Figure 5B In some embodiments, the chip package structure 500 is arranged along Figure 5ACross-sectional view along the section line II'. Figure 5C In some embodiments, the chip package structure 500 is arranged along Figure 5A Cross-sectional view along the section line II-II'.

[0153] Figure 5D In some embodiments, the chip package structure 500 is arranged along Figure 5A Cross-sectional view along section line III-III'. Figure 5E In some embodiments, the chip package structure 500 is arranged along Figure 5A Cross-sectional view along section line IV-IV'.

[0154] Fig. 5F In some embodiments, the chip package structure 500 is arranged along Figure 5A Sectional view along the section line V-V'. Figure 5G In some embodiments, the chip package structure 500 is arranged along Figure 5A Cross-sectional view along the section line VI-VI'.

[0155] like Figure 5A and Figure 5B In some embodiments shown in FIG. 1 , the chip package structure 500 is Figure 4A and Figure 4B The chip package structure 500 is similar to the chip package structure 400 , except that the chip package structure 500 further includes the anti-warping structures 167 and 169 and the adhesive layer 510 , but does not include the anti-warping structures 161 and 162 .

[0156] In some embodiments, the anti-warping structure 167 is bonded to the wiring substrate 110 via the adhesive layer 150. In some embodiments, the anti-warping structure 167 is electrically insulated from the wiring substrate 110 and the chip package 120. In some embodiments, the material composition of the anti-warping structure is similar to that of the Figure 1D The material composition of the anti-warping structure 161 is the same.

[0157] like Figure 5A In some embodiments shown in FIG. 1 , the line width W169 of the anti-warping structure 169 is greater than the line width W167 of the anti-warping structure 167. Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F ,and Figure 5G In some embodiments shown, the thickness T169 of the anti-warping structure 169 is greater than the thickness T167 of the anti-warping structure 167 .

[0158] Therefore, in some embodiments, the anti-warping capability of the anti-warping structure 169 is greater than the anti-warping capability of the anti-warping structure 167. In some embodiments, the anti-warping structure 169 is located on a portion of the wiring substrate 110 that is prone to large warping. In some embodiments, the anti-warping structure 167 is located on a portion of the wiring substrate 110 that is prone to small warping.

[0159] like Figure 5A In some embodiments shown, the chip package 120 has corner portions C and sidewalls 126. In some embodiments, the sidewalls 126 are located between the corner portions C. In some embodiments, since a first portion of the wiring substrate 110 adjacent to the sidewalls 126 is prone to small warpage, the anti-warpage structure 167 is located on the first portion.

[0160] In some embodiments, the anti-warping structure 167 is located between two corner portions C. In some embodiments, the anti-warping structure 167 extends along the corresponding sidewall 126 . In some embodiments, the anti-warping structure 167 is separated from the chip package 120 .

[0161] In some embodiments, since the second portion of the wiring substrate 110 is adjacent to the corner portion C and is prone to large warping, the anti-warping structure 169 is located on the second portion. In some embodiments, the anti-warping structures 169 surround the corner portions C respectively. In some embodiments, the anti-warping structures 169 are L-shaped. In some embodiments, the anti-warping structures 167 and 169 are made of semiconductor materials or metal materials.

[0162] In some embodiments, the adhesive layer 510 is bonded between the anti-warping structure 169 and the cover 220 . In some embodiments, the method of forming the adhesive layer 510 may include forming the adhesive layer 510 on the anti-warping structure 169 and bonding the cover 220 to the adhesive layer 510 .

[0163] In some embodiments, the adhesive layer 510 is made of a polymer material such as epoxy or silicone. In some embodiments, the adhesive layer 510 can fix the anti-warping structure 169 to the cover 220 , which can improve the anti-warping capability of the anti-warping structure 169 .

[0164] Fig. 6A FIG. 6 is a top view of the chip package structure 600 in some embodiments. Figure 6B In some embodiments, the chip package structure 600 is arranged along Fig. 6A Cross-sectional view along the section line II'. Figure 6C In some embodiments, the chip package structure 600 is arranged along Fig. 6A Cross-sectional view along the section line II-II'.

[0165] like Fig. 6A , Figure 6B ,and Figure 6C In some embodiments shown, the chip package structure 600 and Figure 5A , Fig. 5F ,and Figure 5G The chip package structure 500 is similar to the chip package structure 600 , except that the anti-warping structure 167 in the chip package structure 600 has a portion 167 a , and the anti-warping structure 169 has portions 169 a and 169 b .

[0166] In some embodiments, the portions 167a are separated from each other. In some embodiments, the portions 167a are disposed along the corresponding sidewalls 126 of the chip package 120. In some embodiments, in one of the anti-warping structures 169, the portions 169a and 169b are separated from each other.

[0167] In one of the anti-warping structures 169 of some embodiments, the portion 169 a extends along one of the sidewalls 126 , the portion 169 b extends along the other of the sidewalls 126 , and the one of the sidewalls 126 meets the other to form a corner portion C.

[0168] In some embodiments, since the photolithography process and the etching process are used to easily form a straight line structure, the straight line portions 167a, 169a, and 169b and the anti-warping structure 167 can be easily formed, which can improve the yield of the portions 167a, 169a, and 169b and the anti-warping structure 167.

[0169] Fig. 7A is a cross-sectional view of a chip package structure 700 in some embodiments. Figure 7B In some embodiments, Fig. 7A FIG. 7 is a top view of a chip package structure 700 . Fig. 7A In some embodiments, the chip package structure 700 is arranged along Figure 7B Cross-sectional view along the section line II'.

[0170] like Fig. 7A and Figure 7B In some embodiments shown in FIG. 7 , the chip package structure 700 is Figure 1D and Figure 1D-1 The chip package structure 700 is similar to the chip package structure 100 , except that the chip package structure 700 further includes a conductive bump 710 and an underfill layer 720 , but does not include the adhesive layer 150 of the chip package structure 100 .

[0171] In some embodiments, the anti-warping structure 161 is bonded to the wiring substrate 110 via the conductive bump 710. In some embodiments, the conductive bump 710 is located between the anti-warping structure 161 and the wiring substrate 110. In some embodiments, the conductive bump 710 contacts the semiconductor lower surface 161a of the anti-warping structure 161.

[0172] In some embodiments, the wiring substrate 110 further includes a dummy bonding pad 118 on the dielectric layer 116. In some embodiments, the conductive bump 710 is bonded to the dummy bonding pad 118. In some embodiments, the anti-warping structure 161 is electrically insulated from the wiring structure 119 of the wiring substrate 110 and the chip package 120. In some embodiments, the wiring structure 119 includes all conductive vias 114 and all wiring layers 112 of the wiring substrate 110.

[0173] In some embodiments, the conductive bump 710 is made of a conductive material such as copper, aluminum, tungsten, cobalt, nickel, or tin. In some embodiments, the conductive bump 710 can be formed by a plating process such as an electroplating process.

[0174] In some embodiments, the underfill layer 720 is located between the anti-warping structure 161 and the wiring substrate 110. In some embodiments, the underfill layer 720 surrounds the conductive bump 710 and the anti-warping structure 161. In some embodiments, the underfill layer 720 is made of an insulating material such as a polymer material.

[0175] Fig. 8A is a cross-sectional view of a chip package structure 800 in some embodiments. Figure 8B In some embodiments, Fig. 8A FIG. 8 is a top view of a chip package structure 800 . Fig. 8A In some embodiments, the chip package structure 800 is arranged along Figure 8B Cross-sectional view along the section line II'.

[0176] like Fig. 8A and Figure 8B In some embodiments shown, the chip package structure 800 and Figure 2A and Figure 2B The chip package structure 800 is similar to the chip package structure 200 , except that the chip package structure 800 further includes a conductive bump 710 and an underfill layer 720 , but does not include the adhesive layer 150 of the chip package structure 200 .

[0177] In some embodiments, the anti-warping structures 161 and 162 are bonded to the wiring substrate 110 via the conductive bumps 710. In some embodiments, the conductive bumps 710 are located between the anti-warping structures 161 and 162 and the wiring substrate 110. In some embodiments, the conductive bumps 710 contact the semiconductor lower surfaces 161a and 162a of the anti-warping structures 161 and 162.

[0178] In some embodiments, the wiring substrate 110 further includes a dummy bonding pad 118. In some embodiments, the conductive bump 710 is bonded to the dummy bonding pad 118. In some embodiments, the anti-warping structures 161 and 162 are electrically insulated from the wiring structure 119 of the wiring substrate 110 and the chip package 120.

[0179] In some embodiments, the underfill layer 720 is located between the anti-warping structure 161 and the wiring substrate 110 and between the anti-warping structure 162 and the wiring substrate 110. In some embodiments, the underfill layer 720 surrounds the conductive bump 710 and the anti-warping structures 161 and 162. In some embodiments, the underfill layer 720 is made of an insulating material such as a polymer material.

[0180] Fig. 9A is a cross-sectional view of a chip package structure 900 in some embodiments. Fig. 9B In some embodiments, Fig. 9A FIG. 9 is a top view of a chip package structure 900 . Fig. 9A In some embodiments, the chip package structure 900 is arranged along Fig. 9B Cross-sectional view along the section line II'.

[0181] like Fig. 9A and Fig. 9B In some embodiments shown in FIG. 1 , the chip package structure 900 is Fig. 8A and Figure 8B The chip package structure 800 is similar to the chip package structure 800 , except that the thickness T162 of the anti-warping structure 162 is smaller than the thickness T161 of the anti-warping structure 161 in the chip package structure 900 .

[0182] Fig. 10A is a cross-sectional view of a chip package structure 1000 in some embodiments. Fig. 10B In some embodiments, Fig. 10A FIG. 1 is a top view of the chip package structure 1000 . Fig. 10A In some embodiments, the chip package structure 1000 is arranged along Fig. 10B Cross-sectional view along the section line II'.

[0183] like Fig. 10A and Fig. 10B In some embodiments shown in FIG. 1 , the chip package structure 1000 and Fig. 9A and Fig. 9B The chip package structure 1000 is similar to the chip package structure 900, except that the chip package structure 1000 further includes anti-warping structures 163 and 164. In some embodiments, the sizes of the anti-warping structures 161 (or 162), 163, and 164 are different from each other.

[0184] Fig.11A FIG. 1 is a top view of the chip package structure 1100 in some embodiments. Fig. 11B In some embodiments, the chip package structure 1100 is arranged along Fig.11A Cross-sectional view along the section line II'. Fig. 11C In some embodiments, the chip package structure 1100 is arranged along Fig.11ACross-sectional view along the section line II-II'.

[0185] Fig.11D In some embodiments, the chip package structure 1100 is arranged along Fig.11A Cross-sectional view along section line III-III'. Fig.11E In some embodiments, the chip package structure 1100 is arranged along Fig.11A Cross-sectional view along section line IV-IV'.

[0186] Fig.11F In some embodiments, the chip package structure 1100 is arranged along Fig.11A Sectional view along the section line V-V'. Fig.11G In some embodiments, the chip package structure 1100 is arranged along Fig.11A Cross-sectional view along the section line VI-VI'.

[0187] like Fig.11A and Fig. 11B In some embodiments shown in FIG. 1 , the chip package structure 1100 and Fig. 8A and Figure 8B The chip package structure 1100 is similar to the chip package structure 800 , except that the chip package structure 1100 further includes anti-warping structures 167 and 169 and an adhesive layer 510 , but does not include the anti-warping structures 161 and 162 .

[0188] In some embodiments, the anti-warping structures 167 and 169 are bonded to the wiring substrate 110 via the conductive bumps 710. In some embodiments, the underfill layer 720 is located between the anti-warping structure 167 and the wiring substrate 110, and between the anti-warping structure 169 and the wiring substrate 110. In some embodiments, the underfill layer 720 surrounds the conductive bumps 710 and the anti-warping structures 167 and 169.

[0189] In some embodiments, the wiring structure 119 of the wiring substrate 110 and the chip package 120 are electrically insulated from the anti-warping structures 167 and 169. In some embodiments, the material composition of the anti-warping structures 167 and 169 can be the same as Figure 1D The material composition of the anti-warping structure 161 is the same.

[0190] like Fig.11A In some embodiments shown in FIG. 1 , the line width W169 of the anti-warping structure 169 is greater than the line width W167 of the anti-warping structure 167. Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F In some embodiments shown in 11G and 11B, the thickness T169 of the anti-warping structure 169 is greater than the thickness T167 of the anti-warping structure 167.

[0191] like Fig.11A In some embodiments shown, the chip package 120 has corner portions C and sidewalls 126. In some embodiments, the sidewalls 126 are located between the corner portions C. In some embodiments, since the wiring substrate 110 adjacent to the sidewalls 126 is prone to small warpage, the anti-warpage structure 126 is located on the first portion.

[0192] In some embodiments, the anti-warping structure 167 is located between two corner portions C. In some embodiments, the anti-warping structure 167 extends along the corresponding sidewall 126 . In some embodiments, the anti-warping structure 167 is separated from the chip package 120 .

[0193] In some embodiments, the anti-warping structure 169 is located on the second portion of the wiring substrate 110 because the second portion is adjacent to the corner portion C and is prone to large warping. In some embodiments, the anti-warping structure 169 surrounds one of the corner portions C. In some embodiments, the anti-warping structure 169 is L-shaped.

[0194] In some embodiments, the adhesive layer 510 is bonded between the anti-warping structure 169 and the cover 220 . In some embodiments, the method of forming the adhesive layer 510 may include forming the adhesive layer 510 on the anti-warping structure 169 and bonding the cover 220 to the adhesive layer 510 .

[0195] In some embodiments, the adhesive layer 510 is made of a polymer material such as oxide or silicone. In some embodiments, the adhesive layer 510 can fix the anti-warping structure 169 to the cover 220 , which can improve the anti-warping capability of the anti-warping structure 169 .

[0196] In some embodiments, the method for forming a chip package structure 1100 includes: joining the chip package 120 to the wiring substrate 110 via the solder bump 130, joining the anti-warping structures 167 and 169 to the wiring substrate 110 via the conductive bump 710, forming bottom filling layers 140 and 720 between the chip package 120 and the wiring substrate 110 and between the anti-warping structures 167 and 169 and the wiring substrate 110, forming an adhesive layer 170 on the wiring substrate 110, placing the annular structure 180 on the adhesive layer 170, forming adhesive layers 190, 210, and 510 on the annular structure 180, the chip package 120, and the anti-warping structure 169, respectively, placing the cover 220 on the adhesive layers 190, 210, and 510, and forming a solder bump 230 on the lower surface 111 of the wiring substrate 110.

[0197] Fig. 12A FIG. 1 is a top view of the chip package structure 1200 in some embodiments. Fig. 12B In some embodiments, the chip package structure 1200 is arranged along Fig. 12A Cross-sectional view along the section line II'. Fig. 12C In some embodiments, the chip package structure 1200 is arranged along Fig. 12A Cross-sectional view along the section line II-II'.

[0198] like Fig. 12A , Fig. 12B ,and Fig. 12C In some embodiments shown in FIG. 1 , the chip package structure 1200 and Fig.11A , Fig.11F ,and Fig.11G The chip package structure 1100 is similar to the chip package structure 1200 , except that the anti-warping structure 167 has a portion 167 a and the anti-warping structure 169 has portions 169 a and 169 b in the chip package structure 1200 .

[0199] In one of the anti-warping structures 167 of some embodiments, the portions 167a are separated from each other. In some embodiments, the portions 167a extend along the corresponding sidewalls 126 of the chip package 120. In one of the anti-warping structures 169 of some embodiments, the portions 169a and 169b are separated from each other.

[0200] In one of the anti-warping structures 169 of some embodiments, portion 169a extends along one of the sidewalls 126, portion 169b extends along the other of the sidewalls 126, and one of the sidewalls 126 meets the other to form one of the corner portions C.

[0201] The processes and materials used to form the chip package structures 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , 1100 , and 1200 may be similar to or the same as the processes and materials used to form the chip package structure 100 . Figures 1A to 12C Units denoted by the same reference numerals may have the same or similar structures and materials. Therefore, the details are not repeated here. In some embodiments, the anti-warping structures 161, 162, 163, 164, 167, and 169 are semiconductor substrates and do not have devices, conductive lines, and conductive vias.

[0202] In some embodiments, a chip packaging structure and a method for forming the same are provided. The method for forming the chip packaging structure forms a first anti-warping structure on a wiring substrate to locally reduce the warping of the wiring substrate, which can improve the coplanarity of solder bumps under the wiring substrate. The method further forms a second anti-warping structure on the wiring substrate, and the second anti-warping structure has a different size from the first anti-warping structure. The first anti-warping structure and the second anti-warping structure have different anti-warping capabilities to improve design flexibility.

[0203] In some embodiments, a chip packaging structure is provided. The chip packaging structure includes a wiring substrate. The chip packaging structure includes a chip package located on the wiring substrate and electrically connected to the wiring substrate. The chip packaging structure includes a first anti-warping structure bonded to the wiring substrate. The first anti-warping structure is composed of a semiconductor material, and the first anti-warping structure is electrically insulated from the chip package and the wiring structure of the wiring substrate. The chip packaging structure includes a heat dissipation structure located on the wiring substrate and surrounding the chip package and the first anti-warping structure.

[0204] In some embodiments, the chip packaging structure further includes an adhesive layer between the first anti-warping structure and the wiring substrate.

[0205] In some embodiments, the chip packaging structure further includes a second anti-warping structure joined to the wiring substrate, wherein the second anti-warping structure is composed of semiconductor material, the second anti-warping structure is electrically insulated from the wiring structure of the wiring substrate, the chip packaging, and the first anti-warping structure, and the heat dissipation structure further surrounds the second anti-warping structure.

[0206] In some embodiments, the first anti-warping structure is thicker than the second anti-warping structure.

[0207] In some embodiments, the first anti-warping structure is wider than the second anti-warping structure.

[0208] In some embodiments, the first anti-warpage structure surrounds a first corner portion of the chip package.

[0209] In some embodiments, the chip package has a side wall, a first corner portion and a second corner portion of the chip package are located on opposite sides of the side wall, a second anti-warping structure is located between the first corner portion and the second corner portion and extends along the side wall, and the second anti-warping structure is separated from the chip package.

[0210] In some embodiments, the first anti-warping structure is L-shaped.

[0211] In some embodiments, the heat dissipation structure has a cover to cover the chip package and the first anti-warping structure, and the chip package structure further includes an adhesive layer located between the first anti-warping structure and the cover.

[0212] In some embodiments, the heat dissipation structure covers the chip package and the first anti-warping structure, and the chip package structure further includes an adhesive layer located between the first anti-warping structure and the heat dissipation structure.

[0213] In some embodiments, the chip packaging structure further includes a first conductive bump located between the first anti-warping structure and the wiring substrate, wherein the first conductive bump contacts the semiconductor bottom surface of the first anti-warping structure.

[0214] In some embodiments, the chip packaging structure further includes a second conductive bump located between the first anti-warping structure and the wiring substrate, wherein the second conductive bump contacts the lower surface of the semiconductor, the wiring substrate includes a dummy bonding pad, and the first conductive bump and the second conductive bump are bonded to the dummy bonding pad.

[0215] In some embodiments, a chip packaging structure is provided. The chip packaging structure includes a wiring substrate. The chip packaging structure includes a chip package located on the wiring substrate and electrically connected to the wiring substrate. The chip packaging structure includes a first anti-warping structure bonded to the wiring substrate. The first anti-warping structure is electrically insulated from the chip package. The chip packaging structure includes a second anti-warping structure bonded to the wiring substrate. The second anti-warping structure is electrically insulated from the chip package and the first anti-warping structure, and the second anti-warping structure is thinner than the first anti-warping structure. The chip packaging structure includes a heat dissipation structure located on the wiring substrate and surrounding the chip package, the first anti-warping structure, and the second anti-warping structure.

[0216] In some embodiments, the second anti-warping structure is narrower than the first anti-warping structure.

[0217] In some embodiments, a method for forming a chip package structure is provided. The method includes bonding the chip package to a wiring substrate. The method includes bonding a first anti-warping structure to the wiring substrate. The first anti-warping structure is composed of a semiconductor material, and the first anti-warping structure is electrically insulated from a wiring structure of the wiring substrate and the chip package. The method includes bonding a heat dissipation structure to the wiring substrate. The heat dissipation structure surrounds the chip package and the first anti-warping structure.

[0218] In some embodiments, the method further includes forming an adhesive layer on the first anti-warping structure, wherein the heat dissipation structure has a cover, and after bonding the heat dissipation structure to the wiring substrate, bonding the adhesive layer to the cover.

[0219] In some embodiments, the step of bonding the first anti-warping structure to the wiring substrate includes bonding the first anti-warping structure to the wiring substrate via a first conductive bump, wherein the first conductive bump is bonded to a dummy bonding pad of the wiring substrate.

[0220] In some embodiments, the step of bonding the first anti-warping structure to the wiring substrate further includes bonding the first anti-warping structure to the wiring substrate via a second conductive bump, wherein the second conductive bump is bonded to a dummy bonding pad of the wiring substrate.

[0221] In some embodiments, the method further includes bonding a second anti-warping structure to a wiring substrate, wherein the second anti-warping structure is composed of a semiconductor material, is electrically insulated from the chip package and the wiring structure of the wiring substrate, and is thinner than the first anti-warping structure.

[0222] In some embodiments, the second anti-warping structure is narrower than the first anti-warping structure.

[0223] The features of the above embodiments are helpful for those with ordinary knowledge in the technical field to understand the present invention. Those with ordinary knowledge in the technical field should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent substitutions do not deviate from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: a wiring substrate; a chip package, located on the wiring substrate and electrically connected to the wiring substrate; a first anti-warping structure bonded to the wiring substrate, wherein the first anti-warping structure is electrically insulated from the chip package and a wiring structure of the wiring substrate; as well as A heat dissipation structure is located on the wiring substrate and surrounds the chip package and the first anti-warping structure.

2. The chip packaging structure according to claim 1, wherein: Also includes: An adhesive layer is located between the first anti-warping structure and the wiring substrate.

3. The chip packaging structure according to claim 1 or 2, characterized in that: Also includes: A second anti-warping structure is bonded to the wiring substrate, wherein the second anti-warping structure is electrically insulated from the wiring structure of the wiring substrate, the chip package, and the first anti-warping structure, and the heat dissipation structure further surrounds the second anti-warping structure.

4. The chip packaging structure as claimed in claim 3, characterized in that: The first anti-warping structure is thicker than the second anti-warping structure.

5. The chip packaging structure as claimed in claim 4, characterized in that: The first anti-warping structure is wider than the second anti-warping structure.

6. The chip packaging structure according to claim 5, characterized in that: The first anti-warping structure surrounds a first corner portion of the chip package.

7. The chip packaging structure according to claim 6, wherein: The chip package has a side wall, the first corner portion and a second corner portion of the chip package are located on opposite sides of the side wall, the second anti-warping structure is located between the first corner portion and the second corner portion and extends along the side wall, and the second anti-warping structure is separated from the chip package.

8. The chip packaging structure according to claim 6, wherein: The first anti-warping structure is L-shaped.

9. A chip packaging structure, characterized in that: include: a wiring substrate; a chip package, located on the wiring substrate and electrically connected to the wiring substrate; a first anti-warping structure bonded to the wiring substrate, wherein the first anti-warping structure is electrically insulated from the chip package; a second anti-warping structure bonded to the wiring substrate, wherein the second anti-warping structure is electrically insulated from the chip package and the first anti-warping structure, and the second anti-warping structure is thinner than the first anti-warping structure; as well as A heat dissipation structure is located on the wiring substrate and surrounds the chip package, the first anti-warping structure, and the second anti-warping structure.

10. The chip packaging structure according to claim 9, wherein: The second anti-warping structure is narrower than the first anti-warping structure.

Images