Groove type integrated circuit chip capable of improving warping

Abstract

The utility model particularly relates to a groove type integrated circuit chip for improving warping, which comprises a cellular area positioned in the central area of the chip, the cellular area comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type epitaxial layer and a first conductive type substrate positioned on the lower surface of the first conductive type epitaxial layer, and the first conductive type substrate is positioned on the lower surface of the first conductive type epitaxial layer. A plurality of evenly-arranged strip-shaped grooves are formed in the first conduction type epitaxial layer, a plurality of evenly-arranged groove gate structures are arranged in the grooves, the depth of the grooves is smaller than 5 micrometers, and second conduction type columns are arranged at the bottoms of the grooves in the extending direction of the grooves. The second conductive type column comprises a plurality of second conductive type layers which are connected with one another, and the doping concentrations in the plurality of second conductive type layers are sequentially reduced from top to bottom; parameter performance of the whole chip is not affected, the problem of wafer warping can be well solved, and the method is suitable for an integrated circuit chip with the groove depth larger than 6.5 micrometers.

Description

Technical Field

[0001] The utility model relates to a design improvement of a groove type integrated circuit chip, in particular to a groove type integrated circuit chip with improved warping. Background Art

[0002] In the field of integrated circuit manufacturing, the continuous pursuit of higher integration and faster computing speed is a powerful driving force for the rapid development of the entire industry. The requirement for further reduction of integrated circuit production costs has made the use of smaller vertical trench gate devices to replace planar lateral devices an important development direction. As one of the key processes for vertical devices, the deep trench process has been increasingly widely studied and used.

[0003] Shielded gate trench (SGT) devices are all MOSFET chips with a deep trench longitudinal structure. Due to the deep trench of the chip structure and the filling of polysilicon and oxide in the trench, the polysilicon, oxide and silicon substrate in the deep trench will expand thermally during the high temperature thermal process. Due to the different thermal expansion coefficients between different materials, tensile stress is generated at the interface. The places with more stress are prone to deformation, causing the warping of the entire wafer. The deeper the trench, the more serious the warping (especially for SGT devices above 60V, the trench depth is greater than 5um, and the wafer warping is more serious). Especially in the 12-inch process, the cell density of the manufactured trench chip is greater, which will lead to more serious wafer warping problems. At the same time, in order to pursue more parameter performance of 12-inch wafer trench chips, 12-inch wafer trench chips are required to be thinned to less than 150μm, or even thinner (such as 100um, 75um, etc.), which further aggravates the warping of 12-inch wafer trench chips and even causes problems such as wafer fragmentation during transportation.

[0004] For shielded gate trench SGTs above 100V, in the 12-inch wafer process, the chip cell density is high, the trench depth is deep (generally greater than 5.5um), and the entire wafer is very thin, which can easily cause problems such as wafer warping. Wafer warping brings the following problems:

[0005] 1. Excessive warpage will cause the equipment vacuum alarm to occur during the wafer transmission or operation process, and thus the operation cannot be completed normally. In severe cases, it will cause fragments;

[0006] 2. Excessive warping will also affect the subsequent transportation, dicing and packaging of the wafer, and it is very easy to break during transportation and dicing. Utility Model Content

[0007] In view of the problems mentioned in the background technology, the purpose of the present invention is to provide a trench integrated circuit chip with improved warping.

[0008] The above technical objectives of the utility model are achieved through the following technical solutions: a trench-type integrated circuit chip with improved warpage, comprising a cell region located in the central region of the chip, the cell region comprising a semiconductor substrate, the semiconductor substrate comprising a first conductive type epitaxial layer and a first conductive type substrate located on the lower surface of the first conductive type epitaxial layer, a plurality of uniformly arranged trench gate structures are arranged in the first conductive type epitaxial layer, the trench gate structure comprising strip-shaped trenches;

[0009] It is characterized in that: the groove extends in the first conductive type epitaxial layer along its upper surface toward the lower surface, and a second conductive type column is provided along the direction of extension of the groove and at the bottom of the groove, the second conductive type column includes a plurality of interconnected second conductive type layers, and the doping concentration in the plurality of interconnected second conductive type layers decreases from top to bottom, and the second conductive type column is in the shape of an inverted trapezoidal candied haws.

[0010] Preferably, the groove depth is less than 5 um, and the total depth of the groove and the second conductive type column is not less than 6.5 um.

[0011] Preferably, the number of the second conductive type layers in the second conductive type column is not less than 2.

[0012] Preferably, the trench gate structure includes upper and lower shielding gate trench structures and left and right shielding gate structures;

[0013] The upper and lower shielding gate trench structures are provided with upper and lower parts in the trench, the upper part includes control gate polysilicon and a gate oxide layer located on the side wall of the control gate polysilicon, and the lower part includes shielding gate polysilicon, a field oxide layer wrapping the shielding gate polysilicon, and an isolation oxide layer located between the control gate polysilicon and the shielding gate polysilicon, and the trench is sequentially covered with an insulating dielectric layer and a source metal;

[0014] The left and right shielding gate groove structures include control gate polysilicon located on the left and right sides of the upper part of the groove, a gate oxide layer located on the side walls of the control gate polysilicon, a shielding gate polysilicon located in the middle of the groove and separated from the control gate polysilicon by an isolation oxide layer, and a field oxide layer wrapping the shielding gate polysilicon, and the groove is covered with an insulating dielectric layer and a source metal in sequence.

[0015] Preferably, a second conductive type body region is provided between adjacent trenches, the second conductive type body region is provided in the first conductive type epitaxial layer, a first conductive type source region is provided in the second conductive type body region, the first conductive type source region is provided on both sides of the second conductive type body region; and both the first conductive type source region and the second conductive type body region are adjacent to the gate oxide layer;

[0016] The source metal passes through the insulating dielectric layer and respectively makes ohmic contact with the second conductive type body region and the first conductive type source region;

[0017] A drain metal is disposed on the lower surface of the first conductive type substrate, and the drain metal is in ohmic contact with the first conductive type substrate.

[0018] To sum up, the utility model mainly has the following beneficial effects: the trench-type integrated circuit chip with improved warping of the utility model, by performing multiple high-energy injections of second conductive type ions in the trench to bear the pressure-resistant replacement of deep trenches, reduces the depth of the trench, which neither affects the parameter performance of the entire chip nor can effectively solve the wafer warping problem, and is suitable for integrated circuit chips with a trench depth greater than 6.5um. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the prior art;

[0020] Figure 2 It is a structural schematic diagram of embodiment 1 of the utility model;

[0021] Figure 3 It is a structural schematic diagram of embodiment 2 of the utility model;

[0022] Figure 4 It is a structural schematic diagram of embodiment 3 of the utility model;

[0023] Figure 5 It is a schematic diagram of the structure of forming an N-type substrate 1 and an N-type epitaxial layer 2 in Embodiment 1, Embodiment 2 and Embodiment 3 of the present utility model;

[0024] Figure 6 It is a schematic diagram of the structure of forming the groove 3 in the embodiment 1, the embodiment 2 and the embodiment 3 of the utility model;

[0025] Figure 7 It is a schematic diagram of the structure of forming a first second conductive type layer 81, a second second conductive type layer 82, a third second conductive type layer 83, and a fourth second conductive type layer 84 in Embodiment 1 and Embodiment 3 of the present utility model;

[0026] Figure 8 It is a schematic diagram of the structure of forming a first second conductive type layer 81, a second second conductive type layer 82, a third second conductive type layer 83, a fourth second conductive type layer 84, and a fourth second conductive type layer 85 in Embodiment 2 of the present utility model;

[0027] Fig. 9 It is a schematic diagram of the structure of the thick silicon dioxide layer and the conductive polysilicon in step 5 formed in Examples 1, 2 and 3 of the present invention;

[0028] Fig.10 It is a schematic diagram of the structure of forming the shielding gate polysilicon 11 and the field oxide layer 12 in the embodiment 1, the embodiment 2 and the embodiment 3 of the utility model;

[0029] Fig.11 It is a schematic diagram of the structure of forming the shielding gate polysilicon 11 and the field oxide layer 12 in the embodiment 1, the embodiment 2 and the embodiment 3 of the utility model;

[0030] Fig.12 It is a schematic diagram of the structure of forming the gate oxide layer 10 in Embodiment 1, Embodiment 2 and Embodiment 3 of the present utility model;

[0031] Fig.13 It is a schematic diagram of the structure of forming the control gate polysilicon 9 in Embodiment 1, Embodiment 2 and Embodiment 3 of the utility model;

[0032] Fig.14 It is a schematic diagram of the structure of forming the second conductive type column 7, the N-type source region 5 and the P-type body region 4 in the embodiment 1, the embodiment 2 and the embodiment 3 of the present utility model;

[0033] Fig.15 It is a comparison diagram of the electric field distribution diagram of the prior art integrated circuit chip and the embodiment 1 of the utility model;

[0034] Figure numerals: 1. first conductive type substrate; 2. first conductive type epitaxial layer; 3. trench; 4. second conductive type body region; 5. first conductive type source region; 6. insulating dielectric layer; 7. second conductive type column; 8. second conductive type layer; 81. first layer of second conductive type layer; 82. second layer of second conductive type layer; 83. third layer of second conductive type layer; 84. fourth layer of second conductive type layer; 9. control gate polysilicon; 10. gate oxide layer; 11. shielding gate polysilicon; 12. field oxide layer; 13. source metal; 14. drain metal; 15. isolation oxide layer. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0036] In order to solve the problem of 12-inch wafer warping, the utility model must reduce the depth of the groove. If the groove depth is too shallow, the device voltage resistance is insufficient for SGT of 100V and above. Therefore, the main problem solved by the utility model is to ensure that the 12-inch wafer does not warp and the device voltage resistance is ensured.

[0037] The utility model forms a second conductive type column 7 at the bottom of the groove 3 through multiple high-energy second conductive type ion implantations of different doses and energies through the entire process heat process. The second conductive type column 7 and the first conductive type epitaxial layer 2 are mutually depleted to achieve charge balance, thereby replacing the existing deep grooves to bear the withstand voltage. The utility model solution can effectively solve the problem of wafer warping and ensure the withstand voltage capability of the device.

[0038] The manufacturing method of the utility model forms a multi-layer second conductive type layer 8 at the bottom of the groove by multiple high-energy injections. During the high-temperature thermal process of the entire process, the second conductive type ions in the second conductive type layer diffuse and connect together to form a second conductive type column 7.

[0039] The trench-type integrated circuit chip for improving warpage of the utility model comprises, in a specific implementation, a cell region located in the central region of the chip, the cell region comprising a semiconductor substrate, the semiconductor substrate comprising a first conductive type epitaxial layer 2 and a first conductive type substrate 1 located on the lower surface of the first conductive type epitaxial layer 2, a plurality of evenly arranged trench gate structures are arranged in the first conductive type epitaxial layer 2, the trench gate structure comprises a strip-shaped trench 3; the trench 3 extends in the first conductive type epitaxial layer 2 along its upper surface toward the lower surface, a second conductive type column 7 is arranged along the direction in which the trench 3 extends and at the bottom of the trench 3, the second conductive type column 7 comprises a plurality of interconnected second conductive type layers, and the doping concentration in the plurality of interconnected second conductive type layers 8 decreases from top to bottom, and the second conductive type column 7 is in the shape of an inverted trapezoidal candied haws;

[0040] A second conductive type body region 4 is provided between adjacent trenches 3, the second conductive type body region 4 is provided in the first conductive type epitaxial layer 2, a first conductive type source region 5 is provided in the second conductive type body region 4, the first conductive type source region 5 is provided on both sides of the second conductive type body region 4; and both the first conductive type source region 5 and the second conductive type body region 4 are adjacent to the gate oxide layer 10;

[0041] The source metal 13 passes through the insulating dielectric layer 6 and respectively makes ohmic contact with the second conductive type body region 4 and the first conductive type source region 5 ; a drain metal 14 is provided on the lower surface of the first conductive type substrate 1 , and the drain metal 14 makes ohmic contact with the first conductive type substrate 1 .

[0042] The trench gate structure includes upper and lower shielding gate trench structures and left and right shielding gate structures;

[0043] like Figure 2 The trench gate structure is an upper and lower shielding gate trench structure, and an upper and lower part are provided in the trench 3, the upper part includes a control gate polysilicon 9 and a gate oxide layer 10 located on the side wall of the control gate polysilicon 9, and the lower part includes a shielding gate polysilicon 11, a field oxide layer 12 wrapping the shielding gate polysilicon 11, and an isolation oxide layer 15 located between the control gate polysilicon 9 and the shielding gate polysilicon 11, and the trench 3 is sequentially covered with an insulating dielectric layer 6 and a source metal 13;

[0044] The number of the second conductive type layers 8 in the second conductive type column 7 is 4, and the second conductive type layer 8 includes a first second conductive type layer 81, a second second conductive type layer 82, a third second conductive type layer 83 and a fourth second conductive type layer 84; the depth of the groove 3 is about 4um, and the total depth of the groove 3 and the second conductive type column 7 is about 6.5um, which is suitable for SGT 100VN integrated circuit chips;

[0045] like Figure 3 The trench gate structure is an upper and lower shielding gate trench structure, and an upper and lower part are provided in the trench 3, the upper part includes a control gate polysilicon 9 and a gate oxide layer 10 located on the side wall of the control gate polysilicon 9, and the lower part includes a shielding gate polysilicon 11, a field oxide layer 12 wrapping the shielding gate polysilicon 11, and an isolation oxide layer 15 located between the control gate polysilicon 9 and the shielding gate polysilicon 11, and the trench 3 is sequentially covered with an insulating dielectric layer 6 and a source metal 13;

[0046] The number of the second conductive type layers 8 in the second conductive type column 7 is 5, and the second conductive type layer 8 includes a first second conductive type layer 81, a second second conductive type layer 82, a third second conductive type layer 83, a fourth second conductive type layer 84 and a fourth second conductive type layer 85; the depth of the groove 3 is about 4um, and the total depth of the groove 3 and the second conductive type column 7 is about 7um, which is suitable for SGT 150VN integrated circuit chips;

[0047] like Figure 4 The trench gate structure is a left and right shielding gate trench structure, including a control gate polysilicon 9 located on the left and right sides of the upper part of the trench 3, a gate oxide layer 10 located on the sidewalls of the control gate polysilicon 9, a shielding gate polysilicon 9 located in the middle of the trench 3 and separated from the control gate polysilicon 9 by an isolation oxide layer 15, and a field oxide layer 12 wrapping the shielding gate polysilicon 11, and the trench 3 is sequentially covered with an insulating dielectric layer 6 and a source metal 13;

[0048] The number of the second conductive type layers 8 in the second conductive type column 7 is 4, and the second conductive type layer 8 includes a first second conductive type layer 81, a second second conductive type layer 82, a third second conductive type layer 83 and a fourth second conductive type layer 84; the depth of the groove 3 is about 4um, and the total depth of the groove 3 and the second conductive type column 7 is about 6.5um, which is suitable for SGT 100VN integrated circuit chips;

[0049] The number of the second conductive type layers 8 of the present invention is determined according to the withstand voltage of the integrated circuit chip. The higher the withstand voltage, the more the number of the second conductive type layers 8 is required.

[0050] The preparation method of the utility model is shown in Example 1:

[0051] like Figure 2 As shown, taking SGT 100VN as an example, it includes a cell area located in the central area of ​​the chip, the cell area includes a semiconductor substrate, the semiconductor substrate includes an N-type epitaxial layer 2 and an N-type substrate 1 located on the lower surface of the N-type epitaxial layer 2, a plurality of uniformly arranged strip-shaped grooves 3 are arranged in the N-type epitaxial layer 2, and an upper and lower part are arranged in the groove 3, the upper part includes a control gate polysilicon 9 and a gate oxide layer 10 located on the side wall of the control gate polysilicon 9, and the lower part includes a shielding gate polysilicon 11, a field oxide layer 12 wrapping the shielding gate polysilicon 11, and an isolation oxide layer 15 located between the control gate polysilicon 9 and the shielding gate polysilicon 11, and the groove 3 is sequentially covered with an insulating dielectric layer 6 and a source metal 13;

[0052] The trench 3 extends in the N-type epitaxial layer 2 along its upper surface toward the lower surface, and a P-type column 7 is provided along the extending direction of the trench 3 and at the bottom of the trench 3. The P-type column 7 includes a plurality of interconnected P-type layers 8, and the doping concentration in the plurality of P-type layers 8 decreases from top to bottom.

[0053] The depth of the groove 3 is about 4 um, and the total depth of the groove 3 and the P-type column 7 is about 6.5 um; the number of the P-type layers 8 in the P-type column 7 is 4.

[0054] A P-type body region 4 is provided between adjacent trenches 3, the P-type body region 4 is provided in the N-type epitaxial layer 2, an N-type source region 5 is provided in the second conductive type body region 4, the N-type source region 5 is provided on both sides of the P-type body region 4; and both the N-type source region 5 and the P-type body region 4 are adjacent to the gate oxide layer 10;

[0055] The source metal 13 passes through the insulating dielectric layer 6 and respectively makes ohmic contact with the P-type body region 4 and the N-type source region 5;

[0056] A drain metal 14 is disposed on the lower surface of the N-type substrate 1 , and the drain metal 14 is in ohmic contact with the N-type substrate 1 .

[0057] Fig.15 The existing SGT integrated circuit chip (such as Figure 1 ) and the utility model embodiment 1 (such as Figure 2 ) electric field distribution comparison diagram; through comparison, it can be found that compared with the prior art, the electric field strength of the integrated circuit chip of the utility model is greater, the integral area under the electric field strength curve is larger, and the corresponding voltage resistance is stronger. Therefore, the voltage resistance of the utility model is higher than that of the prior art. The reason is that the P-type column 7 and the N-type epitaxial layer 2 of the utility model are mutually depleted to form a structure similar to a super junction, and the P-type doping concentration in the P-type layer 8 in the P-type column 7 gradually decreases from top to bottom to form a structure similar to a gradual junction. Since the P-type column 7 and the N-type epitaxial layer 2 of the gradual junction are more thoroughly depleted, the voltage resistance of the utility model is greatly improved.

[0058] The utility model discloses a method for preparing a warpage-improved trench integrated circuit chip, comprising the following method:

[0059] like Figure 5 As shown, step 1, selecting an N-type substrate 1, growing an N-type epitaxial layer 2 on the N-type substrate 1, the upper surface of the N-type epitaxial layer 2 being the first main surface, and the lower surface of the N-type substrate 1 being the second main surface;

[0060] like Figure 6 As shown, step 2, under the mask of the hard mask layer window, anisotropic dry etching is performed on the first main surface to form a plurality of evenly arranged grooves 3 in the N-type epitaxial layer 2, wherein the depth of the grooves 3 is less than 5 um;

[0061] like Figure 7 As shown, step three, using high-energy ion implantation technology, continuously perform several high-energy ion implantations in the first main surface and the trench 3 to implant P-type ions, then remove the hard mask layer window to form a P-type layer 8 below the trench 3;

[0062] In the step 3, the P-type layer 8 includes a first P-type layer 81, a second P-type layer 82, a third P-type layer 83 and a fourth P-type layer 84; the process conditions of the four high-energy implantations are: energy 100kev dose 5E12, energy 250kev dose 3.5E12, energy 450kev dose 3.5E12, energy 920kev dose 3E12;

[0063] During the high-energy ion implantation, P-type ions are also implanted between the trenches 3, and the hard mask layer window material is silicon dioxide;

[0064] like Fig. 9As shown, step 4, using SACVD technology, using inductive coupling to excite plasma process, to form a thick silicon dioxide layer on the first main surface and in the groove 3;

[0065] Step 5: depositing conductive polysilicon on the thick silicon dioxide layer, wherein the conductive polysilicon fills the groove 3;

[0066] like Fig.10 As shown, step six, the conductive polysilicon and the thick silicon dioxide layer are etched respectively to obtain the shielding gate polysilicon 11 below the trench 3 and the field oxide layer 12 below and on the sidewall of the trench 3;

[0067] In the step six, the field oxide layer 12 includes a first oxide layer made by furnace thermal oxidation method, the thermal oxidation temperature is 1050°C, the first oxide layer thickness is 2500A and a second oxide layer deposited by SACVD vapor phase, the second oxide layer thickness is 2500A;

[0068] like Fig.11 As shown, step seven, using PECVD technology, using inductive coupling to excite the plasma process, continue to deposit a layer of silicon dioxide layer on the shielding gate polysilicon 11 in the trench 3, and etch away the silicon dioxide layer on the first main surface and the silicon dioxide layer on the side wall of the trench to obtain an isolation oxide layer 15 located on the shielding gate polysilicon 11;

[0069] like Fig.12 As shown, step eight, a thin oxide layer is grown on the first main surface and in the trench 3 by thermal oxidation to obtain a gate oxide layer 10 located on the upper sidewall of the trench 3;

[0070] like Fig.13 As shown, step nine, continue to deposit conductive polysilicon on the first main surface and in the trench 3, etch and remove the conductive polysilicon on the first main surface, and obtain a control gate polysilicon 9 located at the upper part of the trench 3, wherein the control gate polysilicon 9 is separated from the shield gate polysilicon 11 by an isolation oxide layer 15;

[0071] like Fig.14 As shown, in step ten, P-type impurity ions are generally implanted on the first main surface, and a P-type body region 4 is formed by driving a well;

[0072] In the step ten, the P-type impurity ions injected in this step are activated by pushing the well to form a P-type body region 4; the well depth of the P-type body region 4 is 1.02um; the process conditions for general injection of P-type impurity ions are: energy 240kev dose 3E12, and the process conditions for pushing the well are: temperature 1100C time 30min.

[0073] In the step 10, at this time, the high-energy P-type ions in the P-type layer 8 below the trench 3 are activated in the push-trap thermal process of step 10, and diffuse into each other to form a P-type column 7; in this embodiment 1, the depth of the trench 3 is about 4um, and the total depth of the trench 3 and the P-type column 7 is about 6.5um;

[0074] Step 11: On the first main surface, selectively implant high-concentration N-type impurity ions through the shielding of the photolithography mask, and form an N-type source region 5 through annealing;

[0075] like Figure 2 As shown, in step twelve, an insulating dielectric layer 6 is deposited on the first main surface, and the insulating dielectric layer 6 is etched to obtain a metal contact hole;

[0076] Step 13: depositing metal in the metal contact hole on the insulating dielectric layer 6, and etching the metal to obtain a source metal 13 that is in ohmic contact with the P-type body region 4 and the N-type source region 5 respectively;

[0077] Step 14: thinning the second main surface, and then depositing metal on the second main surface to obtain a drain metal 14 , wherein the drain metal 14 is in ohmic contact with the N-type substrate 1 .

[0078] For an N-type integrated circuit chip, the N-type is N-type conductive and the P-type is P-type conductive; for a P-type integrated circuit chip, the N-type is P-type conductive and the P-type is N-type conductive.

[0079] In the present embodiment 1, the total depth of the trench 3 and the P-type pillar 7 is about 6.6 um.

[0080] The preparation method of the utility model is shown in Example 2:

[0081] Taking SGT 150V as an example, N type is N type, P type is P type,

[0082] like Figure 8 and Figure 3As shown, compared with Example 1, in Example 2 of the utility model, in Step 3, the P-type layer 8 includes a first P-type layer 81, a second P-type layer 82, a third P-type layer 83, a fourth P-type layer 84 and a fifth P-type layer 85; the process conditions of the five high-energy injections are: energy 100kev dose 5E12, energy 250kev dose 3.5E12, energy 450kev dose 3.5E12, energy 920kev dose 3E12; 1050kev dose 2E12; in Step 10, the P-type layer 8 formed by five high-energy particle injections below the trench 3 diffuses and connects to form a P-type column 7 during the push-well heat process of Step 10. In this Example 2, the depth of the trench 3 is about 4um, and the total depth of the trench 3 and the P-type column 7 is about 7um;

[0083] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A trench-type integrated circuit chip with improved warpage, comprising a cell region located in the central area of ​​the chip, the cell region comprising a semiconductor substrate, the semiconductor substrate comprising a first conductive type epitaxial layer (2) and a first conductive type substrate (1) located on the lower surface of the first conductive type epitaxial layer (2), a plurality of evenly arranged trench gate structures are arranged in the first conductive type epitaxial layer (2), the trench gate structure comprising strip-shaped trenches (3); Features: The groove (3) extends in the first conductive type epitaxial layer (2) along its upper surface toward the lower surface, and a second conductive type column (7) is provided along the extending direction of the groove (3) and at the bottom of the groove (3), the second conductive type column (7) comprising a plurality of interconnected second conductive type layers, and the doping concentration in the plurality of interconnected second conductive type layers (8) decreases from top to bottom, and the second conductive type column (7) is in the shape of an inverted trapezoidal sugar-coated haws.

2. The trench integrated circuit chip with improved warpage as claimed in claim 1, characterized in that: The depth of the groove (3) is less than 5 um, and the total depth of the groove (3) and the second conductive type column (7) is not less than 6.5 um.

3. The trench integrated circuit chip with improved warpage as claimed in claim 1, wherein: The number of the second conductive type layers (8) in the second conductive type column (7) is not less than 2.

4. The trench integrated circuit chip with improved warpage as claimed in claim 1, wherein: The trench gate structure includes upper and lower shielding gate trench structures and left and right shielding gate structures.

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