Chip interconnection circuit
By designing chip interconnection circuits between BMC and CPLD, combining comparator and voltage divider circuit, the problem of shortage of hardware IO resources is solved, and the monitoring and management of CPLD status is realized, providing a reliable and simple design with a wide range of Application prospects.
Patent Information
- Application Number
- CN202421214479.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-30
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-05-30
AI Technical Summary
The hardware IO direct interconnection method between BMC and CPLD requires multiple enable signals, power-on completion signals, etc., resulting in a shortage of IO resources and cannot meet the actual design needs.
A chip interconnection circuit is designed, combining comparator and voltage divider circuit, through three-state output components and resistor voltage divider, the GPIO resource requirement for BMC is reduced, and the monitoring and management of CPLD status is realized.
It effectively solves the problem of IO resource shortage in the direct connection mode of BMC and CPLD hardware, provides a reliable and simple design with wide application prospects.
Smart Images
Figure CN222354432U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of servers, and in particular relates to a chip interconnection circuit. Background Art
[0002] BMC communicates with CPLD through a specific communication protocol (such as I2C) to obtain various status information on the server board, such as temperature, voltage, fan speed, etc. At the same time, the BMC IO can be directly connected to the CPLD IO through the hardware circuit to connect the signals and send control instructions to the CPLD to achieve remote control and management of the server hardware.
[0003] Ideally, I2C communication between BMC and CPLD is a reliable and stable communication method suitable for many application scenarios. However, in actual applications, I2C communication may be unstable due to various factors. Hardware design, unstable power supply or interference sources may lead to communication failure or data errors, so some key power-on and power-off control signals, in-position signals, and fault signals are interconnected in hardware.
[0004] Compared with the above I2C interconnection method, the hardware circuit direct connection method between BMC IO and CPLD IO is more stable. However, due to the large number of power control signals, in-position signals, and fault signals that need to be interconnected, if a one-to-one connection is used for each enable signal and power-on completion signal in actual design, there is often a lack of IO resources for BMC and CPLD. Utility Model Content
[0005] In view of the above-mentioned deficiencies in the prior art, the utility model provides a chip interconnection circuit to solve the above-mentioned technical problems.
[0006] The utility model provides a chip interconnection circuit, comprising:
[0007] BMC, a first chip and a second chip;
[0008] The second chip is connected to the first input end of the three-state output element, and the second input end of the three-state output element is connected to the first power supply; the output end of the three-state output element is connected to one end of the first resistor; the other end of the first resistor is connected to a common node; the common node is respectively connected to the pull-down resistor port of the second chip, the input end of the first comparator, and the input end of the second comparator;
[0009] A second power source is connected to one end of a second resistor, and the other end of the second resistor is connected to the common node;
[0010] The output terminal of the first comparator and the output terminal of the second comparator are both connected to the BMC.
[0011] In an optional implementation, the output end of the first comparator is connected to a first GPIO port of the BMC, and the output end of the second comparator is connected to a second GPIO port of the BMC.
[0012] In an optional implementation, the reference voltage of the first comparator is 2.5V.
[0013] In an optional implementation, the reference voltage of the second comparator is 1.25V.
[0014] In an optional implementation, the first power supply and the second power supply are both 3.3V DC power supplies.
[0015] In an optional implementation, the resistance of the first resistor is 15K, and the resistance of the second resistor is 25K.
[0016] In an optional implementation, the pull-down resistor port of the first chip is a GPIO port, the pull-down resistor port is connected to a pull-down resistor, and the resistance of the pull-down resistor is 10K.
[0017] In an optional implementation, the first chip and the second chip are both complex programmable logic devices.
[0018] In an optional implementation, the first chip is arranged on a first board, and the second chip is arranged on a second board; the importance level of the first board is higher than that of the second board.
[0019] In an optional implementation, the BMC is connected to an LED display light.
[0020] The beneficial effect of the utility model is that the chip interconnection circuit provided by the utility model combines the comparator and the voltage divider circuit, reduces the IO resources required when the BMC monitors the status of the board, and can effectively solve the problem of IO resource shortage faced by the hardware IO direct interconnection mode of the BMC and the CPLD.
[0021] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 It is a schematic diagram of a chip interconnection circuit according to an embodiment of the utility model.
[0024] Figure 2 It is a schematic diagram of the circuit state of a chip interconnection circuit according to an embodiment of the utility model.
[0025] Figure 3 The utility model is a schematic diagram of the working process of the chip interconnection circuit of one embodiment. DETAILED DESCRIPTION
[0026] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0028] In order to facilitate the understanding of the present invention, the principle of the chip interconnection circuit of the present invention is further described below in combination with embodiments.
[0029] For details, please refer to Figure 1 , the chip interconnection circuit includes:
[0030] BMC, a first chip and a second chip, wherein the first chip and the second chip are both complex programmable logic devices, the first chip is CPLD-R, and the second chip is CPLD-L; the second chip CPLD-L is connected to the first input end of the three-state output element U1, and the second input end of the three-state output element U2 is connected to the first power supply; the output end of the three-state output element U3 is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to a common node; the common node is respectively connected to the pull-down resistor port of the second chip CPLD-L, the input end of the first comparator U2, and the input end of the second comparator U3; the second power supply is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the common node; the output end of the first comparator U2 and the output end of the second comparator U3 are both connected to the BMC. Wherein, the output end of the first comparator U2 and the output end of the second comparator U3 are respectively connected to two GPIO pins of the BMC.
[0031] The component parameters in the chip interconnect circuit include:
[0032] The reference voltage of the first comparator U2 is 2.5V, the reference voltage of the second comparator U3 is 1.25V, and the first power supply and the second power supply are both 3.3V DC power supplies. The resistance of the first resistor R1 is 15K, and the resistance of the second resistor R2 is 25K. The pull-down resistor port of the first chip CPLD-R is a GPIO port, and the pull-down resistor port is connected to the pull-down resistor R3, and the resistance of the pull-down resistor R3 is 10K.
[0033] Specifically, the interconnection circuit between BMC and CPLD consists of three parts: the three-state gate circuit, the comparator circuit, and the resistor voltage divider circuit. There are two CPLDs in the figure, which are devices on two different boards in the server. Their main functions are timing control and status monitoring of the single board. If an abnormal situation occurs, it needs to be reported to BMC as soon as possible. They need to interconnect some enable signals, power-on completion, and abnormal interrupt signals during the power-on and power-off process. At the same time, these signals also need to be transmitted to BMC so that BMC can manage the entire server.
[0034] The truth table of the three-state output element U1 is shown in Table 1:
[0035] Table 1
[0036]
[0037] The truth table of the first comparator U2 is shown in Table 2:
[0038] Table 2
[0039]
[0040] The truth table of the second comparator U3 is shown in Table 3:
[0041] Table 3
[0042]
[0043] Through the combination of the above components, this interconnection circuit can realize that BMC uses two GPIOs to obtain the three states of board R and L transmitted by the CPLD on board R. According to the output of U1, U2, and U3, the values of each point are shown in Table 4. Please refer to Figure 2When the server is in state ①, the first chip CPLD-R fails, and the built-in pull-down of CPLD-R IO——D point is removed through the logic code. At this time, the GPIO——E and F points of the BMC are both high level. When the server is in state ②, point A of CPLD-L outputs a high level, and the built-in pull-down resistor of CPLD-R IO——D point is added through the logic code, and the value is 10k. At this time, the voltage value of point C after the circuit voltage division is 1.7V, and the GPIO——E point of the BMC is low level, and point F is high level. When the server is in state ③, point A of CPLD-L outputs a low level, and the built-in pull-down resistor of CPLD-R IO——D point is added through the logic code, and the value is 10k. At this time, the voltage value of point C after the circuit voltage division is 0.94V, and the GPIO——E and F points of the BMC are both low level.
[0044] Among them, state ① means that the first board (board R) where the first chip CPLD-R is located is in an abnormal state; state ② means that the first board (board R) where the first chip CPLD-R is located is normal, and the second board (board L) where the second chip CPLD-L is located is normal; state ③ means that the first board (board R) where the first chip CPLD-R is located is normal, and the second board (board L) where the second chip CPLD-L is located is abnormal.
[0045] Table 4
[0046]
[0047] Please refer to Figure 3 , define the interconnection and management relationship between boards: In the server, BMC monitors and manages the running status of L board and R board. R board is connected to BMC by connector or cable. L board is not directly connected to BMC. Instead, CPLD-L reports the status to CPLD of R board first, and then CPLD-R reports the status of both R board and L board to BMC. The implementation steps of this circuit are shown in the figure below. Board R is more important than board L. If R board is abnormal, then board L will not work normally regardless of whether it is abnormal. The normality of board L depends on the status of board R. However, if board L is abnormal, the function of board R itself is not affected and it can still run normally.
[0048] BMC is connected to the LED display light. After learning the status of board L and board R, BMC controls the LED light to light up the corresponding color.
[0049] Although the present invention is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person skilled in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present technical field may easily think of changes or substitutions within the technical scope disclosed in the present invention, and these shall be within the scope of protection of the present invention.
Claims
1. A chip interconnection circuit, characterized in that: include: BMC, a first chip, and a second chip; The second chip is connected to the first input end of the three-state output element, and the second input end of the three-state output element is connected to the first power supply; the output end of the three-state output element is connected to one end of the first resistor; the other end of the first resistor is connected to a common node; the common node is respectively connected to the pull-down resistor port of the second chip, the input end of the first comparator, and the input end of the second comparator; A second power source is connected to one end of a second resistor, and the other end of the second resistor is connected to the common node; The output terminal of the first comparator and the output terminal of the second comparator are both connected to the BMC.
2. The chip interconnection circuit according to claim 1, characterized in that: The output end of the first comparator is connected to the first GPIO port of the BMC, and the output end of the second comparator is connected to the second GPIO port of the BMC.
3. The chip interconnection circuit according to claim 1, characterized in that: The reference voltage of the first comparator is 2.5V.
4. The chip interconnection circuit according to claim 1, characterized in that: The reference voltage of the second comparator is 1.25V.
5. The chip interconnection circuit according to claim 1, characterized in that: The first power supply and the second power supply are both 3.3V DC power supplies.
6. The chip interconnection circuit according to claim 1, characterized in that: The resistance value of the first resistor is 15K, and the resistance value of the second resistor is 25K.
7. The chip interconnection circuit according to claim 1, characterized in that: The pull-down resistor port of the first chip is a GPIO port, the pull-down resistor port is connected to a pull-down resistor, and the resistance value of the pull-down resistor is 10K.
8. The chip interconnection circuit according to claim 1, characterized in that: The first chip and the second chip are both complex programmable logic devices.
9. The chip interconnection circuit according to claim 8, characterized in that: The first chip is arranged on a first board, and the second chip is arranged on a second board; the importance level of the first board is higher than that of the second board.
10. The chip interconnection circuit according to claim 1, characterized in that: The BMC is connected to an LED display light.