Chip package

Abstract

The utility model relates to a chip package. An apparatus comprising: a support having an upper surface; an integrated circuit chip mounted on an upper surface of the support, in which the integrated circuit chip includes: a lower surface facing the upper surface of the support; at least one pixel disposed at the upper surface of the integrated circuit chip and in the central portion; and a first electrical connection pad disposed at a periphery of an upper surface of the integrated circuit chip; a resin covering an upper surface of the support and a periphery of the integrated circuit chip, and including an opening in a front surface of a central portion of the integrated circuit chip; the transparent plate is used for sealing the opening; wherein: a lower surface of the transparent plate faces the integrated circuit chip, and a periphery thereof rests on top of a surface of the resin and is in contact with the surface of the resin; a part of the resin is placed on the top of the periphery of the upper surface of the transparent plate and is in contact with the periphery of the upper surface of the transparent plate; and the resin prevents the transparent plate from displacing in a plane parallel to the upper surface of the support.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French patent application No. 2211833, filed on November 14, 2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to integrated circuits, and more particularly to packaging for an integrated circuit chip including at least one pixel for receiving light. Background Art

[0004] Integrated circuit chips are known that include one or more pixels (e.g., a pixel array) that are arranged on one side of the upper surface of the chip, in a central portion of the upper surface. These known chips also include electrical connection pads that are arranged on the upper surface side of the chip, i.e., on the upper surface of the chip, and that are arranged at the periphery of the upper surface of the chip. These known chips implement, for example, a light sensor or an image sensor.

[0005] The known encapsulation packages of these known chips generally include a support on which the chip is mounted or assembled, and the lower surface of the chip opposite to the upper surface of the chip rests on the upper surface of the support. Then, according to a technique called "wire bonding", the connection pads of the chip are connected to the electrical connection pads of the support by conductive wires. The encapsulation packages of these chips also include a plate that is transparent to the operating wavelength of the pixels of the chip. The transparent plate is arranged above and in front of the upper surface of the chip. These packages also include an annular wall extending vertically between the chip and the transparent plate or between the support and the transparent plate to define a cavity in which (one or more) pixels of the chip are arranged.

[0006] However, these known packages have various drawbacks, for example relating to the way in which the transparent plate is held above the chip and / or the way in which the cavity is formed in which the pixel(s) of the chip are arranged.

[0007] There is a need to overcome all or some of the disadvantages of known packages of the type described above. Utility Model Content

[0008] One embodiment provides a device, which includes: a support member having an upper surface; an integrated circuit chip mounted on the upper surface of the support member, the chip including: a lower surface facing the upper surface of the support member, at least one pixel arranged on one side of the upper surface of the chip and located in the central part of the upper surface of the chip, and a first electrical connection pad arranged at the periphery of the upper surface of the chip; a resin covering the upper surface of the support member and the periphery of the chip and including an opening in front of the central part of the chip; and a transparent plate closing the opening; wherein: the lower surface of the transparent plate faces the chip, and its periphery rests on the top of the resin and contacts the resin; a portion of the resin rests on the top of the periphery of the upper surface of the transparent plate and contacts the periphery of the upper surface of the transparent plate; and the resin prevents the transparent plate from being displaced in a plane parallel to the upper surface of the support member.

[0009] According to an embodiment, the device comprises no glue between the upper surface of the chip and the lower surface of the transparent plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above features and advantages as well as other features and advantages will be described in detail in the remainder of the present disclosure in specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0011] Figure 1 The steps of an embodiment of a method of manufacturing an integrated circuit chip encapsulation package are shown in simplified cross-sectional views;

[0012] Figure 2 Another step of the manufacturing method is shown in a simplified cross-sectional view;

[0013] Figure 3 Another step of the manufacturing method is shown in a simplified cross-sectional view;

[0014] Figure 4 Another step of the manufacturing method is shown in a simplified cross-sectional view;

[0015] Figure 5 Another step of the manufacturing method is shown in a simplified cross-sectional view;

[0016] Figure 6 A further step of the manufacturing method is shown in a simplified cross-sectional view; and

[0017] Figure 7 A further step of the production method is shown in a simplified cross-sectional view. DETAILED DESCRIPTION

[0018] Similar features are denoted by similar reference numerals in the various figures. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0019] For the sake of clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, the functions implemented by the described chip and its pixels are not described in detail, and the described embodiments are compatible with the common functions of integrated circuit chips including pixels, such as color imagers, three-dimensional imagers, ambient light sensor functions, etc.

[0020] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0021] In the following disclosure, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "up", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., the orientation of the figures is referenced unless otherwise stated.

[0022] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0023] Figure 1 The steps of an embodiment of a method of manufacturing an encapsulated package of an integrated circuit chip 1 are shown in simplified cross-sectional views.

[0024] The chip 1 includes an upper surface 100 and a lower surface 102 opposite to the upper surface 100 .

[0025] The chip 1 comprises at least one pixel, for example, preferably in the form of Figure 1 A plurality of pixels are arranged in the form of an array of pixels 104 as shown, Figure 1 The pixel(s) of chip 1 are arranged on the side of the upper surface 100 of chip 1. In other words, the pixel(s) of chip 1 are configured to receive light on the side of the surface 100 of chip 1. The pixel(s) of chip 1 are arranged in the central part of chip 1, i.e., in the central part of surface 100.

[0026] The chip 1 further comprises electrical connection pads 106. The pads 106 are arranged on the side of the surface 100 of the chip 1. More specifically, the pads 106 are arranged at the periphery of the chip 1, ie, in the periphery (or peripheral part) of the surface 100 of the chip 1.

[0027] For example, each pad 106 is arranged in a space extending between a pixel(s) of the chip 1 and a corresponding lateral (peripheral) edge of the chip 1 , ie, in a space extending between a central portion of the chip 1 and an edge of the chip 1 .

[0028] In the remainder of this disclosure, a vertical surface of the chip 1 that is perpendicular to the surfaces 100 and 102 , that extends from one of the surfaces 100 and 102 to the other of the surfaces 100 and 102 , is referred to as an “edge” of the chip 1 .

[0029] exist Figure 1 At the step shown in , the chip 1 is mounted on a support 110, which is, for example, a printed circuit board or a substrate made of, for example, semiconductor material. More specifically, the support 110 comprises an upper surface 112, and the chip 1 is mounted on the surface 112 of the support 110, i.e., it rests on this surface 112. As an example, although this Figure 1 Not shown, but a glue layer is arranged between the surface 102 of the chip 1 and the surface 112 of the support 110 to mechanically bond the chip 1 to the support 110 , which glue may have thermally conductive properties facilitating the dissipation of heat generated by the chip 1 towards the support 110 .

[0030] The support 110 comprises electrical connection pads 113 arranged on one side of its surface 112 , or in other words, the surface 112 of the support 110 comprises the pads 113 .

[0031] The support member 110 includes a lower surface 114 opposite to its upper surface 112. Figure 1 Although not shown, the conductive balls may be bonded to the surface 114 of the support 110 and electrically connected to an element arranged on the side of the surface 112 of the support 110 , for example, to the pads 113 , through electrical conductors arranged in the support 110 .

[0032] The chip 1 is electrically connected to the support 110. More specifically, the pads 106 of the chip 1 are electrically connected to the pads 113 of the support 110 through the conductive wires 116 according to the wire bonding technique.

[0033] Figure 2 A further step of the manufacturing method is shown in a simplified cross-sectional view, and more particularly Figure 1 Step after step.

[0034] At this step, a resist layer 200 or a photoresist layer 200 is formed on the Figure 1More specifically, the layer 200 is formed on the surface 112 of the support 110, i.e., on the entire portion of the surface 112 not covered by the chip 1, and on at least the periphery of the chip 1, i.e., on at least the peripheral portion of the surface 100 of the chip 1. Thus, the layer 200 covers not only the pads 106 of the chip 1, but also the pads 113 of the support 110.

[0035] According to an embodiment, Figure 2 As shown in , the layer 200 is formed over the entire surface 100 of the chip 1 .

[0036] Preferably, the layer 200 is formed with a thickness sufficient to embed the connection wires 116 in the layer 200. As an example, the thickness of the layer 200 measured perpendicularly to and from the surface 112 is equal to the desired height between the support 110 and the transparent plate to be placed above and in front of the chip 1. Preferably, the layer 200 is formed such that its upper surface is flat.

[0037] Figure 3 A further step of the manufacturing method is shown in a simplified cross-sectional view, and more particularly Figure 2 Step after step.

[0038] At this step, an opening 300 is formed in the layer 200. The opening 300 spans the entire thickness of the layer 200. The opening 300 appears on the central portion of the chip 1, i.e., on the central portion of the surface 100 of the chip 1. Thus, the pixel(s) of the chip 1, e.g., the array of pixels 104 of the chip 1, is exposed at the bottom of the opening 300. Furthermore, the opening 300 is formed so that a portion of the layer 200 remains in place on the periphery of the surface 100 of the chip 1 and covers the pads 113.

[0039] According to an embodiment, to form the opening 300, only a portion of the layer 200 arranged at the location of the opening 300 is illuminated through a mask configured so that a portion of the layer 200 resting on the periphery of the chip 1 and the support 110 does not receive light, after which the portion of the layer 200 that has received light is removed, for example with the aid of a suitable solvent, to form the opening 300. In this case, the resin of the layer 200 is referred to as "positive". After the opening 300 is formed, a heat treatment may be provided to make the resin of the layer 200 insensitive to light and / or to mechanically stabilize (or harden) the resin.

[0040] According to an alternative embodiment, to form the opening 300, a portion of the layer 200 resting on the periphery of the chip 1 and on the support 110 is illuminated through a mask configured so that a portion of the layer 200 arranged at the location of the opening 300 does not receive light, after which the portion of the layer 200 that does not receive light is removed, for example with the aid of a suitable solvent, to form the opening 300. In this case, the resin of the layer 200 is referred to as "negative". A heat treatment may then be provided to render the resin of the layer 200 insensitive to light and / or to mechanically stabilize the resin.

[0041] According to yet another alternative embodiment, in order to form the layer 200 and the opening 300, instead of first forming the layer 200 ( Figure 2 ) Then, a through opening 300 is formed in the layer 200 ( Figure 3 ), but the layer 200 provided with the opening 300 is laminated on the support 110 and the chip 1 in the form of a dry film, so that the opening 300 appears on the central part of the chip 1, and the resin of the layer 200 covers the periphery of the chip 1 and the support 110. The layer 200 is then called a laminated dry film, for example. A heat treatment may then be provided to make the resin of the layer 200 insensitive to light and / or to stabilize the resin mechanically.

[0042] Figure 4 A further step of the manufacturing method is shown in a simplified cross-sectional view, and more particularly Figure 3 Step after step.

[0043] At this step, the resist layer 400 is formed on the Figure 3 Described in structure.

[0044] More specifically, according to Figure 4 In the embodiment shown in FIG. 4 , the layer 400 is laminated on the layer 200 in the form of a dry film, so that a portion of the layer 400 covers the opening 300 on the side opposite to the chip 1 (ie, is closed over the opening 300 ).

[0045] Figure 5 A further step of the manufacturing method is shown in a simplified cross-sectional view, and more particularly Figure 4 Step after step.

[0046] At this step, an opening 500 is formed in layer 400. Opening 500 spans the entire thickness of layer 400. Opening 500 includes a central portion that appears on opening 300, i.e., a central portion that is vertically aligned with opening 300, and a peripheral portion that appears on layer 200, i.e., a central portion that is vertically aligned with a portion of layer 200. A portion of layer 400 remains in place on layer 200, all around opening 500.

[0047] For example, in a direction perpendicular to the surface 112 of the support member 110, the opening 500 is aligned with the opening 300, the center of the opening 500 is aligned with the center of the opening 300 in this direction, for example, and in a plane parallel to the surface 112, the dimension of the opening 500 is greater than the dimension of the opening 300.

[0048] The pixel(s) of chip 1 , for example, the array of pixels 104 of chip 1 , is exposed to light passing through openings 500 and 300 .

[0049] According to an embodiment, in order to form the opening 500, a portion of the layer 400 arranged at the location of the opening 500 is illuminated through a mask configured so that a portion of the layer 500 intended to remain in place on the layer 200 does not receive light, after which the portion of the layer 400 that has received light is removed, for example with the aid of a suitable solvent, to form the opening 500. In this case, the resin of the layer 400 is referred to as "positive". A heat treatment may then be provided to render the resin of the layer 400 insensitive to light and / or to mechanically stabilize the resin.

[0050] According to an alternative embodiment, in order to form the opening 500, a portion of the layer 400 intended to remain in place on the layer 200 after the opening 500 is formed is illuminated through a mask configured so that a portion of the layer 400 arranged at the location of the opening 500 does not receive light, after which the portion of the layer 400 that does not receive light is removed, for example with the aid of a suitable solvent, to form the opening 500. In this case, the resin of the layer 400 is referred to as "negative". A heat treatment may then be provided to render the resin of the layer 400 insensitive to light and / or to mechanically stabilize the resin.

[0051] According to yet another alternative embodiment, to form the layer 400 and the opening 500, instead of first forming the layer 400 ( Figure 4 ) Then, a through opening 500 is formed in the layer 400 ( Figure 5 ), but the layer 400 provided with the opening 500 is laminated on the layer 200 in the form of a dry film, so that the opening 500 includes a central part appearing on the opening 300 and a peripheral part appearing on the layer 200. The layer 400 is then, for example, a dry laminated film. A heat treatment may then be provided to make the resin of the layer 400 insensitive to light and / or to stabilize the resin mechanically.

[0052] Figure 6 A further step of the manufacturing method is shown in a simplified cross-sectional view, and more particularly Figure 5 Step after step.

[0053] exist Figure 6 At the step, the plate 600 is arranged in the opening 500 ( Figure 5). The plate 600 is made of a material that is transparent to the operating wavelength of the pixel(s) of the chip 1. The dimension of the plate 600 in a plane parallel to the surface 112 of the support 110 is substantially equal to the opening 500 ( Figure 5 ) so that the plate 600 fits into the opening 500. In other words, in a plane parallel to the surface 112 of the support 110, the plate 600 has a dimension similar to the opening 500 ( Figure 5 ) have the same dimensions as the dimensions of .

[0054] Thus, the plate 600 comprises a peripheral portion resting on the layer 200. More specifically, the plate 600 has a lower surface facing the chip 1, the periphery of the lower surface of the plate 600 resting on top of and in contact with the layer 200. Preferably, no glue is arranged between the plate 600 and the layer 200.

[0055] The resin of layer 400 prevents displacement of plate 600 in a plane parallel to surface 112 of support 110 . Positioning and holding of plate 600 above chip 1 is therefore facilitated by opening 500 and layer 400 .

[0056] Furthermore, parallelism between plate 600 and chip 1 , for example, between plate 600 and upper surface 100 of chip 1 , is ensured by the fact that the upper surface of layer 200 is flat and no glue is dispensed between the periphery of plate 600 and layer 200 .

[0057] The plate 600 further comprises a central portion arranged in front of the central portion at the surface of the chip 1 and therefore of the pixel(s) of the chip 1. In other words, the central portion of the plate 600 is vertically aligned with the opening 300. This central portion of the plate 600 covers the opening 600 on the side opposite to the chip 1. The pixel(s) of the chip 1 are thus arranged in a cavity corresponding to the opening 300, which cavity extends upwards between the chip 1 and the plate 600 and is laterally delimited by the resin, more particularly by the resin of the layer 200.

[0058] As an example, plate 600 and layer 400 have equal or substantially equal thicknesses.

[0059] exist Figure 6 At the step of placing the plate 600 in the opening 500 ( Figure 5 ) thereafter, a resist layer 602 is formed on layer 400 and at least on the periphery of plate 600, i.e., on top of and in contact with the peripheral portion of the upper surface of plate 600.

[0060] exist Figure 6 In the embodiment shown in , layer 602 is formed on layer 400 and over the entire upper surface of plate 600 .

[0061] Figure 7 A further step of the manufacturing method is shown in a simplified cross-sectional view, and more particularly Figure 6 Step after step.

[0062] At this step, an opening 700 is formed in the layer 602. The opening 700 spans the entire thickness of the layer 602. The opening 700 appears on the central portion of the plate 600. Furthermore, the opening 700 does not appear on the periphery of the plate 600, or in other words, the resin of the layer 602 remains in place and in contact with the periphery of the plate 600, and more precisely, on top of the peripheral portion of the upper surface of the plate 600.

[0063] For example, in a direction perpendicular to the surface 112 of the support 110, the opening 700 is aligned with the opening 300, that is, the center of the opening 700 is aligned with the center of the opening 300 and the opening 500 ( Figure 5 ) is aligned with the center of the plate 600. Moreover, in a plane parallel to the surface 112, the dimensions of the opening 700 are, for example, equal to or greater than the dimensions of the opening 300, but smaller than the dimensions of the plate 600, and therefore smaller than the opening 500 ( Figure 5 ) dimension.

[0064] Displacement of the plate 600 in a direction orthogonal to the surface 112 of the support 110 is prevented by the layer 602 and the layer 200, between which the periphery of the plate 600 is interposed. More specifically, the portion of the layer 602 that rests on top of and in contact with the periphery of the upper surface of the plate 600 prevents the plate 600 from moving in a direction that would pull the plate 600 away from the support 110 ( Figure 7 Symmetrically, the portion of the periphery of the lower surface of the plate 600 of the layer 200 that rests on top of and in contact with it prevents the plate 600 from moving in a direction that would bring the plate 600 closer to the support 110 ( Figure 7 Any displacement of surface 112 (in the middle and downward) perpendicular to support member 110.

[0065] The plate 600 is then held in place by the resin, more precisely the resin of the layers 200 , 400 and 602 , which prevents any movement of the plate 600 in a direction orthogonal to the surface 112 of the support 110 and in a plane parallel to this surface 112 .

[0066] The pixel(s) of chip 1 , for example the array of pixels 104 of chip 1 , is exposed to light that passes successively through opening 700 , transparent plate 600 and opening 300 .

[0067] According to an embodiment, in order to form the opening 700, a portion of the layer 602 arranged at the location of the opening 700 is illuminated through a mask configured so that a portion of the layer 602 intended to remain in place on the periphery of the layer 400 and the plate 600 does not receive light, after which the portion of the layer 602 that has received light is removed, for example with the aid of a suitable solvent, to form the opening 700. In this case, the resin of the layer 602 is referred to as "positive". A heat treatment may then be provided to render the resin of the layer 602 insensitive to light and / or to mechanically stabilize the resin.

[0068] According to an alternative embodiment, in order to form the opening 700, a portion of the layer 602 intended to remain in place on the layer 400 and on the periphery of the plate 600 after the opening 700 is formed is illuminated through a mask configured so that a portion of the layer 602 arranged at the location of the opening 700 does not receive light, after which the portion of the layer 602 that does not receive light is removed, for example with the aid of a suitable solvent, to form the opening 700. In this case, the resin of the layer 602 is referred to as "negative". A heat treatment may then be provided to render the resin of the layer 602 insensitive to light and / or to mechanically stabilize the resin.

[0069] exist Figure 7 , the chip 1 is encapsulated in a package comprising a support 110, resin of layers 200, 400 and 602 and a board 600. Furthermore, while the central portion of the chip 1 comprising the pixel(s) of the chip 1 is not covered by the resin and is located in front of the central portion of the board 600 to be able to receive light, the periphery of the upper surface 100 of the chip 1, where the pads 113 are arranged and the edges of the chip 1 are covered by the resin. This advantageously makes it possible to avoid the formation of dendrites or foreign bodies, i.e. small metal particles, for example from the pads 106 and / or the wires 116. In fact, when such dendrites and foreign bodies are deposited on the pixel(s) of the chip 1, they may render the chip 1 inoperative, in particular its light capture function.

[0070] Although so far in combination Figures 1 to 7 This has not yet been specifically described in the embodiments and variants of the method described, but the mask used is, for example, an optical mask, or in other words, a plate of material transparent to the irradiation light provided with a pattern made of one or more materials opaque to these wavelengths, such as a chrome pattern. During each step of irradiation through the mask, the mask can be arranged above the irradiated resin layer, or in contact with it. As an example, in each irradiation step, the irradiation light is ultraviolet light. Of course, a person skilled in the art is able to design these masks and implement these irradiation steps.

[0071] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0072] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, a person skilled in the art is able to select the resist for each of the layers 200, 400 and 602 and the corresponding mask and irradiation conditions.

[0073] An embodiment provides a method for manufacturing a package for an integrated circuit chip, the method comprising the following consecutive steps: a) providing a support member having an upper surface, a chip being mounted on the upper surface, the chip comprising: a lower surface facing the upper surface of the support member; at least one pixel arranged on one side of the upper surface of the chip and located in a central portion of the upper surface of the chip; and a first electrical connection pad arranged on the periphery of the upper surface of the chip; b) forming a first resist layer on the upper surface of the support member and on the periphery of the chip, the first resist layer comprising a first through opening appearing on the central portion of the upper surface of the chip; c) forming a second resist layer comprising a second through opening, the second through opening having a central portion appearing on the first opening and a peripheral portion appearing on the first resist layer; d) arranging a transparent plate in the second opening; and e) forming a third resist layer, the third resist layer comprising a third through opening appearing on the central portion of the transparent plate in front of the central portion of the upper surface of the chip.

[0074] According to an embodiment, at steps b), c), d) and e), the first layer covers the periphery of the chip.

[0075] According to an embodiment, at step a), an electrical connection line connects the first pad to a second electrical connection pad of the support arranged on the upper surface side of the support, and at steps b), c), d) and e), the first layer covers the connection line.

[0076] According to an embodiment, the transparent plate and the second opening have substantially equal dimensions in a plane parallel to the upper surface of the support.

[0077] According to an embodiment, at step d), the periphery of the transparent plate rests on top of and in contact with the first layer.

[0078] According to an embodiment, at step c), a second layer is formed on top of and in contact with the first resist layer.

[0079] According to an embodiment, at step e), the third layer rests on top of and / or is in contact with a peripheral portion of the transparent plate around the third opening.

[0080] According to an embodiment, step b) comprises, in sequence: depositing a first layer; and forming a first opening by irradiating the first layer through a first mask and then by removing a portion of the first layer that has received light, the first mask being configured such that only a portion of the first layer arranged at the location of the first opening receives light.

[0081] According to an embodiment, step c) comprises, in sequence: depositing a second layer on the first layer; and forming a second opening by irradiating the second layer through a second mask and then by removing a portion of the second layer that has received light, the second mask being configured so that only a portion of the second layer arranged at the position of the second opening receives light.

[0082] According to an embodiment, the second layer is deposited on the first layer in the form of a stacked film.

[0083] According to an embodiment, step e) includes, in sequence: depositing a third layer on the second resist layer and the transparent plate; forming a third opening by irradiating the third layer through a third mask and then by removing a portion of the third layer that has received light, the third mask being configured so that only a portion of the third layer arranged at the position of the third opening receives light.

[0084] In one aspect, a method for manufacturing a package for an integrated circuit chip is provided, comprising the following steps performed in succession: a) mounting an integrated circuit chip to an upper surface of a support, wherein the integrated circuit chip comprises: a lower surface facing the upper surface of the support; at least one pixel arranged at the upper surface of the integrated circuit chip in a central portion of the upper surface of the integrated circuit chip; and a first electrical connection pad arranged at the periphery of the upper surface of the integrated circuit chip; b) forming a first resist layer on the upper surface of the support and the periphery of the integrated circuit chip, the first resist layer comprising a first pixel present in the central portion of the upper surface of the integrated circuit chip; c) forming a second resist layer on the upper surface of the first resist layer, the second resist layer including a second through opening, the second through opening having a central portion appearing on the first opening and a peripheral portion appearing on the upper surface of the first resist layer; d) arranging a transparent plate in the second opening, and the transparent plate is supported by the upper surface of the first resist layer; and e) forming a third resist layer on the upper surface of the second resist layer, the third resist layer including a third through opening, the third through opening appearing on the central portion of the transparent plate and positioned in front of the central portion of the upper surface of the integrated circuit chip.

[0085] In one embodiment, at steps b), c), d) and e), the first resist layer covers the first electrical connection pads arranged on the periphery of the integrated circuit chip.

[0086] In one embodiment, the method further comprises, at step a), connecting an electrical connection line between a first electrical connection pad and a second electrical connection pad of the support member arranged on the upper surface side of the support member, and wherein the first resist layer covers the electrical connection line.

[0087] In one embodiment, the transparent plate and the second opening have substantially equal dimensions in a plane parallel to the upper surface of the support.

[0088] In one embodiment, at step d), the periphery of the transparent plate rests on top of and in contact with the first resist layer.

[0089] In one embodiment, at step c), the second resist layer is formed on top of the first resist layer and in contact with the first resist layer.

[0090] In one embodiment, at step e), the third resist layer rests on top of and contacts the peripheral portion of the transparent plate around the third opening.

[0091] In one embodiment, step b) includes, in sequence: depositing the first resist layer; and forming the first opening by irradiating the first resist layer through a first mask and then removing the portion of the first resist layer that has received light, wherein the first mask is configured so that only a portion of the first resist layer arranged at the position of the first opening receives light.

[0092] In one embodiment, step c) includes, in sequence: depositing the second resist layer on the first layer; and forming the second opening by irradiating the second resist layer through a second mask and then removing the portion of the second resist layer that has received light, wherein the second mask is configured so that only a portion of the second resist layer arranged at the position of the second opening receives light.

[0093] In one embodiment, the second resist layer is deposited on top of the first resist layer in the form of a stacked film and extends over the first through opening.

[0094] In one embodiment, step e) includes, in sequence: depositing the third resist layer on the second resist layer and the transparent plate; and forming the third opening by irradiating the third resist layer through a third mask and then removing the portion of the third resist layer that has received light, wherein the third mask is configured so that only a portion of the third resist layer arranged at the position of the third opening receives light.

Claims

1. A chip package, characterized in that: include: a support member having an upper surface; an integrated circuit chip mounted on the upper surface of the support, wherein the integrated circuit chip comprises: a lower surface facing the upper surface of the support; at least one pixel arranged at the upper surface of the integrated circuit chip and in a central portion of the upper surface of the integrated circuit chip; and a first electrical connection pad arranged at the periphery of the upper surface of the integrated circuit chip; a resin covering an upper surface of the support member and a periphery of the integrated circuit chip and including an opening in front of a central portion of the integrated circuit chip; and a transparent plate closing the opening; in: The lower surface of the transparent plate faces the integrated circuit chip and its periphery rests on top of and in contact with the surface of the resin; a portion of the resin resting on top of and in contact with the periphery of the upper surface of the transparent plate; and The resin prevents the transparent plate from being displaced in a plane parallel to an upper surface of the support.

2. The chip package according to claim 1, characterized in that: No adhesive is provided between the upper surface of the integrated circuit chip and the lower surface of the transparent plate.

3. The chip package according to claim 1, characterized in that: The resin includes: a first resin portion covering an upper surface of the support member and a periphery of the integrated circuit chip and having a first opening extending therethrough; a second resin portion covering an upper surface of the first resin portion and having a second opening extending therethrough aligned with the first opening; wherein the transparent plate is installed in the second opening; and A third resin portion covers an upper surface of the second resin portion and a peripheral portion of the transparent plate and has a third opening extending therethrough aligned with the first opening and the second opening.

4. The chip package according to claim 3, characterized in that: The transparent plate is supported in the second opening by a portion of the upper surface of the first resin portion surrounding the first opening.

5. The chip package according to claim 3, characterized in that: The second resin portion includes a laminated film layer on the first resin portion.

6. The chip package according to claim 3, characterized in that: The transparent plate and the second opening have substantially equal dimensions in a plane parallel to the upper surface of the support.

7. The chip package according to claim 3, characterized in that: Also included is an electrical connection line disposed between a first electrical connection pad and a second electrical connection pad of the support member on the upper surface side of the support member, and wherein the first resin portion covers the electrical connection line.

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