Silicon carbide UMOS device with uniform current distribution
By constructing the structure of the current distribution layer and the control gate dielectric layer and well region in the silicon carbide UMOS device, the problems of uneven current distribution and electric field concentration are solved, achieving uniformity of current distribution and improving the reliability of the device.
Patent Information
- Application Number
- CN202421180516.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-28
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2034-05-28
AI Technical Summary
There are problems of uneven current distribution and gate breakdown in silicon carbide UMOS devices, resulting in high on-resistance and poor reliability.
By constructing a current sharing layer, the current is constructed from top to bottom along the gate dielectric layer to build a lateral low-resistance path to reduce the on-resistance of the device. By controlling the thickness of the bottom of the gate dielectric layer and the height of the bottom of the well region and the bottom of the gate dielectric, the reduction The electric field is concentrated.
The uniformity of current distribution is achieved, the on-resistance of the device is reduced, the reliability and voltage withstand capability of the device are improved, and the cost of the manufacturing process is reduced.
Smart Images
Figure CN222382027U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a silicon carbide UMOS device with uniform current distribution. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, which is widely used in electric vehicles, aerospace, power conversion and other fields. The development of device structure and preparation process has promoted the reduction of device on-resistance and the improvement of reliability. However, due to the characteristics of silicon carbide materials, the quality of the silicon dioxide gate dielectric generated is relatively low compared to silicon process and the work function gap of the material has a high requirement for the thickness of the insulating layer of the gate dielectric. Compared with trench-MOS, U-type gate can be wet-etched, and the manufacturing process cost is low. However, at the gate corners of U-type gate and trench-MOS, electric field concentration is prone to occur, resulting in gate breakdown. The gate corner of U-type gate is an obtuse angle, and the electric field concentration is smaller than that of trench-MOS, but due to its small bottom gate control area, the current distribution is concentrated; therefore, gate reliability and current concentration are problems that need to be solved for U-type gate devices. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a silicon carbide UMOS device with uniform current distribution, construct a current equalizing layer, and construct a lateral low-resistance path for the current from top to bottom along the gate dielectric layer, so that the current is more evenly distributed inside the device and the on-resistance of the device is reduced.
[0004] The utility model is implemented as follows: a silicon carbide UMOS device with uniform current distribution, comprising:
[0005] Silicon carbide substrate,
[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0007] A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer;
[0008] A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer;
[0009] a gate dielectric layer, the gate dielectric layer passing through the well region and connected to the upper side of the current balancing layer, and a groove is provided in the gate dielectric layer;
[0010] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region;
[0011] An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region, one side of the N-type source region is connected to one side of the P-type source region, and the other side of the N-type source region is connected to one side of the gate dielectric layer;
[0012] A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively;
[0013] A gate metal layer, wherein the gate metal layer is disposed on the groove;
[0014] and a drain metal layer connected to a lower side of the silicon carbide substrate.
[0015] The advantages of the utility model are:
[0016] 1. The device adopts a U-shaped gate structure. Compared with the trench gate structure, the angle of the gate corner is larger, and the electric field concentration problem is relatively small. It is relatively easy to suppress the electric field concentration at the gate corner, but the current channel is narrower and the current is more concentrated;
[0017] Second, two approaches are adopted to solve the problem of electric field concentration at the gate corner of the U-shaped gate structure. One is to increase the voltage resistance of the gate dielectric layer itself by controlling the thickness of the bottom of the gate dielectric layer. The other is to control the bottom of the well region to be at the same height as the bottom of the gate dielectric, so that the electric field at the corner of the gate dielectric diffuses to the well region, reducing the electric field concentration.
[0018] 3. To address the problem of narrower current channels, a current-balancing layer is constructed to build a lateral low-resistance path for the current from top to bottom along the gate dielectric layer, so that the current is more evenly distributed inside the device and the on-resistance of the device is reduced;
[0019] Fourth, as the depth increases, the contact area between the etching solution and the internal material of silicon carbide decreases, and the etching naturally presents the characteristics of being wide on the top and narrow on the bottom. Compared with trench-MOS, which requires trenches with consistent widths from top to bottom and can only be etched by sputtering, UMOS can use chemical reaction etching, which has lower manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0021] Figure 1 The utility model is a schematic diagram of a silicon carbide UMOS device with uniform current distribution.
[0022] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide UMOS device with uniform current distribution.
[0023] Figure 3 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 1 .
[0024] Figure 4This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 2 .
[0025] Figure 5 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 3 .
[0026] Figure 6 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 4 .
[0027] Figure 7 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 5 .
[0028] Figure 8 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 6 .
[0029] Fig. 9 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 7 .
[0030] Fig.10 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 8 .
[0031] Fig.11 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 9 .
[0032] Fig.12 This is a cross-sectional view of the process of a silicon carbide UMOS device with uniform current distribution in the utility model. Figure 10 . DETAILED DESCRIPTION
[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0038] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide UMOS device with uniform current distribution, including:
[0039] Silicon carbide substrate 101,
[0040] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;
[0041] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the drift layer 102;
[0042] A well region 104, wherein the lower side of the well region 104 is connected to the upper side of the current balancing layer 103;
[0043] A gate dielectric layer 105 , wherein the gate dielectric layer 105 passes through the well region 104 and is connected to the upper side of the current-balancing layer 103 , and a groove 1051 is provided in the gate dielectric layer 105 ;
[0044] A P-type source region 106 , wherein the lower side of the P-type source region 106 is connected to the upper side of the well region 104 ;
[0045] An N-type source region 107, wherein the lower side of the N-type source region 107 is connected to the upper side of the well region 104, one side of the N-type source region 107 is connected to one side of the P-type source region 106, and the other side of the N-type source region 107 is connected to one side of the gate dielectric layer 105;
[0046] A source metal layer 108 , wherein the source metal layer 108 is connected to the P-type source region 106 and the N-type source region 107 ;
[0047] A gate metal layer 109, wherein the gate metal layer 109 is disposed on the groove 1051;
[0048] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .
[0049] like Figures 2 to 12 As shown, the method for preparing the above-mentioned silicon carbide UMOS device comprises the following steps:
[0050] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing a drift layer 102 on the upper side of the silicon carbide substrate 101, wherein the drift layer 102 has a thickness of 20-30 μm;
[0051] Step 2, ion implantation is performed on the drift layer 102 to form a current balancing layer 103 in the drift layer 102, with a thickness of 1 μm and an ion implantation energy of 700-1000 kev;
[0052] Step 3, ion implantation is performed on the drift layer 102 to form a well region 104 in the drift layer 102, wherein the bottom side of the well region 104 is connected to the current balancing layer 103, and the thickness is 1 μm. The ion implantation energy is 330-670 kev.
[0053] Step 4: forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 102 to form a P-type source region 103, wherein the ion implantation energy is 10-330kev and the depth is 1μm;
[0054] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the drift layer 102, form an N-type source region 107, the implantation energy is 10-330kev, and the depth is 1μm;
[0055] Step 6, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, and etch the N-type source region 107 and the P-type well region 106 with a wet chemical solution, the etching depth L3 is 2 μm, and a groove b is formed, the top width L1 of the groove b is 800-1500nm, and the bottom width L2 of the groove b is 500-800nm; the chemical concentrated solution is a mixture of sulfuric acid solution and hydrogen peroxide, firstly configure the ratio of sulfuric acid and water to form a sulfuric acid solution, the ratio is 1:2-1:4; then configure the concentration of hydrogen peroxide, the concentration of hydrogen peroxide is 30-45%, and finally the sulfuric acid solution and hydrogen peroxide are mixed to form a chemical solution, the ratio of sulfuric acid solution to hydrogen peroxide is 1:3-1:6;
[0056] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing dry oxygen oxidation to form a gate dielectric layer 105, wherein the gate dielectric layer 105 is provided with a groove 1051;
[0057] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, forming a through hole, depositing metal, and forming a gate metal layer 109;
[0058] Step 8: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, deposit metal to form a source metal layer 108, remove the barrier layer a, and complete the preparation.
[0059] The silicon carbide substrate 101, the drift layer 102 and the current-balancing layer 103 are all N-type, and the well region 104 is P-type; the doping concentration of the silicon carbide substrate 101 is 5e18 cm -3 The doping concentration of the drift layer 102 is 6e16cm -3 The doping concentration of the current balancing layer 103 is 1e18 cm -3 The doping concentration of the well region 104 is 5e17 cm -3 The doping concentration of the N-type source region 107 is 8e18cm -3 The doping concentration of the P-type source region 106 is 4e19cm -3; The concentration of the silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 110 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the current-balancing layer 103 is to redistribute the current from the source region to the interior of the drift layer 102 relatively evenly, to avoid the burning phenomenon caused by excessive electric field density due to current concentration; the doping concentration of the N-type source region 107 and the P-type source region 106 is to form an ohmic contact with the source metal layer 108 and reduce the contact resistance.
[0060] Preferably, the thickness of the silicon carbide substrate 101 of the device is 1 μm, the thickness of the drift layer 102 is 20-30 μm, the thickness of the current balancing layer 103 is 1 μm, the thickness of the well region 104 is 1 μm, the thickness of the N-type source region 107 and the P-type source region 106 are both 1 μm, the wall thickness of the gate dielectric layer 105 is 50 nm, the width d1 of the top of the gate dielectric layer 105 of the UMOS device is 800-1500 nm, the width d2 of the bottom of the gate dielectric layer 105 is 500-800 nm, the device withstand voltage is 600-800 V, and the thickness of the drift layer 102 is within the above range according to different requirements for the withstand voltage characteristics of the device. Internal adjustment, the doping concentration and thickness design of the well region 104 are to improve the reliability of the device gate dielectric layer 105, the current balancing layer 103 can shield the capacitance effect from the gate to the device drain, thereby reducing the device gate-drain capacitance, reducing the Maitreya platform of the device, and improving the device switching speed; the design margin of the gate dielectric layer width is large, this is because even if the bottom area of the device gate is small, the current balancing layer of the device can complete the redistribution of the internal current of the device, can ensure the gate control ability and conductive channel position of the device, and avoid current concentration; the dielectric thickness of the bottom and side walls of the device gate is to improve the voltage resistance and process compatibility at the corner of the device gate;
[0061] As the depth increases, the contact area between the etching solution and the internal material of silicon carbide decreases, and the etching naturally presents the characteristics of being wide at the top and narrow at the bottom. Compared with trench-MOS, which requires trenches with consistent widths at the top and bottom, only sputtering etching can be used. The device of the utility model can use chemical reaction etching, which has lower manufacturing costs and uses a current equalizing layer to reduce the on-resistance of the device, solving the problem that the on-resistance of UMOS is larger than that of trench-MOS.
[0062] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A silicon carbide UMOS device with uniform current distribution, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer; A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer; a gate dielectric layer, the gate dielectric layer passing through the well region and connected to the upper side of the current balancing layer, and a groove is provided in the gate dielectric layer; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region; An N-type source region, wherein the lower side of the N-type source region is connected to the upper side of the well region, one side of the N-type source region is connected to one side of the P-type source region, and the other side of the N-type source region is connected to one side of the gate dielectric layer; A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively; A gate metal layer, wherein the gate metal layer is disposed on the groove; and a drain metal layer connected to a lower side of the silicon carbide substrate.
2. A silicon carbide UMOS device with uniform current distribution as claimed in claim 1, characterized in that: The thickness of the flow balancing layer is 1 micron.
3. A silicon carbide UMOS device with uniform current distribution as claimed in claim 1, characterized in that: The width d1 of the top of the gate dielectric layer is 800-1500 nm, and the width d2 of the bottom of the gate dielectric layer is 500-800 nm.
4. A silicon carbide UMOS device with uniform current distribution as claimed in claim 1, characterized in that: The silicon carbide substrate, drift layer and current balancing layer are all N-type, and the well region is P-type.