Device for detecting connection state and energy state of ultrasonic scalpel head

Abstract

The utility model discloses a device for detecting the connection state and the energy state of an ultrasonic scalpel head, which comprises a memory and a key signal sampling circuit which are arranged on the ultrasonic scalpel head, and further comprises a processor, a voltage-current conversion circuit, a signal identification circuit, a first signal comparison circuit and a second signal comparison circuit, the processor is electrically connected with the memory through the voltage-current conversion circuit, the memory is electrically connected with the key signal sampling circuit, and the key signal sampling circuit is also electrically connected with the first key and the second key; the input end of the signal identification circuit is electrically connected with the output end of the voltage-current conversion circuit, and the input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both electrically connected with the output end of the signal identification circuit. The output end of the signal identification circuit, the output end of the first signal comparison circuit and the output end of the second signal comparison circuit are electrically connected with the processor. According to the utility model, the connection state and the energy state of the ultrasonic scalpel head can be simultaneously detected.

Description

Technical Field

[0001] The utility model relates to the field of ultrasonic medical equipment, in particular to a device for detecting the connection state and energy state of an ultrasonic blade head. Background Art

[0002] The main components of ultrasonic surgical instruments are ultrasonic scalpels and ultrasonic transducers. The ultrasonic scalpel and ultrasonic transducer are connected together through a connecting line. The ultrasonic transducer converts electrical energy into ultrasonic energy and transmits it to the ultrasonic scalpel; the ultrasonic scalpel concentrates the ultrasonic energy on the ultrasonic blade head to form high-frequency vibration, thereby achieving tissue cutting and completing ultrasonic surgery.

[0003] During actual operation, if the ultrasonic blade head is not connected to the ultrasonic scalpel due to looseness or forgotten connection, the energy in the ultrasonic scalpel host cannot be transmitted to the ultrasonic blade head, and the ultrasonic blade head cannot vibrate, which will cause the operation to be interrupted. Therefore, it is of great significance to detect the connection status of the ultrasonic blade head to ensure the safety and reliability of the ultrasonic operation. In addition, the ultrasonic blade head can usually provide two gears, MAX (maximum gear) and MIN (minimum gear) during operation, which correspond to two different energy states. In different ultrasonic operations or different stages of ultrasonic operations, it is necessary to select the appropriate energy gear according to the actual situation. By detecting the energy state, the safety and reliability of the ultrasonic operation can be further ensured.

[0004] However, there is currently no device that can simultaneously detect the connection state and energy state of an ultrasonic blade. Utility Model Content

[0005] In view of this, the utility model provides a device for detecting the connection state and energy state of an ultrasonic blade head, so as to solve the problem that the existing ultrasonic surgical instruments cannot simultaneously detect the connection state and energy state of the ultrasonic blade head.

[0006] The utility model provides a detection device for the connection state and energy state of an ultrasonic blade head, which is used for an ultrasonic surgical knife. The ultrasonic surgical knife comprises an ultrasonic blade head, and a first key and a second key are arranged on the ultrasonic blade head; the detection device comprises a processor, a memory, a key signal sampling circuit, a voltage-current conversion circuit, a signal recognition circuit, a first signal comparison circuit and a second signal comparison circuit; the memory and the key signal sampling circuit are both arranged on the ultrasonic blade head;

[0007] The output end of the processor is electrically connected to the memory through the voltage-to-current conversion circuit, the memory is electrically connected to the key signal sampling circuit, and the key signal sampling circuit is also electrically connected to both the first key and the second key; the input end of the signal identification circuit is electrically connected to the output end of the voltage-to-current conversion circuit, the input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both electrically connected to the output end of the signal identification circuit, and the output end of the signal identification circuit, the output end of the first signal comparison circuit and the output end of the second signal comparison circuit are all electrically connected to the input end of the processor.

[0008] Optionally, the memory includes a storage chip U7;

[0009] The key signal sampling circuit includes a first resistor R1, a second resistor R2, a first connector J1 and a second connector J2; wherein the first resistor R1 and the second resistor R2 have different resistance values; the first connector J1 and the second connector J2 each have two pins;

[0010] The two pins of the first connector J1 are electrically connected to the first button; the first end of the first resistor R1 is connected to the pin No. 1 of the first connector J1, and is electrically connected to the ground pin GND of the storage chip U7; the second end of the first resistor R1 is connected to the pin No. 2 of the first connector J1;

[0011] The two pins of the second connector J2 are electrically connected to the second button; the first end of the second resistor R2 is connected to the pin No. 1 of the second connector J2, and is electrically connected to the second end of the first resistor R1; the second end of the second resistor R2 is connected to the pin No. 2 of the second connector J2, and is electrically connected to the data pin DQ of the storage chip U7;

[0012] The ground pin GND of the memory chip U7 is also connected to the isolation ground GND_ISO, and the data pin DQ of the memory chip U7 is also electrically connected to the output end of the voltage-to-current conversion circuit.

[0013] Optionally, the voltage-current conversion circuit includes an isolation subcircuit and a conversion subcircuit;

[0014] The output end of the processor is electrically connected to the conversion subcircuit through the isolation subcircuit, and the output end of the conversion subcircuit is electrically connected to the memory, the key signal sampling circuit and the input end of the signal recognition circuit.

[0015] Optionally, the conversion subcircuit includes a voltage-current conversion chip U8, a first MOS tube Q9, a transistor Q2, a Schottky diode D1, a first resistor R76, a second resistor R80, a third resistor R83, a fourth resistor R88, a fifth resistor R93, a sixth resistor R101, a seventh resistor R117, an eighth resistor R118, a ninth resistor R121, a first capacitor C13 and a second capacitor C26;

[0016] The signal input pin VIN of the voltage-current conversion chip U8 is electrically connected to the output end of the isolation sub-circuit through the seventh resistor R117; the positive power pin VSP of the voltage-current conversion chip U8 is electrically connected to the +12V isolation power end through the sixth resistor R101, and the positive power pin VSP of the voltage-current conversion chip U8 is also electrically connected to the +5V isolation power end through the fifth resistor R93, and the positive power pin VSP of the voltage-current conversion chip U8 is also connected to the isolation ground GND_ISO through the first capacitor C13; the reference feedback pin REGF of the voltage-current conversion chip U8 is electrically connected to the +5V reference power end, and the reference feedback pin REGF of the voltage-current conversion chip U8 is also connected to the isolation ground GND_ISO through the second resistor R80 and the third resistor R83 in sequence; the reference ground pin REGS of the voltage-current conversion chip U8 is connected to the common connection end between the second resistor R80 and the third resistor R83;

[0017] The amplifier feedback pin of the voltage-to-current conversion chip U8 The ground pin GND and the open drain output pin OD are both connected to the isolated ground GND_ISO, and the resistance setting pin SET of the voltage-current conversion chip U8 is connected to the isolated ground GND_ISO through the ninth resistor R121;

[0018] The base of the transistor Q2 is electrically connected to the source of the first MOS transistor Q9, and the base of the transistor Q2 is also electrically connected to the emitter of the transistor Q2 through the first resistor R76. The current sensing pin IS of the voltage-to-current conversion chip U8 is connected to the common connection end between the first resistor R76 and the emitter of the transistor Q2; the collector of the transistor Q2 is electrically connected to the gain setting pin VG of the voltage-to-current conversion chip U8, and the collector of the transistor Q2 is also electrically connected to the gate of the first MOS transistor Q9. The first end of the eighth resistor R118 is electrically connected to the +5V reference power supply end. The second end of the eighth resistor R118 is connected to the common connection end between the collector of the transistor Q2 and the gate of the first MOS transistor Q9; the drain of the first MOS transistor Q9 is electrically connected to the No. 3 pin of the Schottky diode D1 through the fourth resistor R88, the No. 1 pin of the Schottky diode D1 is suspended, and the No. 2 pin of the Schottky diode D1 is electrically connected to the +5V isolated power supply end; the first end of the second capacitor C26 is connected to the common connection end between the drain of the first MOS transistor Q9 and the fourth resistor R88, and the second end of the second capacitor C26 is connected to the isolated ground GND_ISO.

[0019] Optionally, the voltage-to-current conversion chip U8 is specifically a voltage-to-current converter chip of model XTR111AIDGQR.

[0020] Optionally, the isolation sub-circuit includes a first optical coupler U9, a second MOS tube Q1, a tenth resistor R26, an eleventh resistor R27, a twelfth resistor R75, a thirteenth resistor R77 and a fourteenth resistor R82;

[0021] The gate of the second MOS transistor Q1 is electrically connected to the output end of the processor through the twelfth resistor R75, the gate of the second MOS transistor Q1 is also electrically connected to the +3.3V digital power supply end through the tenth resistor R26, and the source of the second MOS transistor Q1 is connected to the common connection end between the tenth resistor R26 and the +3.3V digital power supply end; the drain of the second MOS transistor Q1 is electrically connected to the input positive electrode of the first optical coupler U9, the first end of the eleventh resistor R27 is electrically connected to the +3.3V digital power supply end, and the second end of the eleventh resistor R27 is connected to the common connection end between the drain of the second MOS transistor Q1 and the input positive electrode of the first optical coupler U9; the input negative electrode of the first optical coupler U9 is connected to the digital ground DGND through the fourteenth resistor R82;

[0022] The power pin of the first optocoupler U9 is electrically connected to the +3.3V isolated power supply terminal, the output pin of the first optocoupler U9 is electrically connected to the input terminal of the conversion sub-circuit, the first end of the thirteenth resistor R77 is connected to the common connection terminal between the power pin of the first optocoupler U9 and the +3.3V isolated power supply terminal, and the second end of the thirteenth resistor R77 is connected to the common connection terminal between the output pin of the first optocoupler U9 and the input terminal of the conversion sub-circuit; the ground pin of the first optocoupler U9 is connected to the isolated ground GND_ISO.

[0023] Optionally, the signal recognition circuit includes a second optical coupler U24, a third MOS tube Q7, a fifteenth resistor R89, a sixteenth resistor R95, a seventeenth resistor R96, an eighteenth resistor R102 and a nineteenth resistor R103;

[0024] The gate of the third MOS tube Q7 is electrically connected to the output end of the voltage-current conversion circuit, and the gate of the third MOS tube Q7 is also connected to the isolation ground GND_ISO through the fifteenth resistor R89 ​​and the nineteenth resistor R103 in sequence. The input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both connected to the common connection end between the fifteenth resistor R89 ​​and the nineteenth resistor R103; the source of the third MOS tube Q7 is electrically connected to the +3.3V isolation power supply end; the drain of the third MOS tube Q7 is electrically connected to the input positive electrode of the second optical coupler U24 through the sixteenth resistor R95. The negative input electrode of the second optocoupler U24 is connected to the isolation ground GND_ISO through the eighteenth resistor R102; the power pin of the second optocoupler U24 is electrically connected to the +3.3V digital power terminal, the output pin of the second optocoupler U24 is electrically connected to the input terminal of the processor, the first end of the seventeenth resistor R96 is connected to the common connection terminal between the power pin of the second optocoupler U24 and the +3.3V digital power terminal, and the second end of the seventeenth resistor R96 is connected to the common connection terminal between the output pin of the second optocoupler U24 and the processor; the ground pin of the second optocoupler U24 is connected to the digital ground DGND.

[0025] Optionally, the first signal comparison circuit includes a first comparator U29A, a third optical coupler U11, a twentieth resistor R90, a twenty-first resistor R106, a twenty-second resistor R109, a twenty-third resistor R110, a twenty-fourth resistor R111 and a third capacitor C116;

[0026] The power pin of the first comparator U29A is electrically connected to the +12V isolated power supply terminal, and the ground pin of the first comparator U29A is connected to the isolated ground GND_ISO; the positive input pin of the first comparator U29A is electrically connected to the output terminal of the signal recognition circuit through the 24th resistor R111, the inverting input pin of the first comparator U29A is electrically connected to the +3.3V isolated power supply terminal through the 21st resistor R106, and the inverting input pin of the first comparator U29A is also connected to the isolated ground GND_ISO through the 22nd resistor R109, the first end of the third capacitor C116 is connected to the common connection end between the inverting input pin of the first comparator U29A and the 22nd resistor R109, and the second end of the third capacitor C116 is connected to the isolated ground GND_ISO;

[0027] The output pin of the first comparator U29A is electrically connected to the positive input electrode of the third optocoupler U11, the first end of the twenty-third resistor R110 is connected to the common connection end between the output pin of the first comparator U29A and the positive input electrode of the third optocoupler U11, and the second end of the twenty-third resistor R110 is electrically connected to the +3.3V isolated power supply end; the input negative electrode of the third optocoupler U11 is connected to the isolation ground GND_ISO; the power pin of the third optocoupler U11 is electrically connected to the +3.3V digital power supply end, the output pin of the third optocoupler U11 is electrically connected to the input end of the processor, the first end of the twentieth resistor R90 is connected to the common connection end between the power pin of the third optocoupler U11 and the +3.3V digital power supply end, and the second end of the twentieth resistor R90 is connected to the common connection end between the output pin of the third optocoupler U11 and the input end of the processor; the ground pin of the third optocoupler U11 is connected to the digital ground DGND.

[0028] Optionally, the second signal comparison circuit includes a second comparator U29B, a fourth optical coupler U30, a twenty-fifth resistor R112, a twenty-sixth resistor R113, a twenty-seventh resistor R114, a twenty-eighth resistor R115, a twenty-ninth resistor R116 and a fourth capacitor C118;

[0029] The non-inverting input pin of the second comparator U29B is electrically connected to the output end of the signal recognition circuit through the twenty-ninth resistor R116, the inverting input pin of the second comparator U29B is electrically connected to the +3.3V isolated power supply end through the twenty-fifth resistor R112, the inverting input pin of the second comparator U29B is also connected to the isolation ground GND_ISO through the twenty-sixth resistor R113, the first end of the fourth capacitor C118 is connected to the common connection end between the inverting input pin of the second comparator U29B and the twenty-sixth resistor R113, and the second end of the fourth capacitor C118 is connected to the isolation ground GND_ISO;

[0030] The output pin of the second comparator U29B is electrically connected to the positive input electrode of the fourth optocoupler U30, the first end of the twenty-seventh resistor R114 is connected to the common connection end between the output pin of the second comparator U29B and the positive input electrode of the fourth optocoupler U30, and the second end of the twenty-seventh resistor R114 is electrically connected to the +3.3V isolated power supply end; the input negative electrode of the fourth optocoupler U30 is connected to the isolation ground GND_ISO; the power pin of the fourth optocoupler U30 is electrically connected to the +3.3V digital power supply end, the output pin of the fourth optocoupler U30 is electrically connected to the input end of the processor, the first end of the twenty-eighth resistor R115 is connected to the common connection end between the power pin of the fourth optocoupler U30 and the +3.3V digital power supply end, and the second end of the twenty-eighth resistor R115 is connected to the common connection end between the output pin of the fourth optocoupler U30 and the input end of the processor; the ground pin of the fourth optocoupler U30 is connected to the digital ground DGND.

[0031] Optionally, the processor is specifically a LFE2-6E-5F256I model FPGA chip.

[0032] The beneficial effects of the utility model are as follows: the memory is electrically connected to the output end of the processor through the voltage-current conversion circuit, and can store the current signal converted by the voltage-current conversion circuit of the control instruction output by the processor; at the same time, the memory is also electrically connected to the key signal sampling circuit, and can store the voltage signal generated by the key signal sampling circuit. Since the memory is connected to the voltage-current conversion circuit, and the output end of the voltage-current conversion circuit is electrically connected to the signal recognition circuit, and the output end of the signal recognition circuit is electrically connected to the processor, the voltage signal stored in the memory can be fed back to the processor through the signal recognition circuit. Based on the memory, the voltage-current conversion circuit and the signal recognition circuit, two-way communication between the ultrasonic scalpel head and the processor can be achieved; since the memory and the key signal sampling circuit are arranged on the ultrasonic scalpel head, when the ultrasonic scalpel is in an unconnected state due to loosening or forgetting to connect, the signal recognized by the signal recognition circuit is in a constant state; and when the ultrasonic scalpel head is in an unconnected state due to loosening or forgetting to connect, the signal recognized by the signal recognition circuit is in a constant state; and when the ultrasonic scalpel head is in an unconnected state due to loosening or forgetting to connect, the signal recognized by the signal recognition circuit is in a constant state. When in the connected state, the signal recognized by the signal recognition circuit will change before and after the ultrasonic blade is connected. Therefore, the detection of the connection state of the ultrasonic blade can be achieved through the signal feedback between the signal recognition circuit and the processor; the first button and the second button of the ultrasonic blade represent two different energy states of the ultrasonic blade. Since the button signal sampling circuit is electrically connected to the first button and the second button, the connection of different buttons will cause the change of the voltage signal generated by the button signal sampling circuit, which will cause the change of the input signal and the output signal of the signal recognition circuit based on the connection relationship between the memory and the signal recognition circuit. Since the input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both electrically connected to the output end of the signal recognition circuit, the comparison function of the first signal comparison circuit and the second signal comparison circuit on the output signal of the signal recognition circuit can be used to realize the recognition of different button gears, that is, the recognition of the energy state of the ultrasonic blade is realized;

[0033] The ultrasonic blade head connection state and energy state detection device of the utility model can simultaneously detect the connection state and energy state of the ultrasonic blade head, effectively ensuring the safety and reliability of ultrasonic surgery. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The features and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way. In the accompanying drawings:

[0035] Figure 1 A structural diagram of a device for detecting the connection state and energy state of an ultrasonic blade head in the utility model is shown;

[0036] Figure 2 The design diagram of the memory and the key signal sampling circuit in the embodiment of the utility model is shown;

[0037] Figure 3The design diagram of the voltage-current conversion circuit in the embodiment of the utility model is shown;

[0038] Figure 4 The design diagram of the signal recognition circuit in the embodiment of the utility model is shown;

[0039] Figure 5 The design diagram of the first signal comparison circuit in the embodiment of the utility model is shown;

[0040] Figure 6 The design diagram of the second signal comparison circuit in the embodiment of the utility model is shown;

[0041] Figure 7 A complete structural model diagram of the electrical signal acquisition device of the ultrasonic surgical knife in the embodiment of the utility model is shown;

[0042] Fig. 8A The design diagram of the +12V isolated power supply sub-circuit in the embodiment of the utility model is shown;

[0043] Figure 8B The design diagram of the +5V isolated power supply sub-circuit in the embodiment of the utility model is shown;

[0044] Figure 8C The design diagram of the +3.3V isolated power supply sub-circuit in the embodiment of the utility model is shown;

[0045] Fig.8D The design diagram of the +3.3V digital power subcircuit in the embodiment of the utility model is shown. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0047] like Figure 1 As shown, a detection device for the connection state and energy state of an ultrasonic blade head is used for an ultrasonic surgical knife, the ultrasonic surgical knife comprises an ultrasonic blade head, and the ultrasonic blade head is provided with a first key and a second key; the detection device comprises a processor, a memory, a key signal sampling circuit, a voltage-current conversion circuit, a signal recognition circuit, a first signal comparison circuit and a second signal comparison circuit; the memory and the key signal sampling circuit are both provided on the ultrasonic blade head;

[0048] The output end of the processor is electrically connected to the memory through the voltage-to-current conversion circuit, the memory is electrically connected to the key signal sampling circuit, and the key signal sampling circuit is also electrically connected to both the first key and the second key; the input end of the signal identification circuit is electrically connected to the output end of the voltage-to-current conversion circuit, the input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both electrically connected to the output end of the signal identification circuit, and the output end of the signal identification circuit, the output end of the first signal comparison circuit and the output end of the second signal comparison circuit are all electrically connected to the input end of the processor.

[0049] In the present embodiment, the memory is electrically connected to the output end of the processor through the voltage-to-current conversion circuit, and can store the current signal converted by the voltage-to-current conversion circuit of the control instruction output by the processor; at the same time, the memory is also electrically connected to the key signal sampling circuit, and can store the voltage signal generated by the key signal sampling circuit. Since the memory is connected to the voltage-to-current conversion circuit, and the output end of the voltage-to-current conversion circuit is electrically connected to the signal recognition circuit, and the output end of the signal recognition circuit is electrically connected to the processor, the voltage signal stored in the memory can be fed back to the processor through the signal recognition circuit. Based on the memory, the voltage-to-current conversion circuit and the signal recognition circuit, two-way communication between the ultrasonic blade head and the processor can be achieved; since the memory and the key signal sampling circuit are arranged on the ultrasonic blade head, when the ultrasonic surgical knife is in an unconnected state due to loosening or forgetting to connect, the signal recognized by the signal recognition circuit is in a constant state; and when the ultrasonic blade head is in When in the connected state, the signal recognized by the signal recognition circuit will change before and after the ultrasonic blade is connected. Therefore, the detection of the connection state of the ultrasonic blade can be achieved through the signal feedback between the signal recognition circuit and the processor; the first button and the second button of the ultrasonic blade represent two different energy states of the ultrasonic blade. Since the button signal sampling circuit is electrically connected to the first button and the second button, the connection of different buttons will cause the change of the voltage signal generated by the button signal sampling circuit, which will cause the change of the input signal and the output signal of the signal recognition circuit based on the connection relationship between the memory and the signal recognition circuit. Since the input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both electrically connected to the output end of the signal recognition circuit, the comparison function of the first signal comparison circuit and the second signal comparison circuit on the output signal of the signal recognition circuit can be used to realize the recognition of different button gears, that is, the recognition of the energy state of the ultrasonic blade is realized.

[0050] The device for detecting the connection status and energy status of the ultrasonic blade head of the present embodiment can simultaneously detect the connection status and energy status of the ultrasonic blade head, thereby effectively ensuring the safety and reliability of ultrasonic surgery.

[0051] It should be noted that the utility model realizes the simultaneous detection of the connection state and the energy state by improving the hardware circuits in the ultrasonic surgical knife and the electrical connection relationship between the hardware circuits, and does not involve the improvement of the computer program. The computer programs involved are all existing computer programs, and the corresponding computer programs are pre-stored in the memory or storage area of ​​each circuit chip.

[0052] Specifically, in this embodiment, the processor is a FPGA chip of model LFE2-6E-5F256I.

[0053] The LFE2-6E-5F256I is a programmable logic device (FPGA device) that can realize the logic functions of digital circuits, can realize complex digital circuit design, high-speed data transmission and processing; supports multiple standard interface protocols, such as PCIExpress, Gigabit Ethernet, DDR3, etc., and can easily communicate with other devices. In this embodiment, the FPGA chip based on the LFE2-6E-5F256I model can realize two-way communication with the memory in the ultrasonic blade head based on the voltage-current conversion circuit and the signal recognition circuit, thereby facilitating the simultaneous detection of the connection status and energy status of the ultrasonic blade head.

[0054] Preferably, if Figure 2 As shown, the memory includes a storage chip U7;

[0055] The key signal sampling circuit includes a first resistor R1, a second resistor R2, a first connector J1 and a second connector J2; wherein the first resistor R1 and the second resistor R2 have different resistance values; the first connector J1 and the second connector J2 each have two pins;

[0056] The two pins of the first connector J1 are electrically connected to the first button; the first end of the first resistor R1 is connected to the pin No. 1 of the first connector J1, and is electrically connected to the ground pin GND of the storage chip U7; the second end of the first resistor R1 is connected to the pin No. 2 of the first connector J1;

[0057] The two pins of the second connector J2 are electrically connected to the second button; the first end of the second resistor R2 is connected to the pin No. 1 of the second connector J2, and is electrically connected to the second end of the first resistor R1; the second end of the second resistor R2 is connected to the pin No. 2 of the second connector J2, and is electrically connected to the data pin DQ of the storage chip U7;

[0058] The ground pin GND of the memory chip U7 is also connected to the isolation ground GND_ISO, and the data pin DQ of the memory chip U7 is also electrically connected to the output end of the voltage-to-current conversion circuit.

[0059] In the above-mentioned key signal sampling circuit, the first resistor R1 and the second resistor R2 form a series circuit structure. Since the data pin DQ of the storage chip U7 is electrically connected to the output end of the voltage-current conversion circuit, and the second end of the second resistor R2 is connected to the data pin DQ of the storage chip U7, the current signal (i.e., Figure 2 The HP_SIG signal in the voltage-current conversion circuit is transmitted to the first resistor R1 and the second resistor R2, and a voltage signal is generated in the series circuit structure composed of the two resistors; and because the two ends of the series circuit structure composed of the two resistors are electrically connected to the storage chip respectively, the voltage signal generated by the series circuit structure can be stored in the storage chip U7, and fed back to the output end of the voltage-current conversion circuit through the storage chip U7, and then the signal is recognized through the signal recognition circuit, thereby facilitating the detection of the connection state and the energy state respectively.

[0060] Among them, when the ultrasonic blade head is in an unconnected state, the current signal generated in the voltage-to-current conversion circuit will not be transmitted to the series structure composed of two resistors; when the ultrasonic blade head is in a connected state, the current signal generated in the voltage-to-current conversion circuit will be transmitted to the series structure composed of two resistors, which will inevitably cause a change in the signal transmitted by the memory to the output end of the voltage-to-current conversion circuit, and then cause a change in the signal at the input end of the signal recognition circuit, thereby realizing the detection of the detection state of the ultrasonic blade head.

[0061] Furthermore, if the ultrasonic blade head is in a connected state, during the actual working process of the ultrasonic blade head, only one of the first button and the second button will be connected at the same time; when the first button is connected, the first resistor R1 will be short-circuited, and the voltage signal in the entire series circuit structure will be reduced; when the second button is connected, the second resistor R1 will be short-circuited, and the voltage signal in the entire series circuit structure will also be reduced; when neither the first button nor the second button is connected, the voltage signal in the entire series circuit structure is the largest; therefore, the resistance values ​​of the first resistor R1 and the second resistor R2 in this embodiment are different, which can facilitate the generation of different voltage signals when the first button and the second button are connected respectively, so as to facilitate the subsequent use of the signal recognition circuit, the first signal comparison circuit and the second signal comparison circuit to compare the signals to realize the identification of the connection state of the two resistors, and then realize the identification of the ultrasonic blade head button position (ie, energy state).

[0062] Specifically, the memory of this embodiment adopts a GX2431D model memory, which has high-speed data reading, writing and transmission capabilities, large storage capacity, low power consumption, high reliability and good compatibility, and can facilitate two-way communication between the ultrasonic blade head and the processor, thereby facilitating the simultaneous detection of the connection status and energy status of the ultrasonic blade head.

[0063] In this embodiment, the resistance values ​​of the first resistor R1 and the second resistor R2 are different, and appropriate resistance values ​​can be selected according to actual conditions, for example, R1 is 10kΩ and R2 is 20kΩ; when the ultrasonic blade is in a connected state, assuming that the current output by the voltage-to-current conversion circuit is 0.1mA, then when the first button is connected (R1 is short-circuited), the voltage across the series circuit structure composed of the two resistors is 2V; when the second button is connected (R2 is short-circuited), the voltage across the series circuit structure composed of the two resistors is 1V; when neither the first button nor the second button is connected (neither R1 nor R2 is short-circuited), the voltage across the series circuit structure composed of the two resistors is 3V.

[0064] Preferably, the voltage-current conversion circuit includes an isolation subcircuit and a conversion subcircuit;

[0065] The output end of the processor is electrically connected to the conversion subcircuit through the isolation subcircuit, and the output end of the conversion subcircuit is electrically connected to the memory, the key signal sampling circuit and the input end of the signal recognition circuit.

[0066] Connecting an isolation subcircuit between the processor and the conversion subcircuit can achieve electrical protection, thereby ensuring that the entire voltage-to-current conversion circuit can achieve voltage-to-current conversion safely and reliably.

[0067] Preferably, if Figure 3 As shown, the conversion subcircuit includes a voltage-current conversion chip U8, a first MOS tube Q9, a transistor Q2, a Schottky diode D1, a first resistor R76, a second resistor R80, a third resistor R83, a fourth resistor R88, a fifth resistor R93, a sixth resistor R101, a seventh resistor R117, an eighth resistor R118, a ninth resistor R121, a first capacitor C13 and a second capacitor C26;

[0068] The signal input pin VIN of the voltage-current conversion chip U8 is electrically connected to the output end of the isolation sub-circuit through the seventh resistor R117; the positive power pin VSP of the voltage-current conversion chip U8 is electrically connected to the +12V isolation power end through the sixth resistor R101, and the positive power pin VSP of the voltage-current conversion chip U8 is also electrically connected to the +5V isolation power end through the fifth resistor R93, and the positive power pin VSP of the voltage-current conversion chip U8 is also connected to the isolation ground GND_ISO through the first capacitor C13; the reference feedback pin REGF of the voltage-current conversion chip U8 is electrically connected to the +5V reference power end, and the reference feedback pin REGF of the voltage-current conversion chip U8 is also connected to the isolation ground GND_ISO through the second resistor R80 and the third resistor R83 in sequence; the reference ground pin REGS of the voltage-current conversion chip U8 is connected to the common connection end between the second resistor R80 and the third resistor R83;

[0069] The amplifier feedback pin of the voltage-to-current conversion chip U8 The ground pin GND and the open drain output pin OD are both connected to the isolated ground GND_ISO, and the resistance setting pin SET of the voltage-current conversion chip U8 is connected to the isolated ground GND_ISO through the ninth resistor R121;

[0070] The base of the transistor Q2 is electrically connected to the source of the first MOS transistor Q9, and the base of the transistor Q2 is also electrically connected to the emitter of the transistor Q2 through the first resistor R76. The current sensing pin IS of the voltage-to-current conversion chip U8 is connected to the common connection end between the first resistor R76 and the emitter of the transistor Q2; the collector of the transistor Q2 is electrically connected to the gain setting pin VG of the voltage-to-current conversion chip U8, and the collector of the transistor Q2 is also electrically connected to the gate of the first MOS transistor Q9. The first end of the eighth resistor R118 is electrically connected to the +5V reference power supply end. The second end of the eighth resistor R118 is connected to the common connection end between the collector of the transistor Q2 and the gate of the first MOS transistor Q9; the drain of the first MOS transistor Q9 is electrically connected to the No. 3 pin of the Schottky diode D1 through the fourth resistor R88, the No. 1 pin of the Schottky diode D1 is suspended, and the No. 2 pin of the Schottky diode D1 is electrically connected to the +5V isolated power supply end; the first end of the second capacitor C26 is connected to the common connection end between the drain of the first MOS transistor Q9 and the fourth resistor R88, and the second end of the second capacitor C26 is connected to the isolated ground GND_ISO.

[0071] Preferably, if Figure 3As shown, the isolation sub-circuit includes a first optical coupler U9, a second MOS tube Q1, a tenth resistor R26, an eleventh resistor R27, a twelfth resistor R75, a thirteenth resistor R77 and a fourteenth resistor R82;

[0072] The gate of the second MOS transistor Q1 is electrically connected to the output end of the processor through the twelfth resistor R75, the gate of the second MOS transistor Q1 is also electrically connected to the +3.3V digital power supply end through the tenth resistor R26, and the source of the second MOS transistor Q1 is connected to the common connection end between the tenth resistor R26 and the +3.3V digital power supply end; the drain of the second MOS transistor Q1 is electrically connected to the input positive electrode of the first optical coupler U9, the first end of the eleventh resistor R27 is electrically connected to the +3.3V digital power supply end, and the second end of the eleventh resistor R27 is connected to the common connection end between the drain of the second MOS transistor Q1 and the input positive electrode of the first optical coupler U9; the input negative electrode of the first optical coupler U9 is connected to the digital ground DGND through the fourteenth resistor R82;

[0073] The power pin of the first optocoupler U9 is electrically connected to the +3.3V isolated power supply terminal, the output pin of the first optocoupler U9 is electrically connected to the input terminal of the conversion sub-circuit, the first end of the thirteenth resistor R77 is connected to the common connection terminal between the power pin of the first optocoupler U9 and the +3.3V isolated power supply terminal, and the second end of the thirteenth resistor R77 is connected to the common connection terminal between the output pin of the first optocoupler U9 and the input terminal of the conversion sub-circuit; the ground pin of the first optocoupler U9 is connected to the isolated ground GND_ISO.

[0074] Through the conversion sub-circuit and isolation sub-circuit of the above circuit structure, it is possible to achieve voltage-current conversion and significantly improve the safety, stability and reliability of the voltage-current conversion process, thereby ensuring the normal operation of the equipment in a complex environment.

[0075] Specifically, in Figure 3 In the example, the signal input to the processor is the S_IN signal, and the signal output after the voltage-to-current conversion circuit is the HP_SIG signal.

[0076] Specifically, in this embodiment, the voltage-to-current conversion chip U8 is specifically a voltage-to-current converter chip of the XTR111AIDGQR model, which has the advantages of high precision, wide input voltage range, built-in current sampling circuit, high linearity and flexible configuration options; the first optical coupler U9 uses an optical coupler of the 6N137SDM model, which has the advantages of high performance, high precision, high reliability and a wide range of applications; the specifications of each MOS tube, triode, resistor, capacitor and diode in the conversion sub-circuit and the isolation sub-circuit are detailed in Figure 3 As shown, no more listing is given here.

[0077] Preferably, if Figure 4 As shown, the signal recognition circuit includes a second optical coupler U24, a third MOS tube Q7, a fifteenth resistor R89, a sixteenth resistor R95, a seventeenth resistor R96, an eighteenth resistor R102 and a nineteenth resistor R103;

[0078] The gate of the third MOS tube Q7 is electrically connected to the output end of the voltage-current conversion circuit, and the gate of the third MOS tube Q7 is also connected to the isolation ground GND_ISO through the fifteenth resistor R89 ​​and the nineteenth resistor R103 in sequence. The input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both connected to the common connection end between the fifteenth resistor R89 ​​and the nineteenth resistor R103; the source of the third MOS tube Q7 is electrically connected to the +3.3V isolation power supply end; the drain of the third MOS tube Q7 is electrically connected to the input positive electrode of the second optical coupler U24 through the sixteenth resistor R95. The negative input electrode of the second optocoupler U24 is connected to the isolation ground GND_ISO through the eighteenth resistor R102; the power pin of the second optocoupler U24 is electrically connected to the +3.3V digital power terminal, the output pin of the second optocoupler U24 is electrically connected to the input terminal of the processor, the first end of the seventeenth resistor R96 is connected to the common connection terminal between the power pin of the second optocoupler U24 and the +3.3V digital power terminal, and the second end of the seventeenth resistor R96 is connected to the common connection terminal between the output pin of the second optocoupler U24 and the processor; the ground pin of the second optocoupler U24 is connected to the digital ground DGND.

[0079] In the signal recognition circuit of the above circuit structure, the current signal output from the output end of the voltage-current conversion circuit (i.e. Figure 4 The HP_SIG signal in the signal is sent to the processor (i.e. Figure 4 In the S_OUT signal in the ultrasonic cutter head, the signal recognition and feedback for detecting the connection status of the ultrasonic cutter head are realized; on the other hand, the voltage signal (i.e. Figure 4 The SW_OUT signal in the signal is then sent to the first signal comparison circuit and the second signal comparison circuit respectively, so as to realize the recognition and comparison of different voltage signals caused by different key access, thereby facilitating the detection of the energy state of the ultrasonic blade. Among them, the second optical coupler U24 is connected between the third MOS tube Q7 and the processor, which can achieve better electrical isolation in the signal feedback process, ensuring the safety, reliability and stability of the signal feedback.

[0080] In this embodiment, the second optical coupler U24 also uses an optical coupler of the 6N137SDM model. The specifications of the MOS tube and each resistor in the signal recognition circuit are detailed in Figure 4 As shown, no more listing is given here.

[0081] Preferably, if Figure 5 As shown, the first signal comparison circuit includes a first comparator U29A, a third optical coupler U11, a twentieth resistor R90, a twenty-first resistor R106, a twenty-second resistor R109, a twenty-third resistor R110, a twenty-fourth resistor R111 and a third capacitor C116;

[0082] The power pin of the first comparator U29A is electrically connected to the +12V isolated power supply terminal, and the ground pin of the first comparator U29A is connected to the isolated ground GND_ISO; the positive input pin of the first comparator U29A is electrically connected to the output terminal of the signal recognition circuit through the 24th resistor R111, the inverting input pin of the first comparator U29A is electrically connected to the +3.3V isolated power supply terminal through the 21st resistor R106, and the inverting input pin of the first comparator U29A is also connected to the isolated ground GND_ISO through the 22nd resistor R109, the first end of the third capacitor C116 is connected to the common connection end between the inverting input pin of the first comparator U29A and the 22nd resistor R109, and the second end of the third capacitor C116 is connected to the isolated ground GND_ISO;

[0083] The output pin of the first comparator U29A is electrically connected to the positive input electrode of the third optocoupler U11, the first end of the twenty-third resistor R110 is connected to the common connection end between the output pin of the first comparator U29A and the positive input electrode of the third optocoupler U11, and the second end of the twenty-third resistor R110 is electrically connected to the +3.3V isolated power supply end; the input negative electrode of the third optocoupler U11 is connected to the isolation ground GND_ISO; the power pin of the third optocoupler U11 is electrically connected to the +3.3V digital power supply end, the output pin of the third optocoupler U11 is electrically connected to the input end of the processor, the first end of the twentieth resistor R90 is connected to the common connection end between the power pin of the third optocoupler U11 and the +3.3V digital power supply end, and the second end of the twentieth resistor R90 is connected to the common connection end between the output pin of the third optocoupler U11 and the input end of the processor; the ground pin of the third optocoupler U11 is connected to the digital ground DGND.

[0084] Preferably, if Figure 6As shown, the second signal comparison circuit includes a second comparator U29B, a fourth optical coupler U30, a twenty-fifth resistor R112, a twenty-sixth resistor R113, a twenty-seventh resistor R114, a twenty-eighth resistor R115, a twenty-ninth resistor R116 and a fourth capacitor C118;

[0085] The non-inverting input pin of the second comparator U29B is electrically connected to the output end of the signal recognition circuit through the twenty-ninth resistor R116, the inverting input pin of the second comparator U29B is electrically connected to the +3.3V isolated power supply end through the twenty-fifth resistor R112, the inverting input pin of the second comparator U29B is also connected to the isolation ground GND_ISO through the twenty-sixth resistor R113, the first end of the fourth capacitor C118 is connected to the common connection end between the inverting input pin of the second comparator U29B and the twenty-sixth resistor R113, and the second end of the fourth capacitor C118 is connected to the isolation ground GND_ISO;

[0086] The output pin of the second comparator U29B is electrically connected to the positive input electrode of the fourth optocoupler U30, the first end of the twenty-seventh resistor R114 is connected to the common connection end between the output pin of the second comparator U29B and the positive input electrode of the fourth optocoupler U30, and the second end of the twenty-seventh resistor R114 is electrically connected to the +3.3V isolated power supply end; the input negative electrode of the fourth optocoupler U30 is connected to the isolation ground GND_ISO; the power pin of the fourth optocoupler U30 is electrically connected to the +3.3V digital power supply end, the output pin of the fourth optocoupler U30 is electrically connected to the input end of the processor, the first end of the twenty-eighth resistor R115 is connected to the common connection end between the power pin of the fourth optocoupler U30 and the +3.3V digital power supply end, and the second end of the twenty-eighth resistor R115 is connected to the common connection end between the output pin of the fourth optocoupler U30 and the input end of the processor; the ground pin of the fourth optocoupler U30 is connected to the digital ground DGND.

[0087] In the first signal comparison circuit of the above structure, the positive input pin of the first comparator U29A is connected to the signal output by the signal recognition circuit (ie Figure 5 The SW_OUT signal in the first comparator U29A is compared with the threshold value set by the first comparator U29A, and the obtained signal (for example, a level signal 0 or 1) is sent to the processor (i.e. Figure 5 Similarly, in the second signal comparison circuit of the above structure, the positive input pin of the second comparator U29B is connected to the signal output by the signal recognition circuit (ie Figure 6The SW_OUT signal in the output is compared with the threshold value set by the second comparator U29B, and the obtained signal (for example, a level signal of 0 or 1) is sent to the processor (i.e. Figure 6 In the HP_key2 signal in the above structure, the recognition of two different key positions is realized. Similar to the first optical coupler and the second optical coupler mentioned above, in the first signal comparison circuit and the second signal comparison circuit of the above structure, an optical coupler is connected between the comparator and the processor to realize electrical isolation and ensure the safety, reliability and stability of signal comparison.

[0088] The thresholds of the first comparator U29A and the second comparator U29B are different, and can be selected according to the voltage changes caused when the two buttons are connected. In this embodiment, U29A and U29B are two independent voltage comparators in the LM2903 dual voltage comparator. The two independent voltage comparators in the dual voltage comparator of this model share a power input, and the input common mode voltage range includes ground, and can work stably under various power supply conditions.

[0089] In the first signal comparison circuit and the second signal comparison circuit, the third optical coupler U11 and the fourth optical coupler U30 are also 6N137SDM optical couplers. The specifications of the resistors and capacitors are detailed in Figure 5 and Figure 6 As shown, no more listing is given here.

[0090] The complete structural model diagram of the ultrasonic blade connection state and energy state detection device of this embodiment is shown in FIG. Figure 7 As shown, Figure 7 SW1 is the first button and SW2 is the second button.

[0091] Preferably, if Figure 7 As shown, the detection device also includes a power supply circuit;

[0092] The power supply circuit is electrically connected to the processor, the voltage-current conversion circuit, the signal identification circuit, the first signal comparison circuit and the second signal comparison circuit.

[0093] Through the power supply circuit, the required operating voltage (including +12V isolation voltage provided by +12V isolation power supply terminal, +5V isolation voltage provided by +5V isolation power supply terminal, +3V digital voltage provided by +3.3V digital power supply terminal, +3.3V isolation voltage provided by +3.3V isolation power supply terminal, etc.) can be provided to the processor, voltage-to-current conversion circuit, signal identification circuit, first signal comparison circuit and second signal comparison circuit respectively, ensuring that each circuit module can work normally.

[0094] Among them, the memory and key signal sampling circuit arranged on the ultrasonic blade head can be powered by the voltage-to-current conversion circuit when the ultrasonic blade head is in a connected state.

[0095] The power supply circuit includes a +12V isolated power supply subcircuit, a +5V isolated power supply subcircuit, a +3.3V isolated power supply subcircuit and a +3.3V digital power supply subcircuit;

[0096] The input ends of the +12V isolated power subcircuit and the +3.3V digital power subcircuit are both electrically connected to the external +12V analog power supply, and the input ends of the +5V isolated power subcircuit and the +3.3V isolated power subcircuit are both electrically connected to the output end of the +12V isolated power subcircuit; the output end of each isolated subcircuit is electrically connected to the corresponding power supply port in the processor, the voltage-current conversion circuit, the signal identification circuit, the first signal comparison circuit, and the second signal comparison circuit. The specific connection methods all adopt conventional technologies in the circuit field, and the specific details are not repeated here.

[0097] The specific circuit designs of the above-mentioned +12V isolated power subcircuit, +5V isolated power subcircuit, +3.3V isolated power subcircuit and +3.3V digital power subcircuit all adopt conventional designs, such as Figures 8A to 8D As shown, Fig. 8A Specific circuit design for the +12V isolated power sub-circuit, Figure 8B Specific circuit design for the +5V isolated power sub-circuit, Figure 8C Specific circuit design for the +3.3V isolated power subcircuit, Fig.8D This is a specific circuit design of a +3.3V digital power sub-circuit; of course, this embodiment may also adopt other conventional designs, and the specific details will not be repeated here.

[0098] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A device for detecting the connection state and energy state of an ultrasonic blade head, used for an ultrasonic surgical knife, wherein the ultrasonic surgical knife comprises an ultrasonic blade head, and the ultrasonic blade head is provided with a first button and a second button; characterized in that: The detection device includes a processor, a memory, a key signal sampling circuit, a voltage-current conversion circuit, a signal recognition circuit, a first signal comparison circuit and a second signal comparison circuit; the memory and the key signal sampling circuit are both arranged on the ultrasonic cutter head; The output end of the processor is electrically connected to the memory through the voltage-to-current conversion circuit, the memory is electrically connected to the key signal sampling circuit, and the key signal sampling circuit is also electrically connected to both the first key and the second key; the input end of the signal identification circuit is electrically connected to the output end of the voltage-to-current conversion circuit, the input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both electrically connected to the output end of the signal identification circuit, and the output end of the signal identification circuit, the output end of the first signal comparison circuit and the output end of the second signal comparison circuit are all electrically connected to the input end of the processor.

2. The detection device according to claim 1, characterized in that: The memory includes a memory chip U7; The key signal sampling circuit includes a first resistor R1, a second resistor R2, a first connector J1 and a second connector J2; wherein the first resistor R1 and the second resistor R2 have different resistance values; the first connector J1 and the second connector J2 each have two pins; The two pins of the first connector J1 are electrically connected to the first button; the first end of the first resistor R1 is connected to the pin No. 1 of the first connector J1, and is electrically connected to the ground pin GND of the storage chip U7; the second end of the first resistor R1 is connected to the pin No. 2 of the first connector J1; The two pins of the second connector J2 are electrically connected to the second button; the first end of the second resistor R2 is connected to the pin No. 1 of the second connector J2, and is electrically connected to the second end of the first resistor R1; the second end of the second resistor R2 is connected to the pin No. 2 of the second connector J2, and is electrically connected to the data pin DQ of the storage chip U7; The ground pin GND of the memory chip U7 is also connected to the isolation ground GND_ISO, and the data pin DQ of the memory chip U7 is also electrically connected to the output end of the voltage-to-current conversion circuit.

3. The detection device according to claim 1, characterized in that: The voltage-current conversion circuit includes an isolation subcircuit and a conversion subcircuit; The output end of the processor is electrically connected to the conversion subcircuit through the isolation subcircuit, and the output end of the conversion subcircuit is electrically connected to the memory, the key signal sampling circuit and the input end of the signal recognition circuit.

4. The detection device according to claim 3, characterized in that: The conversion subcircuit includes a voltage-current conversion chip U8, a first MOS tube Q9, a triode Q2, a Schottky diode D1, a first resistor R76, a second resistor R80, a third resistor R83, a fourth resistor R88, a fifth resistor R93, a sixth resistor R101, a seventh resistor R117, an eighth resistor R118, a ninth resistor R121, a first capacitor C13 and a second capacitor C26; The signal input pin VIN of the voltage-current conversion chip U8 is electrically connected to the output end of the isolation sub-circuit through the seventh resistor R117; the positive power pin VSP of the voltage-current conversion chip U8 is electrically connected to the +12V isolation power end through the sixth resistor R101, and the positive power pin VSP of the voltage-current conversion chip U8 is also electrically connected to the +5V isolation power end through the fifth resistor R93, and the positive power pin VSP of the voltage-current conversion chip U8 is also connected to the isolation ground GND_ISO through the first capacitor C13; the reference feedback pin REGF of the voltage-current conversion chip U8 is electrically connected to the +5V reference power end, and the reference feedback pin REGF of the voltage-current conversion chip U8 is also connected to the isolation ground GND_ISO through the second resistor R80 and the third resistor R83 in sequence; the reference ground pin REGS of the voltage-current conversion chip U8 is connected to the common connection end between the second resistor R80 and the third resistor R83; The amplifier feedback pin of the voltage-to-current conversion chip U8 The ground pin GND and the open drain output pin OD are both connected to the isolated ground GND_ISO, and the resistance setting pin SET of the voltage-current conversion chip U8 is connected to the isolated ground GND_ISO through the ninth resistor R121; The base of the transistor Q2 is electrically connected to the source of the first MOS transistor Q9, and the base of the transistor Q2 is also electrically connected to the emitter of the transistor Q2 through the first resistor R76. The current sensing pin IS of the voltage-to-current conversion chip U8 is connected to the common connection end between the first resistor R76 and the emitter of the transistor Q2; the collector of the transistor Q2 is electrically connected to the gain setting pin VG of the voltage-to-current conversion chip U8, and the collector of the transistor Q2 is also electrically connected to the gate of the first MOS transistor Q9. The first end of the eighth resistor R118 is electrically connected to the +5V reference power supply end. The second end of the eighth resistor R118 is connected to the common connection end between the collector of the transistor Q2 and the gate of the first MOS transistor Q9; the drain of the first MOS transistor Q9 is electrically connected to the No. 3 pin of the Schottky diode D1 through the fourth resistor R88, the No. 1 pin of the Schottky diode D1 is suspended, and the No. 2 pin of the Schottky diode D1 is electrically connected to the +5V isolated power supply end; the first end of the second capacitor C26 is connected to the common connection end between the drain of the first MOS transistor Q9 and the fourth resistor R88, and the second end of the second capacitor C26 is connected to the isolated ground GND_ISO.

5. The detection device according to claim 4, characterized in that: The voltage-to-current conversion chip U8 is specifically a voltage-to-current converter chip of model XTR111AIDGQR.

6. The detection device according to claim 3, characterized in that: The isolation sub-circuit includes a first optical coupler U9, a second MOS tube Q1, a tenth resistor R26, an eleventh resistor R27, a twelfth resistor R75, a thirteenth resistor R77 and a fourteenth resistor R82; The gate of the second MOS transistor Q1 is electrically connected to the output end of the processor through the twelfth resistor R75, the gate of the second MOS transistor Q1 is also electrically connected to the +3.3V digital power supply end through the tenth resistor R26, and the source of the second MOS transistor Q1 is connected to the common connection end between the tenth resistor R26 and the +3.3V digital power supply end; the drain of the second MOS transistor Q1 is electrically connected to the input positive electrode of the first optical coupler U9, the first end of the eleventh resistor R27 is electrically connected to the +3.3V digital power supply end, and the second end of the eleventh resistor R27 is connected to the common connection end between the drain of the second MOS transistor Q1 and the input positive electrode of the first optical coupler U9; the input negative electrode of the first optical coupler U9 is connected to the digital ground DGND through the fourteenth resistor R82; The power pin of the first optocoupler U9 is electrically connected to the +3.3V isolated power supply terminal, the output pin of the first optocoupler U9 is electrically connected to the input terminal of the conversion sub-circuit, the first end of the thirteenth resistor R77 is connected to the common connection terminal between the power pin of the first optocoupler U9 and the +3.3V isolated power supply terminal, and the second end of the thirteenth resistor R77 is connected to the common connection terminal between the output pin of the first optocoupler U9 and the input terminal of the conversion sub-circuit; the ground pin of the first optocoupler U9 is connected to the isolated ground GND_ISO.

7. The detection device according to claim 1, characterized in that: The signal recognition circuit includes a second optical coupler U24, a third MOS tube Q7, a fifteenth resistor R89, a sixteenth resistor R95, a seventeenth resistor R96, an eighteenth resistor R102 and a nineteenth resistor R103; The gate of the third MOS tube Q7 is electrically connected to the output end of the voltage-current conversion circuit, and the gate of the third MOS tube Q7 is also connected to the isolation ground GND_ISO through the fifteenth resistor R89 ​​and the nineteenth resistor R103 in sequence. The input end of the first signal comparison circuit and the input end of the second signal comparison circuit are both connected to the common connection end between the fifteenth resistor R89 ​​and the nineteenth resistor R103; the source of the third MOS tube Q7 is electrically connected to the +3.3V isolation power supply end; the drain of the third MOS tube Q7 is electrically connected to the input positive electrode of the second optical coupler U24 through the sixteenth resistor R95. The negative input electrode of the second optocoupler U24 is connected to the isolation ground GND_ISO through the eighteenth resistor R102; the power pin of the second optocoupler U24 is electrically connected to the +3.3V digital power terminal, the output pin of the second optocoupler U24 is electrically connected to the input terminal of the processor, the first end of the seventeenth resistor R96 is connected to the common connection terminal between the power pin of the second optocoupler U24 and the +3.3V digital power terminal, and the second end of the seventeenth resistor R96 is connected to the common connection terminal between the output pin of the second optocoupler U24 and the processor; the ground pin of the second optocoupler U24 is connected to the digital ground DGND.

8. The detection device according to claim 1, characterized in that: The first signal comparison circuit includes a first comparator U29A, a third optical coupler U11, a twentieth resistor R90, a twenty-first resistor R106, a twenty-second resistor R109, a twenty-third resistor R110, a twenty-fourth resistor R111 and a third capacitor C116; The power pin of the first comparator U29A is electrically connected to the +12V isolated power supply terminal, and the ground pin of the first comparator U29A is connected to the isolated ground GND_ISO; the positive input pin of the first comparator U29A is electrically connected to the output terminal of the signal recognition circuit through the 24th resistor R111, the inverting input pin of the first comparator U29A is electrically connected to the +3.3V isolated power supply terminal through the 21st resistor R106, and the inverting input pin of the first comparator U29A is also connected to the isolated ground GND_ISO through the 22nd resistor R109, the first end of the third capacitor C116 is connected to the common connection end between the inverting input pin of the first comparator U29A and the 22nd resistor R109, and the second end of the third capacitor C116 is connected to the isolated ground GND_ISO; The output pin of the first comparator U29A is electrically connected to the positive input electrode of the third optocoupler U11, the first end of the twenty-third resistor R110 is connected to the common connection end between the output pin of the first comparator U29A and the positive input electrode of the third optocoupler U11, and the second end of the twenty-third resistor R110 is electrically connected to the +3.3V isolated power supply end; the input negative electrode of the third optocoupler U11 is connected to the isolation ground GND_ISO; the power pin of the third optocoupler U11 is electrically connected to the +3.3V digital power supply end, the output pin of the third optocoupler U11 is electrically connected to the input end of the processor, the first end of the twentieth resistor R90 is connected to the common connection end between the power pin of the third optocoupler U11 and the +3.3V digital power supply end, and the second end of the twentieth resistor R90 is connected to the common connection end between the output pin of the third optocoupler U11 and the input end of the processor; the ground pin of the third optocoupler U11 is connected to the digital ground DGND.

9. The detection device according to claim 8, characterized in that: The second signal comparison circuit includes a second comparator U29B, a fourth optical coupler U30, a twenty-fifth resistor R112, a twenty-sixth resistor R113, a twenty-seventh resistor R114, a twenty-eighth resistor R115, a twenty-ninth resistor R116 and a fourth capacitor C118; The non-inverting input pin of the second comparator U29B is electrically connected to the output end of the signal recognition circuit through the twenty-ninth resistor R116, the inverting input pin of the second comparator U29B is electrically connected to the +3.3V isolated power supply end through the twenty-fifth resistor R112, the inverting input pin of the second comparator U29B is also connected to the isolation ground GND_ISO through the twenty-sixth resistor R113, the first end of the fourth capacitor C118 is connected to the common connection end between the inverting input pin of the second comparator U29B and the twenty-sixth resistor R113, and the second end of the fourth capacitor C118 is connected to the isolation ground GND_ISO; The output pin of the second comparator U29B is electrically connected to the positive input electrode of the fourth optocoupler U30, the first end of the twenty-seventh resistor R114 is connected to the common connection end between the output pin of the second comparator U29B and the positive input electrode of the fourth optocoupler U30, and the second end of the twenty-seventh resistor R114 is electrically connected to the +3.3V isolated power supply end; the input negative electrode of the fourth optocoupler U30 is connected to the isolation ground GND_ISO; the power pin of the fourth optocoupler U30 is electrically connected to the +3.3V digital power supply end, the output pin of the fourth optocoupler U30 is electrically connected to the input end of the processor, the first end of the twenty-eighth resistor R115 is connected to the common connection end between the power pin of the fourth optocoupler U30 and the +3.3V digital power supply end, and the second end of the twenty-eighth resistor R115 is connected to the common connection end between the output pin of the fourth optocoupler U30 and the input end of the processor; the ground pin of the fourth optocoupler U30 is connected to the digital ground DGND.

10. The detection device according to any one of claims 1 to 9, characterized in that: The processor is specifically a LFE2-6E-5F256I model FPGA chip.

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