Buck converter
By introducing the in -time control circuit in the antihypertensive converter, the time the pulse setting signal and the logic door extend the inadequate time to solve the lack of the divert time in the load temporary response, realizing a better response efficacy.
Patent Information
- Application Number
- CN202420643168.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2034-03-29
AI Technical Summary
The buck converter with constant on-time architecture has shortcomings in load transient response, especially when changing from light load to heavy load, the switching frequency is limited by the minimum shutdown time, resulting in unsatisfactory response.
By introducing the turnover time control circuit in the antihypertensive converter, the session setting signal and the logical door are used to extend the duration time to ensure the extension of the turnover time under heavy load conditions, and avoid being restricted by the minimum cutting time.
It achieves better load transient response without increasing circuit complexity, can effectively extend the on-time and improve response performance under heavy load.
Smart Images
Figure CN222395561U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a buck converter, and more particularly to a constant on-time (COT) buck converter. Background Art
[0002] With the evolution of semiconductor technology, the current required by central processing units or application-specific integrated circuits is getting larger and larger, and the voltage conversion rate is getting faster and faster. Therefore, the load transient response performance of the buck converter is becoming more and more important.
[0003] Buck converters include voltage mode, current mode and constant on-time mode, among which the constant on-time mode buck converter maintains the duty cycle by adjusting the off-time and has better transient response than the voltage mode / current mode. Under the constant on-time architecture, when the light load becomes heavy load, the buck converter will shorten the duration of turning off the switch circuit, that is, increase the on / off switching frequency of the switch circuit to meet the output current demand. However, the above switching frequency of the constant on-time architecture is still limited by the minimum off-time, making the load transient response less than ideal. In order to extend the above on-time, the background technology provides multiple critical voltages by adding multiple components to improve the load transient response, but this also increases the complexity of the circuit. Utility Model Content
[0004] The utility model provides a buck converter. The buck converter includes a switch circuit, an error amplifier, a first comparator, a conduction time control circuit and a driver. The switch circuit is electrically connected to an input voltage, and is used to generate an output voltage at the output end of the buck converter according to the input voltage. The error amplifier is used to receive a feedback voltage signal, and to generate a compensation voltage signal according to the feedback voltage signal and a first reference voltage signal, wherein the feedback voltage signal is associated with the output voltage. The first comparator is electrically connected to the error amplifier, and is used to generate a clock setting signal according to the compensation voltage signal and the ramp voltage signal. The conduction time control circuit is electrically connected to the first comparator. The conduction time control circuit includes a reset circuit, a logic gate and a flip-flop. The reset circuit is used to generate a first reset signal according to the conduction time control signal. The logic gate is electrically connected to the first comparator and the reset circuit, and is used to generate a second reset signal according to the clock setting signal and the first reset signal. The flip-flop is electrically connected to the logic gate and the first comparator, and is used to generate the conduction time control signal according to the clock setting signal and the second reset signal. The driver is electrically connected to the on-time control circuit and the switch circuit to control the action of the switch circuit according to the on-time control signal. When the clock setting signal has a first logic level, the logic gate maintains the second reset signal at a second logic level different from the first logic level, so that the second reset signal does not reset the on-time control signal output by the flip-flop.
[0005] In some embodiments of the present invention, the first logic level is a high logic level, and the second logic level is a low logic level.
[0006] In some embodiments of the utility model, the buck converter further includes an inductor and a feedback circuit. The inductor is electrically connected between the switch circuit and the output end. The feedback circuit is electrically connected to the output end to generate the feedback voltage signal according to the output voltage of the output end. The switch circuit further includes an upper bridge switch and a lower bridge switch, and the inductor is electrically connected to the upper bridge switch and the lower bridge switch through a phase node.
[0007] In some embodiments of the present invention, the buck converter further includes a sampling unit electrically connected to the first comparator, and the sampling unit is used to capture the inductor current flowing through the inductor to generate a voltage drop according to the inductor current as the ramp voltage signal.
[0008] In some embodiments of the present invention, the buck converter further includes a filter electrically connected to the phase node, for filtering the current signal associated with the phase node to generate the ramp voltage signal.
[0009] In some embodiments of the present invention, the flip-flop has a data input pin, a clock input pin, a reset pin, and an output pin. The data input pin is used to receive an enable signal. The clock input pin is electrically connected to the output end of the first comparator to receive the clock setting signal. The reset pin is electrically connected to the logic gate to receive the second reset signal. The output pin is used to output the conduction time control signal.
[0010] In some embodiments of the present invention, the enable signal has the first logic level. When the second reset signal has the second logic level and the clock setting signal has the first logic level, the on-time control signal generated by the flip-flop has the first logic level. When the second reset signal has the first logic level, the on-time control signal generated by the flip-flop has the second logic level.
[0011] In some embodiments of the utility model, the reset circuit includes a second comparator, a capacitor, and a switch. The first input terminal of the second comparator is used to receive a second reference voltage, and the second input terminal of the second comparator is electrically connected to a current source. The first terminal of the capacitor is electrically connected to the current source, and the second terminal of the capacitor is electrically connected to a ground terminal. The switch is electrically connected to the current source and the ground terminal, and is used to act according to the on-time control signal.
[0012] In some embodiments of the utility model, the reset circuit further includes an inverter electrically connected to the control end of the switch, and the input end of the inverter is used to receive the on-time control signal. When the on-time control signal is the first logic level, the switch is turned off, so that the capacitor is charged by the input voltage, and when the level of the capacitor is charged to be greater than the second reference voltage, the first reset signal output by the second comparator has the first logic level. When the on-time control signal is the second logic level, the switch is turned on, so that the capacitor is discharged to the ground end, and when the level of the capacitor is discharged to be less than the second reference voltage, the first reset signal output by the second comparator has the second logic level.
[0013] The utility model provides a control method for a buck converter. The buck converter includes a switch circuit, an error amplifier, a comparator, an on-time control circuit and a driver. The error amplifier is electrically connected to the switch circuit, the comparator is electrically connected to the error amplifier, the on-time control circuit is electrically connected to the comparator, and the driver is electrically connected to the on-time control circuit and the switch circuit. The on-time control circuit includes a reset circuit, a logic gate and a flip-flop. The logic gate is electrically connected to the first comparator and the reset circuit, and the flip-flop is electrically connected to the logic gate and the first comparator. The control method includes the following steps. An output voltage is generated at an output end of the buck converter according to an input voltage through the switch circuit. A compensation voltage signal is generated according to a feedback voltage signal and a first reference voltage signal through the error amplifier, wherein the feedback voltage signal is associated with the output voltage. A pulse setting signal is generated according to the compensation voltage signal and a ramp voltage signal through the first comparator. A first reset signal is generated according to the on-time control signal through the reset circuit. A second reset signal is generated according to the pulse setting signal and the first reset signal through the logic gate. The on-time control signal is generated by the flip-flop according to the clock setting signal and the second reset signal. The action of the switch circuit is controlled by the driver according to the on-time control signal. When the clock setting signal has a first logic level, the logic gate maintains the second reset signal at a second logic level different from the first logic level, so that the second reset signal does not reset the on-time control signal output by the flip-flop.
[0014] In summary, the buck converter of the present invention utilizes a clock setting signal in conjunction with a logic gate to extend the on-time, and can provide a better transient response without adding an additional comparator, thus not significantly increasing the complexity of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understood, the attached drawings are described as follows:
[0016] Figure 1 FIG. 4 is a schematic diagram of a buck converter according to an embodiment of the present invention.
[0017] Figure 2 FIG. 4 is a schematic diagram of a conduction time control circuit according to an embodiment of the present invention.
[0018] Figure 3 Schematic diagram of signal waveforms of a buck converter under fast transient response from no-load or light load to heavy load according to an embodiment of the present invention.
[0019] Figure 4 FIG. 4 is a schematic diagram of a buck converter according to an embodiment of the present invention.
[0020] Figure 5 FIG. 4 is a schematic diagram of a buck converter according to an embodiment of the present invention.
[0021] Figure 6 FIG. 4 is a schematic diagram of a buck converter according to an embodiment of the present invention.
[0022] Figure 7 Detailed description is a flow chart of a control method of a buck converter according to an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The following examples are described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention, and the description of the structural operation is not intended to limit the execution order. Any device with equal functions produced by the re-combination of components is within the scope of the present invention. In addition, the illustrations are for illustrative purposes only and are not drawn according to the original size. For ease of understanding, the same or similar components in the following description will be described with the same symbols.
[0024] The terms used throughout the specification and claims, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content. In addition, the terms "include", "including", "have", "contain", etc. used in this article are open terms, that is, they mean "including but not limited to". In addition, "and / or" used in this article includes any one or more items in the relevant enumerated items and all combinations thereof.
[0025] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a buck converter 100 according to an embodiment of the present invention. Figure 1 As shown, the buck converter 100 includes a switch circuit 101, a feedback circuit 106, an error amplifier 112, a first comparator 114, a driver 116, an on-time control circuit 120, an output capacitor C o And the resistor R Co In some embodiments, the switch circuit 101 is electrically connected to the input voltage V IN and through the inductor L S In some embodiments, the switch circuit 101 includes an upper bridge switch 102 and a lower bridge switch 103. For example, the upper bridge switch 102 and the lower bridge switch 103 may be NMOS transistors, but the present invention is not limited thereto. In some embodiments, the first end of the upper bridge switch 102 is electrically connected to the input voltage V IN , and the second end of the upper bridge switch 102 is electrically connected to the inductor LS The first end of the lower bridge switch 103 is electrically connected to the inductor L S The first end of the lower bridge switch 103 is grounded, that is, the inductor L S Through the phase node L X The switch is electrically connected to the upper switch 102 and the lower switch 103 .
[0026] Inductance L S is electrically connected between the switch circuit 101 and the output terminal OUT. In some embodiments, the inductor L S To generate an inductor current I according to the operation of the switch circuit 101 L . Output capacitor C o The first end is electrically connected to the inductor L S Between the second end and the output terminal OUT, the resistor R Co Electrically connected to the output capacitor C o The feedback circuit 106 is electrically connected to the output terminal OUT and is used to generate a feedback signal according to the output voltage V OUT Generate feedback voltage signal V FB , and the feedback voltage signal V FB Including output voltage V OUT In some embodiments, the feedback circuit 106 may be implemented by a voltage divider circuit.
[0027] The error amplifier 112 is used to compare the feedback voltage signal V FB And the first reference voltage signal V ref1 , and generates a compensation voltage signal V according to the difference between the two COMP In some embodiments, the inverting input terminal (indicated by “-” in the figure) of the error amplifier 112 is used to receive the feedback voltage signal V FB , and the non-inverting input terminal of the error amplifier 112 (indicated by “+” in the figure) is electrically connected to the reference voltage source to receive the first reference voltage signal V ref1 In some embodiments, the error amplifier 112 generates a voltage signal V FB And the first reference voltage signal V ref1 The difference between the two generates a compensation voltage signal V COMP .
[0028] In some embodiments, the inverting input terminal of the first comparator 114 is used to receive the ramp voltage signal V RAMP , and the non-inverting input terminal is electrically connected to the output terminal of the error amplifier 112 to receive the compensation voltage signal V COMP In some embodiments, the first comparator 114 generates a voltage signal V RAMP And the compensation voltage signal V COMPGenerates a clock setting signal V CLK .
[0029] In some embodiments, the on-time control circuit 120 is electrically connected to the output terminal of the first comparator 114 to receive the clock setting signal V generated by the first comparator 114. CLK In some embodiments, the on-time control circuit 120 sets the clock signal V CLK Generates the on-time control signal V TON , the driver 116 controls the on-time signal V TON In some embodiments, the driver 116 controls the operation of the switch circuit 101 according to the on-time control signal V TON Generate control signal V G1 and V G2 , to control the actions of the upper bridge switch 102 and the lower bridge switch 103 respectively.
[0030] See also Figure 2 . Figure 2 FIG. 1 is a schematic diagram of a conduction time control circuit 120 according to an embodiment of the present invention. Figure 2 As shown, the on-time control circuit 120 includes a reset circuit 122 , a logic gate 126 , and a flip-flop 128 .
[0031] In some embodiments, the reset circuit 122 includes an inverter 123, a second comparator 124, a current source 125, a capacitor C TON In some embodiments, the inverting input terminal of the second comparator 124 is electrically connected to a reference voltage source to receive a second reference voltage signal V ref2 The non-inverting input terminal of the second comparator 124 is electrically connected to the current source 125 and the capacitor C TON and a switch SW, and the current source 125 is electrically connected to the input voltage V IN And generate current I TON In some embodiments, the switch SW is electrically connected between the non-inverting input terminal of the second comparator 124 and the ground terminal, and the control terminal of the switch SW is electrically connected to the output terminal of the inverter 123. In some embodiments, the switch SW can be implemented by an NMOS transistor, but the present invention is not limited thereto.
[0032] The input terminal of the inverter 123 is used to receive the on-time control signal V TON , to output the on-time control signal V TON The inverted control signal V G3 To the control end of the switch SW, the switch SW is controlled according to the on-time control signal V TONThe current path from the non-inverting input terminal of the second comparator 124 to the ground terminal is turned on / off, thereby changing the voltage V C The second comparator 124 generates a voltage V C And the second reference voltage signal V ref2 Generate a first reset signal V RST In the following description, an NMOS transistor is used as the switch SW as an example, a first logic level (e.g., a high logic level) represents a level (e.g., logic 1) that can actually turn on the NMOS transistor, and a second logic level (e.g., a low logic level) represents a level (e.g., logic 0) that can actually turn off the NMOS transistor, and the low logic level should be lower than the high logic level. However, those skilled in the art can replace the NMOS transistor with a PMOS transistor according to the actual circuit design, and design the logic level of the control signal received by the signal terminal of each component accordingly. This is a technique well known to those skilled in the art and will not be described in detail here for simplicity.
[0033] The operation of the reset circuit 122 will be described below. TON When the logic level is high, the inverter 123 generates a control signal V having a low logic level. G3 To the control end of the switch SW, the switch SW cuts off the current path from the non-inverting input end of the second comparator 124 to the ground end, so that the current source 125 outputs a current I TON For capacitor C TON Therefore, the voltage V at the non-inverting input terminal of the second comparator 124 is C Gradually increases. When the voltage V C gradually increases to be greater than the second reference voltage signal V ref2 When the second comparator 124 outputs the first reset signal V RST is a high logic level. On the contrary, when the on-time control signal V TON is a low logic level, the inverter 123 generates a high logic level control signal V G3 to the control terminal of the switch SW, so that the switch SW conducts the current path from the non-inverting input terminal of the second comparator 124 to the ground terminal, so that the capacitor C TON Discharge to ground. When the capacitor C TON The voltage V at the first terminal C Discharged to a voltage lower than the second reference voltage signal V ref2 When the second comparator 124 outputs the first reset signal V RST With a low logic level. According to the above operation, due to the capacitor C TON With current I TON is a fixed value, so after a fixed time, the first reset signal V output by the second comparator 124RST will be converted from a low logic level to a high logic level.
[0034] In some embodiments, the first input terminal of the logic gate 126 has a NOT gate, represented by a hollow circle in the figure, for setting the clock setting signal V CLK The first input terminal of the logic gate 126 is electrically connected to the output terminal of the first comparator 114 to receive the clock setting signal V CLK The second input terminal of the logic gate 126 is electrically connected to the output terminal of the second comparator 124 to receive the first reset signal V RST , according to the clock setting signal V CLK and the first reset signal V RST Generate a second reset signal V RST '. When the output terminal of the first comparator 114 outputs a low logic level clock setting signal V CLK When the first input terminal of the logic gate 126 receives a signal at a high logic level, the output terminal of the logic gate 126 outputs a second reset signal V at a high logic level. RST '. When the output terminal of the first comparator 114 outputs a high logic level clock setting signal V CLK To the first input terminal of the logic gate 126, at this time, no matter the second input terminal receives a signal of a high logic level or a low logic level, the output terminal of the logic gate 126 will output a second reset signal V of a low logic level. RST '.
[0035] In some embodiments, the first comparator 114 is used to compensate the voltage signal V COMP And the ramp voltage signal V RAMP Compare to generate the clock setting signal V CLK To the logic gate 126 and the flip-flop 128. When the clock setting signal V CLK When the logic gate 126 generates a second reset signal V RST 'Must be at a low logic level; when the clock setting signal V CLK When the second reset signal V RST The logic level of ' will be the same as the first reset signal V RST In some embodiments, the logic gate 126 sets the clock signal V according to the output terminal of the first comparator 114. CLK The inverted signal of the second comparator 124 and the first reset signal V RST The union (AND) generates the second reset signal V RST '.
[0036] Furthermore, the flip-flop 128 may be a D-type flip-flop. According to the embodiment of the utility model, the pins to which the flip-flop 128 is applied include a data input pin D, a clock input pin CLK, a reset pin RST, and an output pin Q. The data input pin D is used to receive an enable signal EN, and the enable signal EN can be always set to a high logic level in this embodiment. The clock input pin CLK is electrically connected to the output end of the first comparator 114 to receive a clock setting signal V CLK The reset pin RST is electrically connected to the output end of the logic gate 126 to receive the second reset signal V RST The output pin Q is used to output the on-time control signal V TON The specific operation of the flip-flop 128 is as follows: when the reset pin RST receives the second reset signal V RST ' is logic 0 (eg, the low logic level or the second logic level) and the clock input pin CLK receives the clock setting signal V CLK When the logic 0 changes to the logic 1 (such as the high logic level or the first logic level) (rising edge triggered), the conduction time control signal output by the output pin Q is V TON is logic 1; then, when the reset pin RST receives the second reset signal V RST ' becomes logic 1, the conduction time control signal V TON Pull down to logic 0. According to the embodiment of the utility model, when the compensation voltage signal V COMP Greater than the ramp voltage signal V RAMP , the clock setting signal V generated by the first comparator 114 CLK From low logic level to high logic level. At this time, the clock setting signal V CLK The flip-flop 128 is triggered so that the on-time control signal V output by the flip-flop 128 is TON On the contrary, if the compensation voltage signal V COMP Less than the ramp voltage signal V RAMP , the clock setting signal V generated by the first comparator 114 CLK At a low logic level, at this time, if the first reset signal V output by the second comparator 124 RST is a high logic level, the output terminal of the logic gate 126 outputs a second reset signal V RST 'To reset the on-time control signal V output by the flip-flop 128 TON is a low logic level.
[0037] To better understand the on-time extension architecture of the present invention, please refer to Figure 1 , Figure 2 as well as Figure 3 . Figure 3 FIG. 1 is a waveform diagram showing the transient response of the buck converter 100 of the present invention compared with the prior art. Figure 3 As shown, symbol P1 represents the prior art (not using the utility model Figure 2 The on-time control signal V TON_WO The symbol P2 represents the compensation voltage signal V of the prior art. COMP_WO Compare the ramp voltage signal V RAMP_WO The waveform of the utility model is represented by symbol P3. Figure 2 The on-time control signal V TON The symbol P4 represents the compensation voltage signal V of the utility model. COMP Compare the ramp voltage signal V RAMP The symbol P5 represents the inductor current I of the present invention. L Compared with the inductor current I of the prior art L_WO The symbol P6 represents the output voltage V of the utility model. OUT Compared with the output voltage V of the existing technology OUT_WO waveform.
[0038] Please refer to symbols P3 and P4. During the time period T2 to T3, if the compensation voltage signal V COMP Greater than the ramp voltage signal V RAMP , indicating that the buck converter 100 as a whole still needs energy to cope with the workload, and at this time the clock setting signal V generated by the first comparator 114 CLK The logic level changes from low to high, so that the second reset signal V generated by the logic gate 126 RST ' must be forced to maintain a low logic level, so that the conduction time control signal V TON is not reset, thereby extending the on-time, such as the extended on-time T of symbol P3 ON_ext As shown, the buck converter 100 of the present invention can make the on-time control signal V TON To extend the time of maintaining the high logic level. TON The logic level is still high during the entire time points T2 to T3 until the compensation voltage signal V COMP No greater than the ramp voltage signal V RAMP When the on-time control signal V TON In other words, when the compensation voltage signal V COMP The voltage is greater than the ramp voltage signal V RAMP During the period when the first reset signal V RSTWhen the logic level is changed from low to high, the flip-flop 128 will not be reset and outputs the on-time control signal V at a high logic level. TON In this way, the buck converter 100 of the present invention can be turned off without the minimum off time T under heavy load. OFF_min is limited, thereby extending the conduction time T ON_ext , thereby making the buck converter 100 have a faster response performance.
[0039] In summary, according to the design of the on-time control circuit 120, the on-time control signal V TON Whether it will be reset still depends on the compensation voltage signal V COMP With the ramp voltage signal V RAMP This is because the utility model uses the second reset signal V RST ' to reset the flip-flop 128 instead of using the first reset signal V RST If the compensation voltage signal V COMP The signal is still greater than the ramp voltage signal V RAMP , which means that the current buck converter 100 still needs to provide energy to the output terminal OUT, and the logic gate 126 can be used to limit the flip-flop 128 from being reset to achieve the effect of extending the conduction time. COMP Less than the ramp voltage signal V RAMP , which means that the logic gate 126 will reset the flip-flop 128 only when the loop can normally regulate the voltage. Compared with the prior art, the present invention can achieve the purpose of extending the on-time by setting the reset circuit 122 and the logic gate 126 in the on-time control circuit 120 under the original constant on-time architecture, and whether to extend the on-time is determined by the loop itself, without the need to refer to other factors for setting and adjustment. Therefore, the architecture of the present invention does not significantly increase the additional cost. In addition, it can be seen from symbols P5 and P6 that compared with the prior art, the buck converter 100 of the present invention extends the on-time, so that the buck converter 100 can have more sufficient inductor current during heavy loads, and the output voltage has a smaller undershoot phenomenon, that is, the present invention can provide better load transient response.
[0040] In some embodiments, the on-time control of the buck converter 100 can be implemented by current control. Under the current mode control with constant on-time, the ramp voltage signal V RAMP According to the inductor current I L For details, please refer to Figure 4 , Figure 4 FIG. 4 is a schematic diagram of a buck converter 400 according to an embodiment of the present invention. Figure 4As shown, the buck converter 400 includes an upper bridge switch 102 and a lower bridge switch 103, a feedback circuit 406, an error amplifier 112, a first comparator 114, a driver 116, an on-time control circuit 120, an output capacitor C o , resistor R Co The buck converter 400 includes an upper bridge switch 102 and a lower bridge switch 103, a feedback circuit 106, an error amplifier 112, a first comparator 114, a driver 116, an on-time control circuit 120, and an output capacitor C o , resistor R Co The architecture and actions between Figure 1 The buck converter 100 includes an upper bridge switch 102 and a lower bridge switch 103, a feedback circuit 106, an error amplifier 112, a first comparator 114, a driver 116, an on-time control circuit 120, and an output capacitor C o , resistor R Co The structure and actions between them are not described here.
[0041] like Figure 4 As shown, the feedback circuit 406 is a voltage divider circuit composed of resistors R1 and R2, and can be Figure 1 An example of the feedback circuit 106. The sampling unit 402 is electrically connected to the first comparator 114. The sampling unit 402 captures the current flowing through the inductor L S The inductor current I L , according to the inductor current I L Generates a voltage drop as a ramp voltage signal V RAMP There are various methods to calculate the inductor current I L Generates a ramp voltage signal V RAMP The present invention does not generate the inductive current I L limited in a manner.
[0042] For example, see Figure 5 , Figure 5 is a schematic diagram of a buck converter 500 according to an embodiment of the present invention, wherein the sampling unit 502 may be Figure 4 An example of a sampling unit 402. Figure 5 As shown, the sampling unit 502 of the buck converter 500 includes a shunt resistor 5021 and a detection circuit 5022. The shunt resistor 5021 is electrically connected to the inductor L S Between the feedback circuit 506, the detection circuit 5022 generates a ramp voltage signal V according to the potential difference between the two ends of the shunt resistor 5021. RAMPSpecifically, the current value flowing through the shunt resistor 5021 is detected by the detection circuit 5022, and the potential difference (voltage drop) across the shunt resistor 5021 can be obtained according to Ohm's law, so as to generate a ramp voltage signal V according to the potential difference (voltage drop). RAMP This is a technique well known to those skilled in the art and will not be described in detail here for the sake of simplicity.
[0043] See also Figure 6 , Figure 6 FIG. 6 is a schematic diagram of a buck converter 600 according to an embodiment of the present invention. Figure 6 As shown, the buck converter 600 includes an upper bridge switch 102 and a lower bridge switch 103, a feedback circuit 106, an error amplifier 112, a first comparator 114, a driver 116, an on-time control circuit 120, an output capacitor C o , resistor R Co and a filter 602. In some embodiments, the filter 602 is electrically connected to the phase node L X , to receive the square wave signal from the switch circuit 101 (associated with the phase node L X The current signal is filtered by RC to generate a sawtooth wave signal or a triangle wave signal as a ramp voltage signal V RAMP This is a technique well known to those skilled in the art and will not be described in detail here for simplicity. The buck converter 600 includes the upper bridge switch 102 and the lower bridge switch 103, the feedback circuit 106, the error amplifier 112, the first comparator 114, the driver 116, the on-time control circuit 120, and the output capacitor C o , resistor R Co The architecture and actions between them correspond to Figure 1 The buck converter 100 includes an upper bridge switch 102 and a lower bridge switch 103, a feedback circuit 106, an error amplifier 112, a first comparator 114, a driver 116, an on-time control circuit 120, and an output capacitor C o , resistor R Co The structure and actions between them are not described here.
[0044] Figure 7 FIG. 7 is a flow chart of a control method 700 of a buck converter according to an embodiment of the present invention. Please note that if substantially the same result can be obtained, these steps do not necessarily have to be followed. Figure 7 Execute in the order shown. Figure 7 The control method 700 shown may be Figure 1 The buck converter 100 shown adopts and can be simply summarized into the following steps.
[0045] In step 702, an output voltage is generated according to an input voltage.
[0046] In step 704 , a compensation voltage signal is generated according to the feedback voltage signal and the first reference voltage signal, wherein the feedback voltage signal is related to the output voltage.
[0047] In step 706 , a clock setting signal is generated according to the compensation voltage signal and the ramp voltage signal.
[0048] In step 708 , a first reset signal is generated according to the on-time control signal.
[0049] In step 710 , a second reset signal is generated according to the clock setting signal and the first reset signal.
[0050] In step 712, a conduction time control signal is generated according to the clock setting signal and the second reset signal.
[0051] In step 714, the operation of the switch circuit is controlled according to the on-time control signal, wherein when the clock setting signal has a high logic level, the second reset signal is maintained at a low logic level so that the second reset signal does not reset the on-time control signal.
[0052] After reading the above paragraphs, the skilled person should be able to easily understand Figure 7 The details of each step in the above process will be omitted for brevity.
[0053] In summary, the buck converter 100 of the present invention utilizes the clock setting signal V CLK By extending the conduction time with the logic gate 126 , a better transient response can be provided without adding an additional comparator, thus not significantly increasing the complexity of the circuit.
[0054] Although the present invention has been disclosed in the form of implementation modes as above, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.
[0055]
Explanation of symbols
[0056] In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the attached symbols are explained as follows:
[0057] 100,400,500,600: Buck converter
[0058] 101: Switching Circuit
[0059] 102,103: Switch
[0060] 104: Load
[0061] 106,406,506: Feedback circuit
[0062] 112: Error amplifier
[0063] 114: First comparator
[0064] 116:Drive
[0065] 120: On-time control circuit
[0066] 122: Reset circuit
[0067] 123: Inverter
[0068] 124: Second comparator
[0069] 125: Current Source
[0070] 126: Logic Gates
[0071] 128: Flip-flop
[0072] 402,502: Sampling unit
[0073] 5021: Shunt resistor
[0074] 5022: Detection circuit
[0075] 602: Filter
[0076] 700: Control Method
[0077] C o :Output Capacitor
[0078] CLK: Clock input pin
[0079] C TON :capacitance
[0080] D: Data input pin
[0081] EN: Enable signal
[0082] I L ,I L_WO :Inductor current
[0083] L S :inductance
[0084] L X :Phase Node
[0085] OUT: Output terminal
[0086] P1~P6: Symbol
[0087] Q: Output pin
[0088] R1, R2: resistors
[0089] R Co :resistance
[0090] RST: Reset pin
[0091] SW: Switch
[0092] T1~T4: Time point
[0093] T OFF_min :Minimum off time
[0094] T ON_ext : Extended on-time
[0095] V C :Voltage
[0096] V CLK :Clock setting signal
[0097] V COMP ,V COMP_WO : Compensation voltage signal
[0098] V FB : Feedback voltage signal
[0099] V G1 ,V G2 ,V G3 :Control signal
[0100] V IN :Input voltage
[0101] V OUT ,V OUT_WO :Output voltage
[0102] V RAMP ,V RAMP_WO :Ramp voltage signal
[0103] V ref1 :First reference voltage signal
[0104] V ref2 : Second reference voltage signal
[0105] V RST :First reset signal
[0106] V RST ': Second reset signal
[0107] V TON ,V TON_WO : On-time control signal.
Claims
1. A buck converter, characterized in that: include: A switch circuit is electrically connected to an input voltage and is used to generate an output voltage at an output end of the buck converter according to the input voltage; an error amplifier, configured to receive a feedback voltage signal and generate a compensation voltage signal according to the feedback voltage signal and a first reference voltage signal, wherein the feedback voltage signal is related to the output voltage; A first comparator, electrically connected to the error amplifier, for generating a clock setting signal according to the compensation voltage signal and the ramp voltage signal; A conduction time control circuit is electrically connected to the first comparator, and the conduction time control circuit includes: A reset circuit, used for generating a first reset signal according to the on-time control signal; a logic gate electrically connected to the first comparator and the reset circuit, for generating a second reset signal according to the clock setting signal and the first reset signal; and A flip-flop electrically connected to the logic gate and the first comparator, for generating the on-time control signal according to the clock setting signal and the second reset signal; and A driver, electrically connected to the on-time control circuit and the switch circuit, for controlling the operation of the switch circuit according to the on-time control signal; When the clock setting signal has a first logic level, the logic gate maintains the second reset signal at a second logic level different from the first logic level, so that the second reset signal does not reset the conduction time control signal output by the flip-flop.
2. The buck converter according to claim 1, characterized in that The first logic level is a high logic level, and the second logic level is a low logic level.
3. The buck converter according to claim 1, wherein: Also includes: an inductor electrically connected between the switch circuit and the output end; as well as A feedback circuit is electrically connected to the output end and is used to generate the feedback voltage signal according to the output voltage of the output end. The switch circuit further includes an upper bridge switch and a lower bridge switch, and the inductor is electrically connected to the upper bridge switch and the lower bridge switch through a phase node.
4. The buck converter according to claim 3, characterized in that: Also includes: The sampling unit is electrically connected to the first comparator, and is used for capturing the inductor current flowing through the inductor to generate a voltage drop according to the inductor current as the ramp voltage signal.
5. The buck converter according to claim 3, characterized in that: Also includes: The filter is electrically connected to the phase node and is used for filtering the current signal associated with the phase node to generate the ramp voltage signal.
6. The buck converter according to claim 1, wherein: The flip-flop has a data input pin, a clock input pin, a reset pin, and an output pin, wherein: The data input pin is used to receive an enable signal; The clock input pin is electrically connected to the output end of the first comparator to receive the clock setting signal; The reset pin is electrically connected to the logic gate to receive the second reset signal; and The output pin is used to output the on-time control signal.
7. The buck converter according to claim 6, characterized in that The enable signal has the first logic level, wherein: When the second reset signal has the second logic level and the clock setting signal has the first logic level, the on-time control signal generated by the flip-flop has the first logic level; and When the second reset signal has the first logic level, the on-time control signal generated by the flip-flop has the second logic level.
8. The buck converter according to claim 1, wherein: The reset circuit includes: A second comparator, a first input terminal of which is used to receive a second reference voltage, and a second input terminal of which is electrically connected to a current source; a capacitor, a first end of which is electrically connected to the current source, and a second end of which is electrically connected to the ground; and The switch is electrically connected to the current source and the ground terminal, and is used for operating according to the on-time control signal.
9. The buck converter according to claim 8, characterized in that The reset circuit also includes an inverter electrically connected to the control end of the switch, and the input end of the inverter is used to receive the conduction time control signal, wherein: When the on-time control signal is at the first logic level, the switch is turned off, so that the capacitor is charged through the current source, and when the level of the capacitor is charged to be greater than the second reference voltage, the first reset signal output by the second comparator has the first logic level; and When the on-time control signal is at the second logic level, the switch is turned on to discharge the capacitor to the ground. When the capacitor level is lower than the second reference voltage, the first reset signal output by the second comparator has the second logic level.