Airborne equipment network card

Abstract

The utility model relates to the technical field of avionics airborne equipment communication, and discloses an airborne equipment network card, which comprises a bus interface module, a photoelectric converter and a core board, the bus interface module is in communication connection with the core board, and the photoelectric converter is in communication connection with the core board through a media independent interface; the bus interface module is used for being in communication connection with a terminal equipment processor; the photoelectric converter is used for providing a photoelectric interface and is in communication connection with airborne equipment through the photoelectric interface; and the core board is used for communicating with the terminal equipment based on a first communication protocol corresponding to the bus interface and communicating with the airborne equipment based on a second communication protocol corresponding to the airborne equipment. In the process of communication between the terminal equipment and the airborne equipment, data conversion can be performed on the received and transmitted data according to the ARINC664 protocol through the airborne equipment network card, so that the communication efficiency between the terminal equipment and the airborne equipment is improved, and the function of the airborne equipment is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of avionics onboard equipment communication, in particular to an onboard equipment network card. Background Art

[0002] In avionics onboard equipment, ARINC664 protocol is widely used. At the same time, ARINC664 bus has many interfaces and complex communication protocols in applications. When communicating between terminal equipment and airborne equipment, it is necessary to convert the received and sent data according to the ARINC664 protocol. However, due to the large number of functions of the airborne equipment system and the complex data parameter types, the success rate of data conversion for the received and sent data cannot be guaranteed, which affects the communication efficiency between the terminal equipment and the airborne equipment and the functional realization of the airborne equipment. Summary of the invention

[0003] In view of this, the utility model provides an airborne device network card to solve the problem that the airborne device cannot guarantee the success rate of data conversion for received and sent data, thereby affecting the communication efficiency between the terminal device and the airborne device and the function realization of the airborne device.

[0004] In a first aspect, the utility model provides an airborne device network card, comprising: a bus interface module, an optoelectronic converter and a core board, wherein the bus interface module is communicatively connected to the core board, and the optoelectronic converter is communicatively connected to the core board via a media independent interface;

[0005] A bus interface module, used for communication connection with a terminal device processor;

[0006] The photoelectric converter is used to provide a photoelectric interface and communicate with the airborne equipment through the photoelectric interface;

[0007] The core board is used to communicate with the terminal device based on a first communication protocol corresponding to the bus interface, and to communicate with the airborne device based on a second communication protocol corresponding to the airborne device.

[0008] In an optional embodiment, the core board includes: an FPGA chip, wherein the FPGA chip includes preset pins and is communicatively connected to the bus interface module through the preset pins, and the preset pins include: eight pairs of data differential channels and one pair of clock differential channels.

[0009] In an optional embodiment, the photoelectric converter includes: a plurality of optical fiber interfaces;

[0010] Multiple optical fiber interfaces are used for data transmission with airborne equipment, and when any optical fiber interface is in an abnormal state, data transmission with the airborne equipment is carried out through the remaining optical fiber interfaces.

[0011] In an optional implementation, the airborne device network card further includes: a flash memory, wherein the flash memory is communicatively connected to the core board;

[0012] The flash memory is used to store the loading files of the core board, wherein the loading files include the program files of the core board.

[0013] In an optional implementation, the airborne device network card further includes: a test interface, wherein the test interface is communicatively connected to the core board;

[0014] Test interface, used to write or debug programs into the core board.

[0015] In an optional implementation, the airborne device network card further includes: a random access memory, wherein the random access memory is communicatively connected to the core board;

[0016] The random access memory is used to store the sending and receiving data of the core board.

[0017] In an optional implementation, the airborne device network card further includes: a power supply device, wherein the power supply device includes: a first power supply chip and a second power supply chip.

[0018] A first power chip, used for converting direct current into direct current of target voltage, and inputting the direct current into a first sub-functional module in the core board;

[0019] The second power chip is used to supply power to each second sub-function module in the core board according to the rated voltage of the second sub-function module, wherein the second sub-function module is the remaining sub-function module in the core board except the first sub-function module.

[0020] In a second aspect, the utility model provides an airborne device communication system, applied to the airborne device network card described in any one of the first aspects; the airborne device communication system comprises: a self-test unit, a clock unit, a link configuration unit, a data management unit and a redundancy management unit;

[0021] A self-checking unit, used to detect the operating status of each functional unit in the airborne device communication system and report the operating status to the terminal device;

[0022] A link configuration unit, configured to configure the bandwidth of each virtual link based on the bus bandwidth, wherein the virtual links are used to send and receive data of corresponding types;

[0023] A data management unit, used to encode the transmitted data to obtain a coded data frame, or to pre-process the received data;

[0024] The redundancy management unit is used to send the encoded data frame to the address controller of the corresponding port through a virtual link based on the port identifier of the sending data, and verify the pre-processed received data according to the target communication protocol.

[0025] In an optional implementation, the self-checking unit further includes: an indicating subunit;

[0026] The indicating subunit is used to indicate the operating status of each functional unit, wherein the operating status includes at least one of the following: power supply voltage status, program file loading status, bus interface and clock unit operating status, and optoelectronic interface connection status.

[0027] In an optional implementation, the link configuration unit is further used to: search for configuration information of a virtual link corresponding to the sent data, obtain a preset transmission unit, and fragment the sent data based on the preset transmission unit to obtain a sent data frame.

[0028] In an optional implementation, the airborne device communication system further includes: a time synchronization unit;

[0029] The time synchronization unit is used to insert a time synchronization frame into a transmitted data frame and extract a time synchronization frame of received data.

[0030] In an optional implementation, the data management unit includes: a received data analysis unit, a data IP unit, a flow control unit, and a cache control unit;

[0031] A receiving data analysis unit, used to perform IP information analysis on the received data to obtain IP fragmentation data, and filter data with incorrect fragmentation information in the IP fragmentation data, wherein the IP fragmentation data is a data frame whose data length is not less than a preset transmission unit of the virtual link;

[0032] The data IP unit is used to delete invalid data in each data frame of the received data;

[0033] A flow control unit, used for encoding a transmission data frame based on a link identifier of a virtual link corresponding to the transmission data frame;

[0034] The cache control unit is used to determine interrupted data frames in received data to determine lost data frames according to the interrupted data frames, wherein the interrupted data frames are adjacent data frames whose codes are not adjacent. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a structural diagram of an onboard device network card according to an embodiment of the utility model;

[0037] Figure 2 This is a schematic diagram of the use scenario of the airborne device network card;

[0038] Figure 3 is an architectural diagram of another airborne device network card according to an embodiment of the utility model;

[0039] Figure 4 This is a schematic diagram of allocating relevant memory resources to the FPGA chip;

[0040] Figure 5 It is a schematic diagram of some bus interface pins in the FPGA chip;

[0041] Figure 6 is an architectural diagram of another airborne device network card according to an embodiment of the utility model;

[0042] Figure 7 It is a schematic diagram of the Flash chip;

[0043] Figure 8 This is a schematic diagram of a DDR chip. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0045] In conjunction with the application scenarios on which the execution of the airborne device network card depends, the application scenarios are described here.

[0046] In avionics onboard equipment, ARINC664 protocol is widely used. At the same time, ARINC664 bus has many interfaces and complex communication protocol in application. When communicating between terminal equipment and airborne equipment, it is necessary to convert the received and sent data according to ARINC664 protocol. However, due to the large number of functions of airborne equipment system and the complex data parameter types, the communication efficiency between terminal equipment and airborne equipment and the function realization of airborne equipment are affected.

[0047] Specifically, in the process of communication between terminal equipment and airborne equipment, there are high requirements for ARINC664 protocol consistency check of sent and received data, ICD (Interface Control Document) parsing and processing, simulation of related communication between airborne equipment, and data monitoring and recording. Therefore, in the scheme of communication between terminal equipment and airborne equipment, there is an urgent need for an airborne equipment that can be applied to a large-scale integrated verification environment to assist in solving data processing problems.

[0048] The embodiment of the utility model provides an airborne device network card, including: a bus interface module, an optoelectronic converter and a core board, wherein the bus interface is communicatively connected to the core board, and the optoelectronic converter is connected to the core board through the media independent interface of the core board; the bus interface is used to communicate with the terminal device processor; the optoelectronic converter is used to provide an optoelectronic interface, and is communicatively connected to the airborne device through the optoelectronic interface; the core board is used to communicate with the terminal device based on a first communication protocol corresponding to the bus interface, and communicate with the airborne device based on a second communication protocol corresponding to the airborne device. In the process of communication between the terminal device and the airborne device, the airborne device network card can be used to perform data conversion on the received and sent data according to the ARINC664 protocol, thereby improving the communication efficiency between the terminal device and the airborne device, and realizing the functions of the airborne device.

[0049] In this embodiment, an onboard device network card is provided. Figure 1 is a diagram of the architecture of an onboard device network card according to an embodiment of the utility model, such as Figure 1 As shown, the airborne device network card includes: a bus interface module 10, an optoelectronic converter 20, and a core board 30, wherein the bus interface module 10 is communicatively connected to the core board 30, and the optoelectronic converter 20 is connected to the core board 30 via a media independent interface.

[0050] The bus interface module 10 is used for communication connection with the terminal device processor.

[0051] In the disclosed embodiment, the above-mentioned airborne device network card is an ARINC664 terminal network card, and the ARINC664 terminal network card can be applied to airborne devices using the ARINC664 bus protocol. The airborne device network card includes the above-mentioned bus interface module, and the bus interface can be a PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface. It should be understood that the data transmission rate of the bus interface can reach 1000Mbps.

[0052] The photoelectric converter 20 is used to provide a photoelectric interface and communicate with the airborne device through the photoelectric interface.

[0053] In the disclosed embodiment, considering that the data transmission rate of the above-mentioned bus interface module can reach 1000Mbps, optical fiber communication can be adopted between the airborne device and the airborne device network card to adapt to the communication efficiency of the bus interface module. Here, the optoelectronic converter can be used to convert between optical signals and electrical signals.

[0054] From the above, it can be seen that the above-mentioned optoelectronic converter can be connected to the core board through a media independent interface. Here, the media independent interface can be SGMII (Serial Gigabit Media Independent Interface) or other gigabit serial interfaces. The specific interface type is subject to what can be implemented, and the present disclosure does not limit this.

[0055] The core board 30 is used to communicate with the terminal device based on the first communication protocol corresponding to the bus interface, and to communicate with the airborne device based on the second communication protocol corresponding to the airborne device.

[0056] In the embodiments of the present disclosure, Figure 2 The figure shows a schematic diagram of the use scenario of the above-mentioned airborne device network card, wherein the terminal device may be a device for communicating with the airborne device, for example, a laptop computer. Usually, the first communication protocol corresponding to the terminal device bus may be a PCIE transmission protocol. In addition, the airborne device bus is an ARINC664 bus, and ARINC664 is used to communicate with the terminal device. Therefore, the above-mentioned second communication protocol may be an ARINC664 protocol (hereinafter referred to as AFDX protocol).

[0057] Specifically, when the airborne device communicates with the terminal device through the airborne device network card, high-speed data transmission can be performed with the CPU of the terminal device through PCIE4x, thereby achieving a data transmission rate of 1000Mbps. In addition, the airborne device network card can convert the acquired data format through the core board to convert the data into the data format of the AFDX protocol, and send the data to the airborne device through the AFDX protocol.

[0058] Similarly, after the airborne device network card obtains the data sent by the airborne device through the above-mentioned AFDX protocol, it can convert the data format of the data through the core board to convert the data into the data format of the PCIE protocol, and send the data to the terminal device through the PCIE protocol.

[0059] It can be seen from the above description that in the disclosed embodiment, the bus interface is used to communicate with the terminal device processor; the photoelectric converter is used to provide a photoelectric interface and communicate with the airborne device through the photoelectric interface; the core board is used to communicate with the terminal device based on the first communication protocol corresponding to the bus interface, and communicate with the airborne device based on the second communication protocol corresponding to the airborne device. In the process of communication between the terminal device and the airborne device, the airborne device network card can be used to convert the received and sent data according to the ARINC664 protocol, thereby improving the communication efficiency between the terminal device and the airborne device and realizing the functions of the airborne device.

[0060] In this embodiment, another onboard device network card is provided. Figure 3 is an architecture diagram of another airborne device network card according to an embodiment of the utility model, such as Figure 3 As shown, the airborne device network card includes:

[0061] The bus interface module 10 is used to communicate with the terminal device processor. Figure 1 The bus interface module 10 of the illustrated embodiment will not be described in detail herein.

[0062] The photoelectric converter 20 is used to provide a photoelectric interface and communicate with the airborne equipment through the photoelectric interface. Figure 1 The photoelectric converter 20 of the illustrated embodiment will not be described in detail herein.

[0063] The core board 30 is used to communicate with the terminal device based on a first communication protocol corresponding to the bus interface, and to communicate with the airborne device based on a second communication protocol corresponding to the airborne device.

[0064] Specifically, the core board 30 includes: an FPGA chip 31, wherein the FPGA chip includes preset pins and is communicatively connected with the bus interface module through the preset pins, and the preset pins include: eight pairs of data differential channels and one pair of clock differential channels.

[0065] In the embodiment of the present disclosure, the FPGA chip can use the JFM7K325T-N model chip of Fudan Micro as the core processor of the module. It should be understood that the arrangement of I / O in the FPGA chip is realized by BANK division. Therefore, it can be realized by Figure 4 The method shown allocates related memory (hereinafter referred to as bank) resources to the FPGA chip, wherein the bank resources can be allocated by column (i.e., Column in the figure), and the specific bank resource allocation method is not described in detail in this disclosure.

[0066] In addition, the FPGA chip includes a bus interface pin, which can be used to connect to the bus interface in the connector, thereby establishing a communication connection between the connector and the terminal device.

[0067] Specifically, Figure 5 The figure shows a schematic diagram of some bus interface pins in the FPGA chip, wherein the data differential channel includes: pin P1-pin P2, pin N3-pin N4, pin M1-pin M2, pin L3-pin L4, pin T5-pin T6, pin R3-pin R4, pin P5-pin P6 and pin M5-pin M6. The clock differential channel includes: pin N7-pin N8.

[0068] In the embodiments of the present disclosure, network connection can be achieved through the bus interface, thereby achieving high-speed and reliable data communication, and efficiently realizing all the functions of the ARINC664 protocol stack and the end system specified by the ARINC664 protocol. At the same time, the bus interface pins can include a pair of data differential channels and a pair of clock differential channels, thereby improving the anti-interference ability during data transmission and increasing the data transmission rate.

[0069] In this embodiment, another onboard device network card is provided. Figure 6 is an architecture diagram of another airborne device network card according to an embodiment of the utility model, such as Figure 6 As shown, the airborne device network card includes:

[0070] The bus interface module 10 is used to communicate with the terminal device processor. Figure 1 The bus interface module 10 of the illustrated embodiment will not be described in detail herein.

[0071] The photoelectric converter 20 is used to provide a photoelectric interface and communicate with the airborne equipment through the photoelectric interface. Figure 1 The photoelectric converter 20 of the illustrated embodiment will not be described in detail herein.

[0072] Specifically, the above-mentioned photoelectric converter 20 includes: a plurality of optical fiber interfaces 21 .

[0073] The above-mentioned multiple optical fiber interfaces are used for data transmission with the airborne equipment, and when any optical fiber interface is in an abnormal state, data transmission is performed with the airborne equipment through the remaining optical fiber interfaces.

[0074] In the disclosed embodiment, the above-mentioned photoelectric converter can adopt a dual redundant ARINC664 optical fiber interface, and the dual redundancy is two optical fiber interfaces, for example, optical fiber interface A and optical fiber interface B. It should be understood that when data is sent and received through the photoelectric converter, one of the optical fiber interfaces is usually used as a backup data port. For example, when the optical fiber interface A is in an abnormal state where data cannot be sent and received, data can be sent and received through the optical fiber interface B as a backup data port to improve the reliability of data transmission.

[0075] The core board 30 is used to communicate with the terminal device based on the first communication protocol corresponding to the bus interface, and to communicate with the airborne device based on the second communication protocol corresponding to the airborne device. Figure 1 The photoelectric converter 20 of the illustrated embodiment will not be described in detail herein.

[0076] In the disclosed embodiment, the above-mentioned optoelectronic converter can adopt a dual redundant ARINC664 optical fiber interface. When data is sent and received through the optoelectronic converter, one of the optical fiber interfaces is usually used as a backup data port, thereby improving the reliability of data transmission.

[0077] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes: a flash memory 40, wherein the flash memory 40 is communicatively connected with the core board;

[0078] The flash memory 40 is used to store the loading files of the core board, wherein the loading files include the program files of the core board.

[0079] In the embodiment of the present disclosure, the above-mentioned program files may include an operating system, an application program, a system configuration file, etc. Here, the chip type of the flash memory (hereinafter referred to as Flash) may be a SM25QH256M chip of SMIC, which has a capacity of 256Mb. Figure 7 Shown is a schematic diagram of a Flash chip.

[0080] Specifically, in the above-mentioned Flash chip, pin 2 and pin 7 are power pins for powering the chip, the GND pin is a ground pin, and the remaining pins are used to communicate with the above-mentioned core board core. It should be understood that the core board can be communicated with in response to a modification request of the terminal device, so as to modify the program file in the Flash, for example, to update the system configuration file.

[0081] In the disclosed embodiment, considering that Flash has high reliability and can provide high-speed reading and writing speeds, the above-mentioned program files can be stored in the Flash, and the cost is relatively low, thereby reducing the hardware cost while ensuring the system operation speed of the airborne device network card.

[0082] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes: a test interface 50, wherein the test interface 50 is communicatively connected with the core board;

[0083] The test interface is used to write or debug programs into the core board.

[0084] In the disclosed embodiment, the test interface may be used to test the core board and program the loading file in the Flash chip through the core board, for example, writing a program in the Flash chip or debugging the program in the loading file.

[0085] Here, the test interface may be a JTAG (Joint Test Action Group) interface. It should be understood that the test interface may also be other types of interfaces, which are subject to implementation, and the present disclosure does not limit this.

[0086] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes: a random access memory 60, wherein the random access memory 60 is communicatively connected with the core board;

[0087] The random access memory 60 is used to store the receiving and sending data of the core board.

[0088] In the embodiment of the present disclosure, the above-mentioned transceived data may be the communication data generated when the above-mentioned avionics equipment communicates with the terminal equipment, and the transceived data may be stored in a random access memory (Double Data Rate, i.e., double data rate storage technology, hereinafter referred to as DDR), so as to facilitate subsequent data analysis and other operations on the transceived data. For example, when testing and verifying the airborne equipment, it is necessary to analyze the transceived data to determine whether the airborne equipment has a fault, and the specific test and verification process is not described in detail in the present disclosure.

[0089] Specifically, the core board can support various types of DDR chips, such as DDR3, DDR3L, DDR2, RLDRAMIII, etc. The specific type of DDR chip used is subject to implementation and is not specifically limited in the present disclosure.

[0090] Here we take the SM47H64M16M DDR chip of SMIC as an example. Figure 8 As shown is a schematic diagram of the DDR chip, wherein the DDR chip can be connected to the core board through the fifth pin, and the fifth pin includes: pins DQ0-DQ15, pins A0-A12, pins BA0-BA1, pins LDM, pin UDM, pin LDQS, pin LDQS#, pin UDQS, pin UDQS#, pin CK, pin CK#, pin CKE, pin RAS#, pin CAS#, pin WE#, pin CS#, pins NC1-NC5 and pin COT.

[0091] In the disclosed embodiment, the above-mentioned airborne device network card may include DDR, so as to store the received and sent data through the DDR, thereby facilitating subsequent operations such as data analysis on the received and sent data.

[0092] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes: a power supply device 70 , wherein the power supply device includes: a first power supply chip 71 and a second power supply chip 72 .

[0093] The first power chip 71 is used to convert the direct current into direct current of a target voltage and input it into the first sub-functional module in the core board;

[0094] The second power chip 72 is used to supply power to each second sub-function module in the core board according to the rated voltage of the second sub-function module, wherein the second sub-function module is the remaining sub-function module in the core board except the first sub-function module.

[0095] In the embodiment of the present disclosure, the target power supply may be 5V, the first power chip may be a SM4644VCONT1.0V MGTVCC1.0V chip, and the second power chip may be a SM4644MGTVCC1.2V VCCO3.3VVCCAUX_1V8 VCC_DDR2_1V8 chip.

[0096] In the embodiment of the present disclosure, different sub-functional modules in the FPGA chip can be powered by the first power chip and the second power chip respectively, thereby improving the stability of power supply to the FPGA chip.

[0097] In summary, in the disclosed embodiments, a bus interface can be used to communicate with a terminal device processor; an optoelectronic interface is provided through an optoelectronic converter, and an optoelectronic interface is used to communicate with an airborne device; a core board communicates with a terminal device based on a first communication protocol corresponding to the bus interface, and communicates with the airborne device based on a second communication protocol corresponding to the airborne device. In the process of communication between the terminal device and the airborne device, the airborne device network card can be used to convert the received and sent data according to the ARINC664 protocol, so that those skilled in the art can understand that in the above method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0098] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0099] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0100] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0101] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0102] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An airborne device network card, characterized in that: include: A bus interface module, an optoelectronic converter and a core board, wherein the bus interface module is communicatively connected to the core board, and the optoelectronic converter is communicatively connected to the core board via a media independent interface; The bus interface module is used to communicate with the terminal device processor; The photoelectric converter is used to provide a photoelectric interface and communicate with the airborne device through the photoelectric interface; The core board is used to communicate with the terminal device based on a first communication protocol corresponding to the bus interface, and to communicate with the airborne device based on a second communication protocol corresponding to the airborne device.

2. The airborne device network card according to claim 1, characterized in that: The core board includes: an FPGA chip, wherein the FPGA chip includes preset pins and is communicatively connected with the bus interface module through the preset pins, and the preset pins include: eight pairs of data differential channels and one pair of clock differential channels.

3. The airborne device network card according to claim 1, characterized in that: The photoelectric converter includes: a plurality of optical fiber interfaces; The multiple optical fiber interfaces are used to transmit data with the airborne device, and when any optical fiber interface is in an abnormal state, data is transmitted with the airborne device through the remaining optical fiber interfaces.

4. The airborne device network card according to claim 1, characterized in that: The airborne device network card further includes: a flash memory, wherein the flash memory is communicatively connected with the core board; The flash memory is used to store the loading file of the core board, wherein the loading file includes the program file of the core board.

5. The airborne device network card according to claim 4, characterized in that: The airborne device network card further includes: a test interface, wherein the test interface is communicatively connected to the core board; The test interface is used to write or debug programs into the core board.

6. The airborne device network card according to claim 1, characterized in that: The airborne device network card further includes: a random access memory, wherein the random access memory is communicatively connected with the core board; The random access memory is used to store the sending and receiving data of the core board.

7. The airborne device network card according to claim 1, characterized in that: The airborne device network card further includes: a power supply device, wherein the power supply device includes: a first power supply chip and a second power supply chip; The first power chip is used to convert direct current into direct current of target voltage and input it into the first sub-functional module in the core board; The second power chip is used to supply power to each of the second sub-function modules in the core board according to the rated voltage of the second sub-function modules, wherein the second sub-function modules are the remaining sub-function modules in the core board except the first sub-function modules.

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