Multi-chip stacking packaging structure

Abstract

The utility model discloses a multi-chip stacked packaging structure, and the structure comprises a substrate; the stacking structure is located on the upper surface of the substrate, the stacking structure comprises multiple layers of semiconductor chips which are sequentially stacked in the direction perpendicular to the upper surface of the substrate, one end of the stacking structure is provided with a step area, the step area comprises a plurality of steps which are lifted step by step, and each step has a corresponding vertex angle; the heat dissipation cover is attached to the surface of the step of the step area and the surface of the semiconductor chip on the top layer, and a hollow hole is formed in the heat dissipation cover at the vertex angle of the step. Due to the existence of the step region and the heat dissipation cover, heat generated by all layers of semiconductor chips in the stacked structure can be released through the heat dissipation cover, so that the heat dissipation performance is improved. And the hollow holes are formed in the heat dissipation cover at the vertex angle of the step and can effectively release the stress in the heat dissipation cover, so that the binding force between the heat dissipation cover and the surface of the step and the surface of the semiconductor chip on the top layer is improved, and the warping of the heat dissipation cover and the layering defect of the packaging structure are further prevented.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a multi-chip stacking packaging structure. Background Art

[0002] With the advancement of technology and the improvement of chip process, electronic products are gradually moving towards high integration and miniaturization. The improvement of chip process means that more transistors can be integrated in the same area, which improves chip performance and increases power consumption. Multi-chip stacking technology is to stack chips with different functions in layers in the Z direction of the package substrate, and the chips and substrate are connected by wire bonding or flip chip technology. The stacking of chips with different functions means the concentration of power consumption and heat. How to effectively guide the concentrated heat out becomes a design difficulty for stacked chips.

[0003] In the prior art, a heat sink is usually mounted on the surface of the topmost chip in a chip stack structure to dissipate heat from the chip stack structure. However, this method has poor heat dissipation performance for the chips in the middle of the chip stack. Utility Model Content

[0004] The technical problem to be solved by the present application is how to improve the heat dissipation performance of the chip in the middle part of the chip stacking structure.

[0005] In order to solve the above problems, some embodiments of the present application provide a multi-chip stacking packaging structure, including:

[0006] substrate;

[0007] A stacking structure located on the upper surface of the substrate, the stacking structure comprising multiple layers of semiconductor chips stacked in sequence in a direction perpendicular to the upper surface of the substrate, one end of the stacking structure having a step area, the step area comprising a plurality of gradually rising steps, each of the steps having a corresponding vertex angle;

[0008] A heat dissipation cover is mounted on the step surface of the step area and the surface of the semiconductor chip on the top layer, and a hollow hole is provided in the heat dissipation cover at the top corner of the step.

[0009] In some embodiments, the number of hollow holes in the heat dissipation cover corresponding to the top corners of each step is one or more.

[0010] In some embodiments, the semiconductor chip includes a first surface and a second surface relative to each other, and a side surface located between the first surface and the second surface, the second surface has a welding bump, the first surface has a connecting pad, and the stacking structure includes a plurality of layers of semiconductor chips stacked in sequence in a direction perpendicular to the upper surface of the substrate, so that the welding bumps on the second surface of the upper semiconductor chip are connected to the connecting pads on the first surface of the adjacent lower semiconductor chip, and the welding bumps on the second surface of the bottom semiconductor chip are electrically connected to the substrate.

[0011] In some embodiments, the heat dissipation cover is attached to the surface of the semiconductor chip on the top layer, including: the heat dissipation cover is attached to the first surface of the semiconductor chip on the top layer.

[0012] In some embodiments, the heat dissipation cover is attached to the surface of the semiconductor chip on the top layer, including: the heat dissipation cover is not only attached to the first surface of the semiconductor chip on the top layer, but also attached to the sides around the semiconductor chip on the top layer.

[0013] In some embodiments, the heat dissipation cover is attached to the step surface of the step area and the surface of the semiconductor chip on the top layer by heat dissipation adhesive, and the heat dissipation adhesive fills the hollow hole.

[0014] In some embodiments, it further includes: a transfer plate for electrically connecting the semiconductor chip above the bottom semiconductor chip to the substrate, and the transfer plate is located on a side of the stacking structure away from the step area.

[0015] In some embodiments, the stacking structure includes multiple layers of semiconductor chips sequentially stacked in a direction perpendicular to the upper surface of the substrate, including: the stacking structure only includes multiple layers of first semiconductor chips sequentially stacked in a direction perpendicular to the upper surface of the substrate.

[0016] In some embodiments, the stacking structure includes a first sub-stack structure and a second sub-stack structure located on one side of the first sub-stack structure, the semiconductor chip includes a first semiconductor chip and a second semiconductor chip, the step area includes a first step area and a second step area, the first sub-stack structure includes a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the upper surface of the substrate, one end of the first sub-stack structure has a first step area, the first step area includes a number of steps that are gradually raised, the second sub-stack structure includes a plurality of second semiconductor chips stacked in sequence along a direction perpendicular to the upper surface of the substrate, one end of the second sub-stack structure has a second step area, the second step area includes a number of steps that are gradually raised; the heat dissipation cover is mounted on the step surface of the first step area of ​​the first sub-stack structure and the surface of the first semiconductor chip on the top layer, the heat dissipation cover is also mounted on the step surface of the second step area of ​​the second sub-stack structure and the surface of the second semiconductor chip on the top layer, and the heat dissipation cover at the top corners of the steps of the first step area and the second step area has a hollow hole.

[0017] In some embodiments, a second hollow hole is formed in the heat dissipation cover located on the surface of the top first semiconductor chip and the top second semiconductor chip.

[0018] The technical solution of this application has the following advantages:

[0019] The multi-chip stacking packaging structure in some of the aforementioned embodiments of the present application comprises: a substrate; a stacking structure located on the upper surface of the substrate, the stacking structure comprising multiple layers of semiconductor chips stacked in sequence in a direction perpendicular to the upper surface of the substrate, one end of the stacking structure having a step area, the step area comprising a plurality of steps that are gradually raised, each of the steps having a corresponding vertex angle; a heat dissipation cover mounted on the step surface of the step area and the surface of the semiconductor chip on the top layer, and the heat dissipation cover located at the vertex angle of the step has a hollow hole. The presence of the step area and the heat dissipation cover enables the heat generated by the semiconductor chips of all layers (including the top layer and the middle layer) in the stacking structure to be released through the heat dissipation cover, thereby improving the heat dissipation performance, thereby improving the electrical performance of the packaging structure. And since the heat dissipation cover located at the vertex angle of the step has a hollow hole, the presence of the hollow hole can effectively release the stress in the heat dissipation cover, thereby improving the bonding force or bonding performance between the heat dissipation cover and the step surface of the step area and the surface of the semiconductor chip on the top layer, thereby preventing the heat dissipation cover from warping and the packaging structure from generating delamination defects. Furthermore, when the heat dissipation cover is mounted, the heat dissipation adhesive can also fill the hollow holes, thereby further improving the bonding force or bonding performance between the heat dissipation cover and the step surface of the step area and the surface of the semiconductor chip on the top layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1This is a schematic diagram of a multi-chip stacking packaging structure in some embodiments of the present application;

[0021] Figure 2 for Figure 1 A schematic diagram of a top view of a heat dissipation cover in a multi-chip stacked packaging structure is shown;

[0022] Figure 3 This is a schematic diagram of a multi-chip stacking packaging structure in some other embodiments of the present application;

[0023] Figure 4 for Figure 3 A schematic top view of the heat dissipation cover in a multi-chip stacked packaging structure is shown.

[0024] Figure 5 This is a schematic diagram of a multi-chip stacking packaging structure in some other embodiments of the present application;

[0025] Figure 6 for Figure 5 A schematic top view of the heat dissipation cover in a multi-chip stacked packaging structure is shown. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0027] Some embodiments of the present application provide a multi-chip stacking packaging structure, referring to Figure 1 and Figure 2 , Figure 2 for Figure 1 The schematic diagram of the top view of the middle heat dissipation cover 207 includes:

[0028] substrate 100;

[0029] A stacking structure 200 located on the upper surface of the substrate 100, the stacking structure 200 includes multiple layers of semiconductor chips 201 stacked in sequence in a direction perpendicular to the upper surface of the substrate 100, one end of the stacking structure has a step area 21, the step area 21 includes a plurality of gradually rising steps, each of the steps has a corresponding vertex angle 22;

[0030] A heat dissipation cover 207 is mounted on the step surface of the step area 21 and the surface of the semiconductor chip 201 on the top layer, and the heat dissipation cover 207 located at the top corner 22 of the step has a hollow hole 208 (refer to Figure 2 ).

[0031] Specifically, the substrate 100 includes an upper surface and a lower surface relative to each other, the upper surface has a plurality of first pads (not shown in the figure), the lower surface has a plurality of second pads (not shown in the figure), the substrate 100 has a first circuit (not shown in the figure), the first circuit may include one or more of a metal line, a metal plug, a through-hole connection structure, and a via connection structure, the first pad and the second pad are connected to the first circuit, the second pad has an external bump 102 on its surface, the external bump 102 is used to be electrically connected to other packaging structures, substrates or devices, part of the first pad is electrically connected to the bottom semiconductor chip 201 of the stacked structure 200, in a specific embodiment, part of the first pad can be welded to the welding bump 203 on the second surface of the bottom semiconductor chip 201 of the stacked structure 200. In other embodiments, part of the first pad can also be electrically connected to the adapter 300. In some embodiments, the substrate 100 can be one of a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, a metal substrate, a printed circuit board (PCB) or a flexible circuit board (FPC). The substrate may be a single-layer board or a multi-layer board. The materials of the first pad, the second pad and the first circuit are metals, and may be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and WSi. The material of the external bump 102 includes solder, and may be one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0032] The stacking structure 200 includes a plurality of semiconductor chips 201 stacked in sequence along a direction perpendicular to the upper surface of the substrate 100. The number of layers of the semiconductor chip 201 is at least two, and can be two, three, four, five or more layers. In this embodiment, the semiconductor chip 201 with three layers is taken as an example for description.

[0033] One end of the stacking structure 200 has a step area 21, and the step area 21 includes a plurality of steps that are gradually raised. The step area is formed by stacking a plurality of semiconductor chips in sequence, and each step has a corresponding vertex angle 22. The number of the steps is the same as the number of layers of the semiconductor chip 201, that is, each layer of semiconductor chip 201 forms a step, and the surface of each step includes a third surface and a fourth surface that intersect, and the intersection of the third surface and the fourth surface is the vertex angle 22. In a specific embodiment, the third surface is a horizontal surface, and the fourth surface is a vertical surface. The presence of the steps in the step area 21 in the stacking structure 200 makes at least a portion of the semiconductor chip 201 of each layer in the stacking structure 200 exposed, so that when the heat dissipation cover 207 is mounted on the step surface of the step area 21 of the stacking structure 200 and the surface of the semiconductor chip 201 of the top layer of the stacking structure, the semiconductor chips 201 of all layers (including the top layer and the middle layer) in the stacking structure 200 can be cooled, thereby improving the heat dissipation performance, thereby improving the electrical performance of the packaging structure.

[0034] In one embodiment, the lateral area of ​​the step accounts for 1 / 4-1 / 2 of the surface area of ​​the first surface of the semiconductor chip 201, while ensuring the heat dissipation efficiency, ensuring that the upper semiconductor chip 201 and the lower semiconductor chip 201 have sufficient connection point layout space, and ensuring the mechanical stability of the stacking structure 200.

[0035] The functions of the semiconductor chips 201 of different layers may be the same or different. The semiconductor chips 201 of different layers may be logic chips or memory chips. In some embodiments, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip or a complementary metal oxide semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static RAM (SRAM) or a non-volatile memory chip (such as a flash memory (Flash), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM) or a resistive RAM (ReRAM)). In a specific embodiment, the memory chip may include a high bandwidth memory (HBM) including a DRAM chip.

[0036] In some embodiments, the semiconductor chip 201 includes a first surface and a second surface relative to each other, and a side surface located between the first surface and the second surface, the second surface has a welding bump 203, the first surface has a connecting pad (not shown in the figure), the semiconductor chip 20 has an integrated circuit (not shown in the figure) (with specific functions), and the integrated circuit is electrically connected to the welding bump 203 and the connecting pad. The stacking method of the multi-layer semiconductor chips 201 in the stacking structure 200 is to flip-chip stack in sequence along a direction perpendicular to the upper surface of the substrate 100, so that the welding bump 203 on the second surface of the upper semiconductor chip 201 is connected to the connecting pad on the first surface of the adjacent lower semiconductor chip 201, and the welding bump 203 on the second surface of the bottom semiconductor chip 201 is electrically connected to the substrate 100. While realizing the electrical connection between the upper semiconductor chip 201 and the lower semiconductor chip 201, the thickness of the packaging structure can be reduced and the signal transmission rate can be improved.

[0037] In some embodiments, an underfill layer 204 is further filled between the upper semiconductor chip 201 and the lower semiconductor chip 201 and between the bottom semiconductor chip 201 and the upper surface of the substrate 101 , and the material of the underfill layer 204 is resin.

[0038] In some embodiments, in order to realize the connection between the upper semiconductor chip 201 and the substrate 100, the packaging structure may further include: an adapter plate 300, which is used to electrically connect the semiconductor chip 201 above the bottom semiconductor chip 201 to the substrate 100, and the adapter plate 300 is located on the side of the stacking structure 200 away from the step area 21. In a specific embodiment, the adapter plate 300 has a plurality of connection circuits 301, and different connection circuits 301 can be electrically connected to semiconductor chips 201 of different layers. In a specific embodiment, the stacking structure 200 has an inverted step area at one end away from the step area 21, and the inverted step area has inverted steps that are gradually raised, and the horizontal surface of each inverted step corresponds to a part of the second surface of the semiconductor chip 201, and the second surface corresponding to the inverted step has an external pad (not shown in the figure), and the connection circuit 301 in the adapter plate 300 is electrically connected to the corresponding external pad.

[0039] The heat dissipation cover 207 is attached to the step surface of the step area 21 and the surface of the semiconductor chip 201 on the top layer. In a specific embodiment, the heat dissipation cover 207 is attached to the step surface of the step area 21 and the surface of the semiconductor chip 201 on the top layer through the heat dissipation adhesive 206. The heat dissipation adhesive 206 plays the role of adhesion and heat conduction. Therefore, the heat generated by the semiconductor chips 201 in all layers (including the top layer and the middle layer) in the stacked structure 200 can be released through the heat dissipation cover 207, thereby improving the heat dissipation performance, thereby improving the electrical performance of the packaging structure. And because the heat dissipation cover 207 located at the top corner 22 of the step has a hollow hole 208 (refer to Figure 2 ), the existence of the hollow holes 208 can effectively release the stress in the heat dissipation cover 207, thereby improving the bonding force or bonding performance between the heat dissipation cover 207 and the step surface of the step area 21 and the surface of the semiconductor chip 201 on the top layer, thereby preventing the heat dissipation cover from warping and the packaging structure from having delamination defects. In addition, the heat dissipation adhesive 206 can also fill the hollow holes 208. Specifically, the heat dissipation adhesive 206 can partially fill or fully fill the hollow holes 208, thereby further improving the bonding force or bonding performance between the heat dissipation cover 207 and the step surface of the step area 21 and the surface of the semiconductor chip 201 on the top layer.

[0040] In some embodiments, the number of the hollow holes 208 in the heat dissipation cover 207 corresponding to the top corner 22 of each step may be one or more. In a specific embodiment, the shape of the hollow holes 208 may be circular, elliptical or polygonal.

[0041] In some embodiments, reference Figure 1 The heat dissipation cover 207 is mounted on the surface of the semiconductor chip 201 on the top layer, including: the heat dissipation cover 207 is mounted on the first surface of the semiconductor chip 201 on the top layer.

[0042] In other embodiments, reference Figure 3 and Figure 4 , Figure 4 for Figure 3 The top view of the heat dissipation cover 207 in the top semiconductor chip 201 is shown in FIG. 2 , wherein the heat dissipation cover 207 is attached to the surface of the top semiconductor chip 201, including: the heat dissipation cover 207 is not only attached to the first surface of the top semiconductor chip 201, but also attached to the sides of the top semiconductor chip 201 to improve the heat dissipation performance of the heat dissipation cover 207 to the top semiconductor chip 201. In some embodiments, the heat dissipation cover 207 at the four corners of the top semiconductor chip 201 may have a third hollow hole 209, and the third hollow hole 209 can further release the stress in the heat dissipation cover 207.

[0043] In some embodiments, continue to refer to Figure 1 The stacking structure 200 includes multiple layers of semiconductor chips stacked in sequence along a direction perpendicular to the upper surface of the substrate 100 , including: the stacking structure 200 only includes multiple layers of first semiconductor chips 201 stacked in sequence along a direction perpendicular to the upper surface of the substrate 100 .

[0044] In other embodiments, reference Figure 5 and Figure 6 , Figure 6 for Figure 5 The schematic diagram of the top view of the heat dissipation cover 207 is a schematic diagram of the structure of the heat dissipation cover 207 in the middle, wherein the stacking structure includes a first sub-stacked structure 200a and a second sub-stacked structure 200b located on one side of the first sub-stacked structure 200a, the semiconductor chip includes a first semiconductor chip 201a and a second semiconductor chip 201b, the step area includes a first step area 21a and a second step area 21b, the first sub-stacked structure 200a includes a plurality of first semiconductor chips 201a stacked in sequence along a direction perpendicular to the upper surface of the substrate 100, one end of the first sub-stacked structure 200a has a first step area 21a, the first step area 21a includes a plurality of steps that are gradually raised, and the second sub-stacked structure 200b includes a plurality of first semiconductor chips 201a stacked in sequence along a direction perpendicular to the upper surface of the substrate 100. The second semiconductor chip 201b is stacked in a multi-layer manner in a plane direction, and one end of the second sub-stack structure 200b (the end away from the first sub-stack structure 200a) has a second step area 21b, and the second step area 21b includes a plurality of steps that are gradually raised; the heat dissipation cover 207 is mounted on the step surface of the first step area 21a of the first sub-stack structure 200a and the surface of the first semiconductor chip 201a on the top layer, and the heat dissipation cover 207 is also mounted on the step surface of the second step area 21b of the second sub-stack structure 200b and the surface of the second semiconductor chip 201b on the top layer, and the heat dissipation cover 207 located at the top corner of the step of the first step area 21a and the second step area 21b has a hollow hole 208 (reference Figure 6 ).

[0045] In a specific embodiment, the first sub-stack structure 200a and the second sub-stack structure 200b may be arranged in an axisymmetric manner. In other embodiments, the first sub-stack structure 200a and the second sub-stack structure 200b may be arranged in other ways.

[0046] The first semiconductor chip 201a and the second semiconductor chip 201b each include a first surface and a second surface opposite to each other, the second surface of the first semiconductor chip 201a has a first solder bump 203a, the second surface of the second semiconductor chip 201b has a second solder bump 203b, the first bottom filling layer 204a is filled between the first semiconductor chips 201a of adjacent layers and between the first semiconductor chip 201a of the bottom layer and the substrate 100, and the second bottom filling layer 204b is filled between the second semiconductor chips 201b of adjacent layers and between the second semiconductor chip 201b of the bottom layer and the substrate 100. Other descriptions or definitions of the first semiconductor chip 201a and the second semiconductor chip 201b are similar to the definitions or descriptions of the semiconductor chip 201 in the aforementioned embodiment, please refer to the definitions or descriptions of the semiconductor chip 201 in the aforementioned embodiment for details, which will not be repeated here.

[0047] In some embodiments, the first sub-stack structure 200 a and the second sub-stack structure 200 b may be filled with a plastic packaging layer.

[0048] In some embodiments, the present invention further includes: a first adapter plate 300a and a second adapter plate 300b, wherein the first adapter plate 300a is electrically connected to other first semiconductor chips 201a above the bottom-most first semiconductor chip 201a from one end of the first step area 21a away from the first sub-stack structure 200a, and the first adapter plate 300a is also electrically connected to the substrate 100, and the second adapter plate 300b is electrically connected to other second semiconductor chips 201b above the bottom-most second semiconductor chip 201b from one end of the second step area 21b away from the second sub-stack structure 200b, and the second adapter plate 300b is also electrically connected to the substrate 100.

[0049] In some embodiments, the heat dissipation cover 207 located on the surface of the top first semiconductor chip 201 a and the top second semiconductor chip 201 b has a second hollow hole 210 , and the second hollow hole 210 can further release the stress in the heat dissipation cover 207 .

[0050] It should be noted that the terms "including" and "having" and their variations involved in this application are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of this application. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to (or referenced) with each other.

[0051] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A multi-chip stacking package structure, characterized in that: include: substrate; A stacking structure located on the upper surface of the substrate, the stacking structure includes multiple layers of semiconductor chips stacked in sequence along a direction perpendicular to the upper surface of the substrate, one end of the stacking structure has a step area, the step area includes a plurality of steps that are gradually raised, each of the steps has a corresponding vertex angle; a heat dissipation cover mounted on the step surface of the step area and the surface of the semiconductor chip on the top layer, and the heat dissipation cover located at the vertex angle of the step has a hollow hole.

2. The multi-chip stacking package structure according to claim 1, wherein: The number of the hollow holes in the heat dissipation cover corresponding to the top corner of each step is one or more.

3. The multi-chip stacking package structure according to claim 1, wherein: The semiconductor chip includes a first surface and a second surface relative to each other, and a side surface located between the first surface and the second surface, the second surface has a welding bump, the first surface has a connecting pad, and the stacking structure includes a plurality of layers of semiconductor chips stacked in sequence in a direction perpendicular to the upper surface of the substrate, so that the welding bumps on the second surface of the semiconductor chip of the upper layer are connected to the connecting pads on the first surface of the semiconductor chip of the adjacent lower layer, and the welding bumps on the second surface of the semiconductor chip of the bottom layer are electrically connected to the substrate.

4. The multi-chip stacking package structure according to claim 3, characterized in that: The heat dissipation cover is attached to the surface of the semiconductor chip on the top layer, including: the heat dissipation cover is attached to the first surface of the semiconductor chip on the top layer.

5. The multi-chip stacking package structure according to claim 3, characterized in that: The heat dissipation cover is attached to the surface of the semiconductor chip on the top layer, including: the heat dissipation cover is not only attached to the first surface of the semiconductor chip on the top layer, but also attached to the side surfaces around the semiconductor chip on the top layer.

6. The multi-chip stacking package structure according to any one of claims 1 to 5, characterized in that: The heat dissipation cover is attached to the step surface of the step area and the surface of the semiconductor chip on the top layer by means of heat dissipation adhesive, and the heat dissipation adhesive fills the hollow hole.

7. The multi-chip stacking package structure according to claim 6, wherein: Also includes: The adapter plate is used to electrically connect the semiconductor chip above the bottom semiconductor chip to the substrate, and the adapter plate is located on a side of the stacking structure away from the step area.

8. The multi-chip stacking package structure according to claim 1, wherein: The stacking structure includes a plurality of semiconductor chips sequentially stacked in a direction perpendicular to the upper surface of the substrate, including: the stacking structure includes only a plurality of first semiconductor chips sequentially stacked in a direction perpendicular to the upper surface of the substrate.

9. The multi-chip stacking package structure according to claim 1, wherein: The stacking structure includes a first sub-stack structure and a second sub-stack structure located on one side of the first sub-stack structure, the semiconductor chip includes a first semiconductor chip and a second semiconductor chip, the step area includes a first step area and a second step area, the first sub-stack structure includes a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the upper surface of the substrate, one end of the first sub-stack structure has a first step area, the first step area includes a plurality of steps that are gradually raised, the second sub-stack structure includes a plurality of second semiconductor chips stacked in sequence along a direction perpendicular to the upper surface of the substrate, one end of the second sub-stack structure has a second step area, the second step area includes a plurality of steps that are gradually raised; the heat dissipation cover is mounted on the step surface of the first step area of ​​the first sub-stack structure and the surface of the first semiconductor chip on the top layer, the heat dissipation cover is also mounted on the step surface of the second step area of ​​the second sub-stack structure and the surface of the second semiconductor chip on the top layer, and the heat dissipation cover at the top corners of the steps of the first step area and the second step area has a hollow hole.

10. The multi-chip stacking package structure according to claim 9, wherein: The heat dissipation cover located on the surface of the top-layer first semiconductor chip and the top-layer second semiconductor chip has a second hollow hole.

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