Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure comprises a first lead frame which comprises a plurality of first and second pins which are arranged in a surrounding manner; each first chip comprises a first surface and a second surface which are oppositely arranged, and the first surfaces are inversely arranged on the surfaces of the first pins; the second lead frame comprises a third surface and a fourth surface which are oppositely arranged, the second lead frame further comprises a main base island and a plurality of auxiliary base islands arranged on the periphery of the main base island, the main base island and the auxiliary base islands are connected through connecting rods, the main base island and the first lead frame are on the same layer, and the main base island is surrounded by the first pin and the second pin; the third surface of each auxiliary base island is arranged on the second surface of a first chip; the second chip comprises a fifth surface and a sixth surface which are oppositely arranged, and the fifth surface is positively arranged on the fourth surface of the main base island; and the bonding wire is connected with the sixth surface of the second chip and the second pin. According to the technical scheme, back interconnection of the first chip and the second chip can be achieved, and the integration requirements of more packaging units are met.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a chip packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, a new design method of chiplet technology has emerged, which packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips increases, the number of chips integrated in a single package increases significantly. The existing 2.5D packaging technology is to package multiple small chips into one package as a multi-chip packaging solution to connect adjacent chip pads in a single package to improve its packaging integration.

[0003] However, the existing 2.5D packaging is mainly based on the packaging on the substrate, and the lead frame is less used in 2.5D packaging due to its low interconnection density. Therefore, how to increase the integration of lead frame-based packaging to meet more packaging unit integration requirements and the expansion of application scenarios is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to provide an integrated package based on a lead frame to meet more packaging unit integration requirements and the expansion of application scenarios, and to provide a chip packaging structure.

[0005] In order to solve the above problems, the utility model provides a chip packaging structure, including: a first lead frame, including a plurality of first pins and a plurality of second pins arranged in a surrounding manner; a plurality of first chips, including a first surface and a second surface arranged oppositely, the first surface being flipped on the surface of the first pin of the first lead frame; a second lead frame, including a third surface and a fourth surface arranged oppositely, the second lead frame further including a main base island and a plurality of auxiliary base islands arranged on the periphery of the main base island, the main base island and the auxiliary base islands being connected by a connecting rod, the main base island being in the same layer as the first lead frame and being surrounded by the first pin and the second pin, the third surface of each of the auxiliary base islands being arranged on the second surface of one of the first chips; a second chip, including a fifth surface and a sixth surface arranged oppositely, the fifth surface of the second chip being mounted on the fourth surface of the main base island; a welding wire connecting the sixth surface of the second chip and the second pin.

[0006] In some embodiments, a projection of the sub-base island on the surface of the first lead frame completely or partially overlaps with a projection of the first chip on the surface of the first lead frame.

[0007] In some embodiments, the first lead frame has four groups of pin arrays distributed on four opposite sides, two adjacent groups of the pin arrays are perpendicular to each other, and each of the pin arrays includes a plurality of the second pins and a plurality of the first pins located on both sides of the plurality of the second pins.

[0008] In some embodiments, the length of the first pin is less than or equal to the length of the second pin, and the length of the first pin decreases in a direction approaching a junction of the pin array.

[0009] In some embodiments, the first chip is disposed at an intersection of the pin array.

[0010] In some embodiments, the first surface of the first chip is flip-chip mounted on the first lead surface via solder bumps.

[0011] In some embodiments, the fifth surface of the second chip is mounted on the fourth surface of the main base island through an adhesive.

[0012] In some embodiments, the sixth surface of the second chip includes a plurality of conductive pads, each of which is connected to a second pin via a bonding wire.

[0013] In some embodiments, a package is also included, covering the first lead frame, the first chip, the second chip, the second lead frame and the bonding wire, and the first pin and the second pin are exposed to the package away from the surface of the first chip and the third surface of the main base island.

[0014] The above technical solution arranges multiple flip-chip first chips between the first lead frame and the second lead frame, and then uses the second lead frame as a base island to mount the upright second chip. The second lead frame can realize the back interconnection between the first chip and the second chip to meet more packaging unit integration requirements and the expansion of application scenarios; the second lead frame can also dissipate the heat of the first chip and the second chip from the back of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0015] It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the specific implementation of the utility model, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a schematic top view of the chip packaging structure according to an embodiment of the present invention.

[0018] Figure 2 It is a side view structural schematic diagram of an embodiment of the chip packaging structure of the present invention.

[0019] Figure 3 The schematic diagram is a top view of the structure of an embodiment of the first lead frame of the chip packaging structure of the utility model.

[0020] Figure 4 The schematic diagram of the top view of the chip packaging structure of the utility model shows the positional relationship between the first lead frame and the first chip in one embodiment.

[0021] Figure 5 The figure is a top view of the structure of an embodiment of the second lead frame of the chip packaging structure of the present invention. DETAILED DESCRIPTION

[0022] The technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0023] Please also read Figure 1 to Figure 5 ,in, Figure 1 A schematic top view of an embodiment of the chip packaging structure of the utility model; Figure 2 It is a schematic side view of an embodiment of the chip packaging structure of the utility model; Figure 3 A schematic top view of the structure of an embodiment of the first lead frame of the chip packaging structure of the utility model; Figure 4 A schematic top view of the positional relationship between the first lead frame and the first chip of the chip packaging structure of the utility model according to an embodiment; Figure 5 The figure is a top view of the structure of an embodiment of the second lead frame of the chip packaging structure of the present invention.

[0024] like Figure 1 to Figure 5As shown, the chip packaging structure of the utility model includes: a first lead frame 111, a first chip 121, a second lead frame 112, a second chip 122, and a bonding wire 130. The first lead frame 111 includes a plurality of first pins 31 and a plurality of second pins 32 arranged in a surrounding manner. The plurality of first chips 121 include a first surface S1 and a second surface S2 arranged oppositely, and the first surface S1 of the first chip 121 is flipped on the surface of the first pin 31 of the first lead frame 111. The second lead frame 112 includes a third surface S3 and a fourth surface S4 arranged oppositely, and the second lead frame 112 further includes a main base island 51 and a plurality of sub-base islands 52 arranged on the periphery of the main base island 51, the main base island 51 and the sub-base island 52 are connected by a connecting rod 53, the main base island 51 is in the same layer as the first lead frame 111 and is surrounded by the first pin 31 and the second pin 32, and the third surface S3 of each sub-base island 52 is arranged on the second surface S2 of the first chip 121. The second chip 122 includes a fifth surface S5 and a sixth surface S6 disposed opposite to each other. The fifth surface S5 of the second chip 122 is mounted on the fourth surface S4 of the main base island 51. The bonding wire 130 connects the sixth surface S6 of the second chip 122 and the second lead 32.

[0025] The above technical solution arranges multiple flip-chip first chips between the first lead frame and the second lead frame, and then uses the second lead frame as a base island to mount the upright second chip. The second lead frame can realize the back interconnection between the first chip and the second chip to meet more packaging unit integration requirements and the expansion of application scenarios; the second lead frame can also dissipate the heat of the first chip and the second chip from the back of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0026] In some embodiments, the first chip 121 and the second chip 122 may be memory chips, wherein the memory integrated circuits may be such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, resistive random access memory (ReRAM) devices, ferroelectric random access memory (FeRAM) devices, or phase change random access memory (PcRAM) devices.

[0027] Please refer to Figure 1In some embodiments, the projection of the auxiliary base island 52 on the surface of the first lead frame 111 completely or partially overlaps with the projection of the first chip 121 on the surface of the first lead frame 111, so that the first chip 121 is connected to the main base island 51 through the auxiliary base island 52, and then the back side of the first chip 121 is connected to the back side of the second chip 122, and at the same time, the heat of the first chip 121 and the second chip 122 are dissipated from the back side of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0028] like Figure 3 As shown, in some embodiments, the first lead frame 111 has four groups of pin arrays 301 distributed on four opposite sides, two adjacent groups of the pin arrays 301 are perpendicular to each other, and each of the pin arrays 301 includes a plurality of second pins 32 and a plurality of first pins 31 located on both sides of the plurality of second pins 32. In this embodiment, each of the pin arrays 301 includes four first pins 31 and four second pins 32, and the first pins 31 are located on both sides of the second pins 32.

[0029] In some embodiments, the length of the first pin 31 is less than or equal to the length of the second pin 32, and the length of the first pin 31 decreases in a direction approaching the intersection 303 of the pin array 301. Figure 1 as well as Figure 3 , a longer second pin 32 is provided to facilitate connection between the sixth surface S6 of the second chip 122 and the second pin 32. The length of the first pin 31 is arranged to decrease in a direction close to the intersection 303 of the pin array 301 to meet the space limitation of the intersection 303 of the pin array 301.

[0030] like Figure 4 As shown, in some embodiments, the first chip 121 is disposed at the intersection 303 of the pin array 301 .

[0031] In other embodiments, the pin array 301 may also be composed of a plurality of first pins 31 and a plurality of second pins 32 located on both sides of the plurality of first pins 31; the length of the second pins 32 is less than or equal to the length of the first pins 31, and the length of the second pins 32 decreases in a direction approaching the intersection of the pin array 301. Accordingly, the first chip 121 is disposed on the first pins 31, that is, at the center of the pin array 301.

[0032] Combined with reference Figure 2 as well as Figure 4In some embodiments, the first surface S1 of the first chip 121 is flip-mounted on the surface of the first lead 31 through the solder bump 21 .

[0033] like Figure 5 As shown, in this embodiment, the second lead frame 112 includes a main base island 51 and four auxiliary base islands 52. The main base island 51 and the auxiliary base island 52 are both rectangular base islands. The four corners of the main base island 51 are connected to the four auxiliary base islands 52 through the connecting rods 53. Figure 1 , Figure 3 as well as Figure 5 The auxiliary base island 52 is located at the intersection 303 of the pin array 301. While the auxiliary base island 52 is connected to the first chip 121, it does not affect the connection between the bonding wire 130 and the second pin 32, thereby realizing a reasonable layout of the packaging space and improving the utilization rate of the packaging space.

[0034] In this embodiment, the connecting rod 53 is a straight rod extending from the main base island 51 to the auxiliary base island 52. In other embodiments, the connecting rod 53 may also be in an arc shape, a step shape, an "L" shape or a "C" shape.

[0035] like Figure 2 As shown, in some embodiments, the fifth surface S5 of the second chip 122 is mounted on the fourth surface S4 of the main base island 51 through the adhesive 22. In this embodiment, the adhesive 22 is a conductive adhesive. In other embodiments, the adhesive 22 can also be a non-conductive adhesive.

[0036] Combined with reference Figure 1 as well as Figure 2 In some embodiments, the sixth surface S6 of the second chip 122 includes a plurality of conductive pads 140 , and each of the conductive pads 140 is connected to a second pin 32 via a bonding wire 130 .

[0037] In some embodiments, a third surface S3 of the sub-base island 52 and a surface of the first lead 31 have a distance in a direction perpendicular to the surface of the first lead frame 111 , providing packaging space for the second chip 122 and the bonding wire 130 .

[0038] like Figure 2As shown, it also includes a package body 150, covering the first lead frame 111, the first chip 121, the second chip 122, the second lead frame 112 and the bonding wire 130, and the first pin 31 and the second pin 32 are away from the surface of the first chip 121 and the third surface S3 of the main base island 51 are exposed to the package body 150. In order to clearly show the chip packaging structure of the utility model, Figure 1 The package body 150 is not shown.

[0039] The above technical solution arranges multiple flip-chip first chips between the first lead frame and the second lead frame, and then uses the second lead frame as a base island to mount the upright second chip. The second lead frame can realize the back interconnection between the first chip and the second chip to meet more packaging unit integration requirements and the expansion of application scenarios; the second lead frame can also dissipate the heat of the first chip and the second chip from the back of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0040] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0041] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0042] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present utility model. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0043] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A first lead frame includes a plurality of first pins and a plurality of second pins arranged in a surrounding manner; A plurality of first chips, comprising a first surface and a second surface arranged opposite to each other, wherein the first surface is flip-mounted on the first pin surface of the first lead frame; A second lead frame, comprising a third surface and a fourth surface arranged opposite to each other, the second lead frame further comprising a main base island and a plurality of sub-base islands arranged outside the main base island, the main base island and the sub-base islands being connected by a connecting rod, the main base island being in the same layer as the first lead frame and surrounded by the first pin and the second pin, the third surface of each of the sub-base islands being arranged on the second surface of the first chip; A second chip comprises a fifth surface and a sixth surface which are arranged opposite to each other, wherein the fifth surface of the second chip is mounted on the fourth surface of the main base island; A bonding wire connects the sixth surface of the second chip and the second pin.

2. The chip packaging structure according to claim 1, characterized in that: A projection of the sub-base island on the surface of the first lead frame completely or partially overlaps with a projection of the first chip on the surface of the first lead frame.

3. The chip packaging structure according to claim 1, characterized in that: The first lead frame has four groups of pin arrays distributed on four opposite sides, two adjacent groups of the pin arrays are perpendicular to each other, and each of the pin arrays includes a plurality of the second pins and a plurality of the first pins located on both sides of the plurality of the second pins.

4. The chip packaging structure according to claim 3, characterized in that: The length of the first pin is less than or equal to the length of the second pin, and the length of the first pin decreases in a direction approaching a junction of the pin array.

5. The chip packaging structure according to claim 4, characterized in that: The first chip is arranged at the intersection of the pin arrays.

6. The chip packaging structure according to claim 1, characterized in that: The first surface of the first chip is flip-mounted on the first lead surface through solder bumps.

7. The chip packaging structure according to claim 1, characterized in that: The fifth surface of the second chip is mounted on the fourth surface of the main base island through an adhesive.

8. The chip packaging structure according to claim 1, characterized in that: The sixth surface of the second chip includes a plurality of conductive pads, each of which is connected to a second pin through a bonding wire.

9. The chip packaging structure according to claim 1, characterized in that: It also includes a package body, covering the first lead frame, the first chip, the second chip, the second lead frame and the bonding wire, and the first pin and the second pin are exposed to the package body away from the surface of the first chip and the third surface of the main base island.

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