Packaging structure of quasi-monolithic power multiplication amplifier

Abstract

The utility model discloses a packaging structure of a quasi-monolithic power multiplication amplifier. The packaging structure comprises a frame base island, the lead frame is arranged on the periphery of the frame base island; the four tube core chips are respectively bonded on the front face of the frame base island through bonding materials, two of the tube core chips are connected through a lead to form a common-gate amplification structure, the other two tube core chips are connected through a lead to form a common-source amplification structure, and the four tube core chips are further connected with the lead frame through leads. The four tube core chips jointly form an amplifying circuit of a push-pull structure; and the frame base island, the lead frame, the four tube core chips and the leads are coated with the plastic package material to form a whole through plastic package. The heat dissipation of the power amplifier is facilitated.

Description

Technical Field

[0001] The utility model relates to the technical field of amplifiers, and particularly relates to a packaging structure of a quasi-monolithic power multiplier amplifier. Background Art

[0002] With the popularization of video, music, game and online media content consumption, future entertainment systems and home office environments are rapidly developing towards more two-way interactive modes. People need faster cable speeds and higher-capacity data transmission, which requires increasing downstream bandwidth and upstream capacity. In order to maintain a competitive advantage in the developing cable television (CATV) business, innovative technologies need to be adopted to meet user needs. The new generation of DOCSIS 4.0 enables CATV operators to increase upstream and downstream capacity more. To meet the increasing bandwidth and data rate requirements, CATV amplifiers must maintain higher linear output power. CATV amplifiers based on gallium nitride (GaN) technology play an important role in this development process. GaN has advantages in these aspects, providing power up to 10W / mm, while typical GaAs designs are only 1W / mm.

[0003] Currently, the typical industry practice is to use bare chips and micro-assembly methods, which can handle the thermal matching and heat dissipation problems of different materials based on gallium arsenide and gallium nitride. The problem is low production efficiency and poor product consistency; or use conventional plastic packaging, but due to the limitations of conductive adhesives and packaging structures, such as conventional packaging integrates all circuits on a single chip, this packaging structure has poor heat dissipation performance, limits the power of the amplifier, and reduces the performance of the device.

[0004] Therefore, the prior art needs to be improved. Summary of the Utility Model

[0005] In view of the deficiencies of the above prior art, the purpose of the present utility model is to provide a packaging structure of a quasi-monolithic power multiplier amplifier, aiming to reduce the packaging cost while improving the yield and consistency and being beneficial to the heat dissipation of the amplifier.

[0006] To achieve the above purpose, the present utility model adopts the following technical solutions:

[0007] The present utility model provides a packaging structure of a quasi-monolithic power multiplier amplifier, which includes:

[0008] A frame base island;

[0009] A lead frame disposed on the periphery of the frame base island;

[0010] Four die chips are respectively bonded to the front of the frame base island through a bonding material. Two of the die chips are connected by leads to form a common-gate amplification structure, and the other two die chips are connected by leads to form a common-source amplification structure. The four die chips are also connected to the lead frame through leads, and the four die chips together form an amplification circuit with a push-pull structure;

[0011] The encapsulation material encapsulates the frame base island, the lead frame, the four die chips and the leads to form an integral package.

[0012] In some examples, the four die chips respectively include two gallium nitride FET die chips and two gallium arsenide HEMT die chips. The two gallium nitride FET die chips form a common-gate amplification structure, and the two gallium arsenide HEMT die chips form a common-source amplification structure.

[0013] In some examples, the bonding material is sintered silver paste.

[0014] In some examples, the silver content of the sintered silver paste is about 85%, and the thermal conductivity of the sintered silver paste reaches 130 W / m.k.

[0015] In some examples, the two gallium nitride FET die chips and the two gallium arsenide HEMT die chips are arranged parallel to each other on the front of the frame base island, and the source contact pads of the two gallium nitride FET die chips and the drain contact pads of the two gallium arsenide HEMT die chips are close. The distance between the two die chips is 100 - 200 um.

[0016] In some examples, the lead frame includes multiple pins, and the multiple pins include output pins, input pins, bias pins, and ground pins;

[0017] The gate contact pads of the two gallium arsenide HEMT die chips are both connected to the input pins of the lead frame through leads. The source contact pads of the two gallium arsenide HEMT die chips are connected to the ground pins of the lead frame through leads. The drain contact pads of the two gallium arsenide HEMT die chips are respectively connected to the source contact pads of the two gallium nitride FET die chips through leads;

[0018] The drain contact pads of the two gallium nitride FET die chips are both connected to the output pins of the lead frame through leads. The gate contact pads of the two gallium nitride FET die chips are connected to the bias pins of the lead frame through leads.

[0019] In some examples, the frame base island is made of copper-iron-phosphorus alloy and has a thickness of 1 - 1.5 mm.

[0020] In some examples, the front of the frame base island is provided with a first locking groove, and the lead frame is made of thin copper material and is provided with a second locking groove on the pins.

[0021] In some examples, the lead is a metal lead, and the metal lead is a 0.25-μm gold wire.

[0022] In some examples, the encapsulation material is an epoxy molding compound with low stress and a glass transition temperature as high as 160°C.

[0023] It should be understood that within the scope of the present utility model, the above-mentioned various technical features of the present utility model and the technical features specifically described hereinafter (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be elaborated one by one here.

[0024] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0025] 1. In the present utility model, four die chips are independently arranged on the front of the frame base island to jointly form an amplifier circuit with a push-pull structure for combined packaging, and its heat dissipation effect is better than that of integrating all circuits on a single chip in the prior art.

[0026] 2. For the four die chips, two gallium arsenide HEMT die chips with a common source electrode using low voltage can achieve good gain; two gallium nitride FET die chips are used for the common gate electrode, which can achieve higher power and linearity. The cost of this product is lower than that of integrating all circuits on a single gallium nitride chip, and while ensuring the high power of the gallium nitride device in the product, its heat dissipation effect is better than that of the device packaged with a single gallium nitride chip.

[0027] 3. The bonding material between the die chip and the frame base island uses sintered silver glue, which has more excellent electrical conductivity and thermal conductivity than traditional silver glue and gold-tin alloy, and its coefficient of thermal expansion matches both gallium nitride and gallium arsenide, two different materials, so that the product has good thermal matching performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0029] Figure 1 It is a schematic diagram of Embodiment 1 of the packaging structure of the quasi-monolithic power multiplier amplifier of the present utility model.

[0030] Figure 2 is Figure 1 a top view schematic diagram of the structure.

[0031] Figure 3 This is a schematic diagram of the application circuit structure of the quasi-monolithic power multiplier amplifier of the present utility model.

[0032] Figure 4 This is a schematic diagram of the temperature curing curve during the sintering of the quasi-monolithic power multiplier amplifier chip of the present utility model.

[0033] Figure 5 This is a flowchart of the preparation method of the quasi-monolithic power multiplier amplifier in the embodiment of the present utility model.

[0034] Reference numerals:

[0035] 10 - Frame base island, 11 - First locking groove, 20 - Lead frame, 21 - Output pin, 22 - Input pin, 23 - Bias pin, 24 - Second locking groove, 25 - Ground pin, 30 - Die chip, 31 - Gallium nitride FET die chip, 32 - Gallium arsenide HEMT die chip, 40 - Bonding material, 50 - Lead, 60 - Plastic encapsulation material. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

[0037] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present utility model are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0038] In the present utility model, unless otherwise clearly defined and limited, terms such as "connection" and "fixation" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0039] In addition, in the present utility model, descriptions such as "first", "second", etc. are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature.

[0040] The present utility model includes the following embodiments.

[0041] Please refer to Figures 1 to 3 , this embodiment provides a packaging structure of a quasi-monolithic power multiplier amplifier, including: a frame base island 10, and the frame base island 10 is used to mount and support the chip.

[0042] Preferably, the frame base island 10 in this embodiment is made of copper-iron-phosphorus alloy and has a thickness of 1 - 1.5 mm. The copper-iron-phosphorus alloy has a high thermal conductivity of up to 262 W / m.k, and also has corrosion resistance and oxidation resistance. The thickened copper-iron-phosphorus alloy significantly improves the heat conduction capacity of the entire base island, greatly increasing the heat dissipation effect and being able to meet the usage requirements of high-frequency and high-power chips such as gallium nitride FET die chips.

[0043] A lead frame 20, which is arranged on the periphery of the frame base island 10. As a way, as Figure 2 shown, the lead frame 20 in this embodiment is respectively arranged on the left and right sides of the frame base island 10 as the input and output ends, and the lead frame 20 serves as a channel for electrical connection between the inside and outside of the packaging structure.

[0044] The lead frame 20 in this embodiment is made of thin copper material, and is interconnected with the frame base island 10 using riveting technology and packaging materials to form a stable structure, and at the same time, a brownification process is added to the lead frame 20.

[0045] Four die chips 30 are respectively bonded to the front surface of the frame base island 10 through a bonding material 40. Among them, two die chips 30 are connected through leads 50 to form a common-gate amplifier structure, and the other two die chips 30 are connected through leads 50 to form a common-source amplifier structure. The four die chips 30 are also connected to the lead frame 20 through leads 50, and the four die chips 30 together form a push-pull structure amplifier circuit.

[0046] As an implementation manner, as Figure 2 and Figure 3 , the four die chips 30 in this embodiment respectively include two gallium nitride FET die chips 31 and two gallium arsenide HEMT die chips 32. The two gallium nitride FET die chips 31 form a common-gate amplifier structure, and the two gallium arsenide HEMT die chips 32 form a common-source amplifier structure.

[0047] The overall circuit structure of a power-doubling type amplifier is generally a push-pull amplifier composed of two cascode structures. From a circuit perspective, it can be implemented with gallium arsenide or gallium nitride. However, the output power of gallium arsenide is relatively small and cannot meet the output index requirements. Gallium nitride is a field-effect transistor with a high-voltage and high breakdown process. If all gallium nitride is used, the operating voltage will need to be doubled to achieve the best performance of the chip, and the cost will increase several times. In the amplifier of the present utility model, the common source electrode uses a low-voltage gallium arsenide HEMT transistor to achieve good gain, and the common gate stage uses a gallium nitride FET transistor to achieve high power and linearity. That is, the amplifier of the present utility model adopts a configuration design of two gallium nitride FET die chips 31 and two gallium arsenide HEMT die chips 32, which can not only ensure the performance of the chip but also reduce the cost.

[0048] The encapsulation material 60 encapsulates the frame base island 10, the lead frame 20, the four die chips 30 and the leads 50 to form an integral package. The function of using the encapsulation material to form an integral package in this embodiment is to protect the chip from damage by the external environment, and at the same time provide electrical connection and heat dissipation support.

[0049] Preferably, the encapsulation material 60 of this embodiment is an epoxy molding compound with low stress and a glass transition temperature as high as 160 °C.

[0050] Some die chip materials such as gallium nitride have the characteristics of high frequency and high power, so the junction temperature can reach up to 200 °C during operation. However, the glass transition temperature Tg of conventional encapsulation materials can only reach about 130 °C. In order to prevent unstable phenomena such as delamination during device operation, the present utility model selects an epoxy molding compound with low stress and a glass transition temperature Tg as high as 160 °C through investigation and comparison of parameters such as the composition, proportion, curing conditions, curing stress release and thermal expansion coefficient of the encapsulation material. This material has stable composition, and has advantages such as good insulation, high bonding strength and strong corrosion resistance. It can adapt to the high-temperature state of gallium nitride during operation, which not only solves the problems of high cost of using metal or ceramic packaging and poor thermal stability and easy moisture absorption of ordinary plastic packaging, but also can maintain good heat dissipation and improve the stability of the product.

[0051] In the encapsulation structure of this embodiment, since four independent die chips 30 are used, its heat dissipation effect is better than that of the prior art in which all circuits are integrated on a single chip, solving the problem that gallium nitride devices in the prior art may generate self-heating effects resulting in too high device temperature, enabling the excellent performance of gallium nitride chips to be fully exerted, and at the same time having better consistency and higher efficiency than traditional hybrid circuit processes, greatly improving the stability and reliability of the product.

[0052] Preferably, the bonding material 40 in this embodiment is sintered silver glue. Further, the silver content of the sintered silver glue is about 85%, and the thermal conductivity of the sintered silver glue reaches 130 W / m·K.

[0053] In the encapsulation structure of this embodiment, the bonding material between the frame base island 10 and the die chip 30 is selected as sintered silver glue with high thermal conductivity. The sintered silver glue contains metallic silver, and the melting point of silver is as high as 961 °C, which has extremely high reliability. The sintered silver glue used in the present utility model has undergone multiple ratios, and finally a sintered silver glue with a silver content of about 85% and other materials such as epoxy resin of about 10% is obtained. The thermal conductivity can reach 130 W / m·K. At a similar sintering temperature, it can have a higher thermal conductivity than traditional silver glue and gold-tin alloy. Moreover, through multiple rounds of tests, it is verified that the thermal expansion coefficient of the sintered silver glue has a good match with that of gallium nitride and gallium arsenide, making the entire structure have very excellent thermal matching and heat dissipation performance, greatly improving the device working environment temperature and service life. This embodiment uses sintered silver glue as the bonding material 40, which solves the problem of thermal matching under the chip combination encapsulation of two different materials.

[0054] Preferably, the bonding method between the die chip 30 and the frame base island 10 is to use sintered silver glue and cooperate with a curing oven to bond the chip according to a set curing curve. When sintering the chip with sintered silver glue, as Figure 4 shown, use the curing oven to set a suitable curing temperature curve. For example, within 30 - 80 minutes after the start of curing, the curing temperature is about 150 °C, and within 90 - 220 minutes after the start of curing, the curing temperature is about 200 °C. Sintering the chip with sintered silver glue in the present utility model has a lower cost than traditional eutectic soldering, and the process is simpler. It can not only improve production efficiency, but also reduce the void ratio to less than 5%, improving the stability and yield of the product.

[0055] As Figure 2 shown, in this embodiment, two gallium nitride FET die chips 31 and two gallium arsenide HEMT die chips 32 are arranged parallel to each other on the front surface of the frame base island 10. The distance between the two die chips 30 is 100 - 200 μm. As Figure 2 shown, between the two gallium arsenide HEMT die chips 32, between the two gallium nitride FET die chips 31, and between the gallium arsenide HEMT die chip 32 and the gallium nitride FET die chip 31, the distance is all 100 - 200 μm. The 100 - 200 μm distance provides sufficient heat dissipation space between the chips. In this embodiment, marks can also be set at the corresponding positions of the die chips 30 on the frame base island 10 to help align the chips.

[0056] In this embodiment, the source contact points S of the two gallium nitride FET die chips 31 are close to the drain contact points D of the two gallium arsenide HEMT die chips 32, facilitating the connection of the two using the shortest leads 50.

[0057] The lead frame 20 of this embodiment includes multiple pins, and the multiple pins include output pins 21, input pins 23, bias pins 23, and ground pins 25.

[0058] Specifically, as Figure 2 shown, the lead frame 20 includes eight pins, which are respectively arranged on the left and right sides of the frame base island 10. The two input pins 22 on the left are radio frequency input terminals, and the two ground pins 25 are ground terminals; the two output pins 21 on the right are radio frequency output and power supply terminals, and the two bias pins 23 are bias terminals.

[0059] The two gallium arsenide HEMT die chips are connected by leads 50 to form the common source of the circuit. The gate G contact points are connected to the pins 22 through leads 50 as the radio frequency input terminal of the circuit, and the source S contact points are connected through leads 50 and connected to the pins 25 as the ground terminal. The two gallium nitride FET die chips are connected by leads 50 to form the common gate of the circuit. The drain D contact points are connected to the pins 21 through leads 50 as the radio frequency output terminal and power supply terminal of the circuit, and the gate G contact points are connected to the pins 23 through leads 50 and connected to the peripheral bias circuit through the pins 23 as the bias terminal. In this way, the two gallium nitride FET die chips 31 and the two gallium arsenide HEMT die chips 32 together form a push-pull structure amplifier circuit to achieve power multiplication amplification.

[0060] Preferably, a first locking groove 11 is provided on the front surface of the frame base island 10, and the lead frame 20 is made of thin copper material and a second locking groove 24 is provided on the pins.

[0061] As Figure 2 shown, the first locking groove 11 is circumferentially provided on the front surface of the frame base island 10 around the periphery of the four die chips 30. This can not only prevent moisture intrusion, but also increase the bonding force between the frame base island 10 and the plastic encapsulation material 60, improve the moisture sensitivity level of the product, and avoid problems such as encapsulation failure. In this embodiment, a second locking groove 24 is provided on each pin of the lead frame 20, which can not only improve the surface roughness, but also increase the contact area and bonding force between the lead frame 20 and the plastic encapsulation material 60.

[0062] In this embodiment, the lead 50 is a metal lead, and the metal lead is a 0.25μm gold wire. The 0.25μm gold wire has advantages such as good electrical conductivity, stable chemical properties, and strong corrosion resistance.

[0063] The packaging structure of the quasi-monolithic power multiplier amplifier of the present utility model has good thermal matching and heat dissipation performance, solves the problem that gallium nitride devices may generate self-heating effects and cause too high device temperature in the prior art, and at the same time solves the problems of thermal matching and heat dissipation under the combined packaging of two different material chips (gallium nitride, gallium arsenide). It can give full play to the excellent performance of gallium nitride chips, and at the same time has better consistency and higher efficiency than the traditional hybrid circuit process, greatly improving the stability and reliability of the product. The packaging structure of the present utility model has lower cost than integrating all circuits on a single gallium nitride chip, and while ensuring that the product has the high power of gallium nitride devices, it can also have better heat dissipation effect than the devices packaged with a single gallium nitride chip.

[0064] As Figure 5 shown, the preparation method of the quasi-monolithic power multiplier amplifier of the present utility model includes the following steps:

[0065] Step S01: Select two gallium arsenide HEMT die chips, two gallium nitride FET die chips, a frame base island, a lead frame, a bonding material, a plastic encapsulation material, and leads;

[0066] Step S02: Place the two gallium arsenide HEMT die chips and the two gallium nitride FET die chips parallel to each other and bond them to the front of the frame base island using sintered silver glue;

[0067] Step S03: Connect the two gallium nitride FET die chips and the two gallium arsenide HEMT die chips to the pins of the lead frame through leads respectively, and connect the two gallium nitride FET die chips and the two gallium arsenide HEMT die chips to each other through leads;

[0068] Step S04: After encapsulating and cutting the two gallium nitride FET die chips, the two gallium arsenide HEMT die chips, the frame base island, the lead frame, and the leads with epoxy molding compound, a quasi-monolithic integrated gallium nitride power multiplier amplifier is formed.

[0069] The packaging structure of the quasi-monolithic power multiplier amplifier of the present utility model uses a copper-iron-phosphorus alloy with a thickness of 1-1.5 mm as the frame base island for four die chips. It not only has good electrical and thermal conductivity, but also has corrosion resistance and oxidation resistance, greatly improving the heat dissipation capacity and stability of the product. Secondly, the plastic packaging material uses an epoxy resin molding compound with low stress and a glass transition temperature Tg as high as 160 °C, with high reliability and can avoid phenomena such as delamination. Most importantly, sintered silver paste with a thermal conductivity as high as 130 W / m.k is used to replace the traditional silver paste and an appropriate curing curve is set with a high-temperature oven to sinter the chips, which not only improves the efficiency but also the yield, and at the same time greatly reduces the risk of voids in the product. The present utility model has good thermal matching and heat dissipation performance, solves the problem that gallium nitride devices may generate self-heating effects under the existing technology, thereby limiting the device performance, enables the excellent performance of gallium nitride chips to be fully exerted, and at the same time has better consistency and higher efficiency than the traditional hybrid circuit process, greatly improving the stability and reliability of the product.

[0070] The above are only examples clearly illustrating the present utility model and do not limit the patent scope of the present utility model. It is impossible to enumerate all implementation manners here. Any equivalent structural transformation made using the content in the technical solution of the present utility model under the concept of the present utility model, or direct / indirect application in other related technical fields is included in the patent protection scope of the present utility model.

Claims

1. A packaging structure of a quasi-monolithic power multiplier amplifier, characterized in that: include: Frame base island; A lead frame is arranged at the periphery of the frame base island; Four tube core chips are respectively bonded to the front side of the frame base island by bonding materials, wherein two tube core chips are connected by leads to form a common gate amplifier structure, wherein the other two tube core chips are connected by leads to form a common source amplifier structure, the four tube core chips are also connected to the lead frame by leads, and the four tube core chips together form an amplifier circuit of a push-pull structure; The plastic packaging material covers the frame base island, the lead frame, the four core chips and the leads to form a whole.

2. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 1, characterized in that: The four tube core chips include two gallium nitride FET tube core chips and two gallium arsenide HEMT tube core chips respectively. The two gallium nitride FET tube core chips form a common gate amplifier structure, and the two gallium arsenide HEMT tube core chips form a common source amplifier structure.

3. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 1 or 2, characterized in that: The bonding material is sintered silver paste.

4. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 1, characterized in that: Two gallium nitride FET tube core chips and two gallium arsenide HEMT tube core chips are placed parallel to each other on the front side of the frame base island, and the source pressure points of the two gallium nitride FET tube core chips and the drain pressure points of the two gallium arsenide HEMT tube core chips are close, and the spacing between the two tube core chips is 100-200um.

5. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 2, characterized in that: The lead frame includes a plurality of pins, and the plurality of pins include an output pin, an input pin, a bias pin, and a ground pin; The gate voltage points of the two GaAs HEMT tube core chips are connected to the input pins of the lead frame through wires, the source voltage points of the two GaAs HEMT tube core chips are connected to the ground pins of the lead frame through wires, and the drain voltage points of the two GaAs HEMT tube core chips are respectively connected to the source voltage points of the two GaN FET tube core chips through wires; The drain voltage points of the two GaN FET die chips are connected to the output pins of the lead frame through leads, and the gate voltage points of the two GaN FET die chips are connected to the bias pins of the lead frame through leads.

6. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 1, characterized in that: The frame base island is made of copper-iron-phosphorus alloy and has a thickness of 1 to 1.5 mm.

7. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 1, characterized in that: A first locking groove is arranged on the front side of the frame base island, and the lead frame is made of thin copper material and a second locking groove is arranged on the pin.

8. The packaging structure of the quasi-monolithic power multiplier amplifier according to claim 1, characterized in that: The lead wire is a metal lead wire, and the metal lead wire is a 0.25 μm gold wire.

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