Chip packaging structure and packaging body

Abstract

The utility model provides a chip packaging structure and a packaging body, the chip packaging structure comprises a chip, the chip comprises a welding area, the welding area is equally divided into N welding sub-areas along a first direction, N is a positive integer greater than or equal to 1, and each welding sub-area is provided with at least one welding spot; and at least one bonding wire, each bonding wire being connected in series with the at least one welding spot of one sub-welding area along a second direction, the second direction being perpendicular to the first direction. According to the chip packaging structure, the welding area of the chip is equally divided into the plurality of welding sub-areas along the first direction, and the welding spots are arranged in each welding sub-area, so that the distribution of the welding spots in the welding area of the chip tends to be uniform, relatively uniform resistance distribution is formed, a good shunting effect on current passing through the chip is achieved, and the reliability of the chip packaging structure is improved. And the surge capacity of the chip is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a chip packaging structure and a packaging body. Background Art

[0002] Surge current refers to the peak current that flows into electronic devices when the power is turned on or due to circuit abnormalities. This sudden change may far exceed the voltage or current range of the device during normal operation, causing damage to components in the circuit and even causing safety accidents. Poor surge performance of the chip will also have a serious impact on the chip, causing damage or performance degradation. Therefore, the maximum surge current IFSM that the chip can withstand is a key parameter that determines whether the device can be used safely. With the continuous development of electronic products, the requirements for the surge current capability of chips are getting higher and higher. Improving the surge capability of chips is an important part of improving chip safety and reliability. Utility Model Content

[0003] The technical problem to be solved by this application is how to improve the surge capability of the chip.

[0004] An embodiment of the present application provides a chip packaging structure, comprising: a chip, wherein the chip comprises a welding area, wherein the welding area is equally divided into N sub-welding areas along a first direction, where N is a positive integer greater than or equal to 1, and each of the sub-welding areas is provided with at least one welding point; and at least one bonding wire, wherein each of the bonding wires is connected in series with at least one welding point of the sub-welding area along a second direction, and the second direction is perpendicular to the first direction.

[0005] In some embodiments, the at least one welding point in at least one of the sub-welding regions is evenly arranged along the second direction.

[0006] In some embodiments, at least one of the sub-welding regions is equally divided into n sub-welding regions along the second direction, where n is a positive integer greater than or equal to 1, and each of the sub-welding regions is provided with a welding point.

[0007] In some embodiments, n is equal to 1, the sub-welding area overlaps with the sub-welding area, and the welding point is located at the center of the sub-welding area.

[0008] In some embodiments, n is greater than 1, and each welding point in the sub-welding area is located at the center of the sub-welding area.

[0009] In some embodiments, the bonding wire is electrically connected to a top metal layer of the chip through the at least one solder joint.

[0010] In some embodiments, the cross-section of the solder joint is a regular shape, and the cross-sectional size of the solder joint is 1.5 to 2 times the cross-sectional size of the bonding wire.

[0011] In some embodiments, the bond wire material includes aluminum, copper, silver, or gold.

[0012] An embodiment of the present application further provides a package body, which includes a connection carrier and one or more chip packaging structures, wherein the connection carrier is used to connect electronic components, and the bonding wires of the chip packaging structure are electrically connected to the connection carrier.

[0013] In some embodiments, the connection carrier is a terminal, a base or a lead frame.

[0014] The beneficial effects of the chip packaging structure provided by the present application include but are not limited to the following:

[0015] The chip packaging structure provided in the present application divides the chip's welding area into a number of sub-welding areas along a first direction, and sets a welding point in each sub-welding area, so that the distribution of the welding points in the chip welding area tends to be uniform, thereby forming a relatively uniform resistance distribution, which has a good shunting effect on the current passing through the chip and improves the surge capability of the chip.

[0016] Furthermore, by evenly distributing the solder joints in at least one sub-soldering area along the second direction, the solder joints connected in series on the bonding wire form evenly distributed resistance values, thereby enhancing the current flow stability and improving the surge capability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figure 1 A schematic diagram of the chip packaging structure of the present application;

[0020] Figure 2a This is a schematic diagram of an embodiment of the chip packaging structure of the present application when N=2;

[0021] Figure 2b This is a schematic diagram of another embodiment of the chip packaging structure of the present application when N=2;

[0022] Figure 3 This is a schematic diagram of an embodiment of the chip packaging structure of the present application when N=3;

[0023] Figure 4This is a schematic diagram of an embodiment of the chip packaging structure of the present application when n=1;

[0024] Figure 5a This is a schematic diagram of an embodiment of the chip packaging structure of the present application when n=2;

[0025] Figure 5b This is a schematic diagram of another embodiment of the chip packaging structure of the present application when n=2;

[0026] Figure 6 It is a schematic diagram showing that all solder joints in the chip packaging structure of the present application are evenly distributed in the soldering area. DETAILED DESCRIPTION

[0027] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0028] The chip packaging structure is a structure that encapsulates the chip and connects it to the external circuit to ensure the chip's electrical interconnection performance and mechanical stability. Wire bonding is an important part of chip packaging technology. It uses heat, pressure, ultrasonic energy, etc. to tightly weld thin metal wires to the conductive layer of the chip and the conductive layer of other components, thereby achieving electrical interconnection between the chip and the outside world. The layout design of the wire bonding structure directly affects the chip's working performance and reliability, one of the important items is the chip's surge performance.

[0029] When the bonding wire is connected to the chip through welding, traditional welding only requires the solder joint position to be on the chip, and does not require the specific position of the solder joint. However, if the same wire bonding method is used for the same product, if the solder joint position of different chips is offset, it will cause differences in surge capacity between different chips of the same product, affecting the stability of product performance.

[0030] Based on the consideration of improving the chip surge capability by optimizing the solder joint position, the present application embodiment provides a chip packaging structure, referring to Figure 1 The chip packaging structure includes: a chip 1, wherein the chip 1 includes a welding area 2, wherein the welding area 2 is equally divided into N sub-welding areas 21 along a first direction, where N is a positive integer greater than or equal to 1, and each of the sub-welding areas 21 is provided with at least one welding point 3; and at least one bonding wire 4, wherein each of the bonding wires 4 is connected in series with the at least one welding point 3 of the sub-welding area 21 along a second direction, wherein the second direction is perpendicular to the first direction.

[0031] The chip packaging structure of the present application divides the welding area 2 of the chip 1 into a plurality of sub-welding areas 21 along a first direction, and connects the welding points 3 in the sub-welding areas 21 in series through bonding wires 4, so that the distribution of the welding points 3 in the welding area 2 tends to be uniform, thereby optimizing the distribution of the welding point positions in the welding area 2, and having a good shunting effect on the instantaneous peak current passing through the chip, thereby improving the surge capability of the chip.

[0032] The chip can be various silicon-based chips or wide bandgap chips on a SiC substrate. Active devices, interlayer dielectric layers and interconnect structures on the SiC substrate can be formed in the SiC substrate. The interconnect structure includes a first interlayer metal layer, a second interlayer metal layer, an insulating layer and a top metal layer. The top metal layer is a conductor layer electrically connected to the bonding wires in the chip and can be made of metal materials such as aluminum and copper. Each bonding wire is electrically connected to the top metal layer of the chip through at least one solder joint.

[0033] The welding area is an effective welding area on the chip for connecting to the package carrier, and its position needs to accurately correspond to the position of the corresponding electrical connection area on the package carrier. The shape of the welding area can be square, circular, or designed to any shape as needed. According to the circuit layout design, the chip can be provided with one or more welding areas, and each welding area can be provided with one or more welding points. The welding points of the chip are electrically connected to the package carrier through bonding wires, and the chip is electrically interconnected with other electronic components through the package carrier.

[0034] The welding area needs to be separated from the edge of the chip and the non-welding area by a certain distance to meet the packaging requirements. The distance between the welding point and the edge of the welding area is generally greater than the diameter of the bonding wire to meet the welding process requirements.

[0035] It should be noted that there is no specific positional relationship between the first direction and the welding area described in the present application, and it is only set to illustrate the relationship between it and the second direction.

[0036] When N=1, there is only one sub-welding area 21, which overlaps with the welding area 2, and all welding points 3 are located in one sub-welding area 21. When the number of welding points 3 is one, the welding point 3 can be set at the center of the sub-welding area 21 (i.e., the welding area 2). When the number of welding points 3 is multiple, the multiple welding points 3 can be evenly arranged on the bonding wire 4.

[0037] refer to Figure 2a In the case where N=1, a welding spot 3 is set at the center of the sub-welding area 21 (welding area 2).

[0038] When N is greater than 1, the welding area 2 is evenly divided into a plurality of sub-welding areas 21 along the first direction, and N is, for example, 2, 3, 4, etc. The number of solder joints 3 in each sub-welding area 21 may be one or more, and the number of solder joints in different sub-welding areas 21 may be the same or different. Evenly dividing the welding area 2 along the first direction and setting solder joints 3 in each sub-welding area 21 can avoid the concentration of solder joints 3, and make the distribution of multiple solder joints 3 in the welding area 2 tend to be uniform, so that a relatively uniform resistance distribution is formed in the welding area 2, and the current stability of the chip packaging structure and the impact resistance of the chip to the peak current are improved. At the same time, the dispersed solder joints 3 can also avoid the short circuit caused by the adhesion of the solder joints, and improve the working reliability of the chip.

[0039] refer to Figure 2b In the case of N=2, the welding area 2 has two sub-welding areas 21, each of which has a welding spot 3, and the welding spot 3 is located at the center of the sub-welding area 21. This setting can make the coordinates of the two welding spots 3 consistent along the second direction, so that the current carrying capacity of each bonding wire 4 is also basically consistent, which can play a better shunting role for the instantaneous peak current passing through the circuit, thereby improving the surge performance of the chip.

[0040] Similarly, when N=3, 4, 5, ..., the coordinates of the welding points 3 in the plurality of sub-welding areas 21 along the second direction are consistent, so that the plurality of bonding wires 4 obtain a substantially consistent flow effect.

[0041] refer to Figure 3 This is an embodiment where N=3. In this case, there are three sub-welding areas 21 in the welding area 2 . A welding spot 3 is arranged in each sub-welding area 21 , and each welding spot 3 is located at the center of the corresponding sub-welding area 21 .

[0042] In some embodiments, there are multiple welding spots 3 in the sub-welding area 21 .

[0043] refer to Figure 4 In the case where there are two sub-welding areas 21 (ie, N=2), two welding spots 3 are disposed in each sub-welding area 21, and there are two bonding wires 4, each bonding wire 4 connects two welding spots 3 in series along the second direction.

[0044] In some embodiments, when there are multiple solder joints 3 in the sub-welding area 2, the multiple solder joints 3 are evenly arranged along the second direction. Such an arrangement can enable the multiple solder joints 3 to form a relatively stable resistance distribution on the bonding wire 4, thereby improving the current flow stability of the bonding wire 4 and improving the surge performance of the chip.

[0045] In some embodiments, the sub-welding area 21 is equally divided into n sub-welding areas 21 a (n is a positive integer greater than or equal to 1) along the second direction, and each sub-welding area 21 a is provided with a welding point 3 .

[0046] When n=1, refer to Figure 2b , the sub-welding area 21a overlaps with the sub-welding area 21. When there is one solder joint 3, the solder joint 3 can be set at the center of the sub-welding area 21a (i.e., the sub-welding area 21). When there are multiple solder joints 3, the multiple solder joints 3 can be evenly distributed along the bonding line 4.

[0047] refer to Figure 5a When n is greater than 1, each sub-welding area 21 has a plurality of sub-welding areas 21 a, and a welding point 3 is arranged in each sub-welding area 21 a. Figure 5a In the example, N=2, n=2, there are two sub-welding areas 2, each of which has two sub-welding areas 21a, each of which has a welding point 3, and the two welding points 3 in the same sub-welding area 2 are connected in series on the same bonding wire 4, and there are two bonding wires 4. It can be understood that the two welding points 3 on the same bonding wire 4 can be stitched by jumper wires.

[0048] refer to Figure 5b , the solder joint 3 in each sub-welding area 21a is arranged at the center position of the sub-welding area 21a, so that the uniformity of distribution of the multiple solder joints 3 in the same sub-welding area 21 in the second direction (i.e., on the bonding wire 4) can be ensured, so that the multiple solder joints 3 on the bonding wire 4 form a uniform resistance distribution. At the same time, the number of solder joints 3 on each bonding wire 4 is the same, so that the current-carrying performance of the two bonding wires 4 is close, thereby having a better current shunting effect.

[0049] In some embodiments, all solder joints in the chip soldering area 2 are evenly distributed in the N sub-soldering areas 21, that is, the same number of solder joints 3 are arranged in each sub-soldering area 21. Figure 6 In the case where N=3 and n=2, the welding area 2 is equally divided into three sub-welding areas 21 along the first direction, and each sub-welding area 21 is equally divided into two sub-welding areas 21a along the second direction. Each sub-welding area 21a is provided with a welding point, that is, six welding points are required on the chip surface, and one bonding wire 4 is connected in series to two welding points 3 in the sub-welding area 21, with a total of three bonding wires 4, and the center positions of the six welding points are respectively located at the center of the six sub-welding areas 21a.

[0050] From the perspective of the entire welding area 2, since all the welding points 3 are evenly distributed in the welding area 2, a relatively even resistance distribution is formed in the entire welding area 2, avoiding the existence of local weak areas, which is more conducive to the passage of large currents, and thus can well improve the surge capacity of the welding area 2. At the same time, this arrangement also makes the layout of multiple welding points 3 in the welding area 2 more reasonable, the area of ​​the welding area 2 is effectively utilized, and the dispersed welding points 3 can improve the operability of the welding process, help improve the welding quality of the chip, reduce the failure rate of the chip during operation, and improve the reliability of the chip.

[0051] It should be noted that not all solder joints 3 in the sub-welding area 2 need to be evenly arranged along the second direction or all solder joints 3 need to be located at the center of the sub-welding area 21a in order to achieve the purpose of improving the chip surge performance. The uniform arrangement of the solder joints 3 in some sub-welding areas 2 or the arrangement of some solder joints 3 at the center of the sub-welding area 21a can improve the chip surge capability to a certain extent.

[0052] In addition, the welding quality of the solder joints will also directly affect the surge capacity of the chip. Compared with solder joints with random shapes, solder joints with regular shapes, uniform solder, and smooth surfaces can make the electrical contact of the chip packaging structure better and the mechanical contact more secure, effectively avoiding loose soldering, cold soldering, and looseness during use, and maintaining a stable resistance value at the solder joints, thereby improving the surge capacity and reliability of the chip.

[0053] The shape of the solder joint can be rectangular, square, circular, elliptical, etc. The size of the solder joint 3 is related to the diameter of the bonding wire. In some embodiments, the length dimension of the solder joint cross section is 1 to 5 times the diameter of the bonding wire, and the width dimension is 1 to 3 times the diameter of the bonding wire.

[0054] The materials of the bonding wire include but are not limited to aluminum, copper, silver and gold, and alloy materials can also be used. The bonding wire is welded by aluminum wire through a cold welding process, which is easy to ensure welding quality and can reduce welding costs. When a 15 mil diameter aluminum wire is used for welding, the solder joint can be a regular rectangle, and the size of the rectangle is generally: 15 to 45 mil long and 15 to 30 mil wide.

[0055] The IFSM capability of a chip is generally evaluated through surge testing, which injects controlled transient voltage and current into the chip to simulate overvoltage and overcurrent conditions that may occur under actual usage conditions to evaluate the tolerance of electronic equipment.

[0056] Take the jumper with 2*12mil stitch as an example, without optimizing the solder joint position, after the IFSM surge capability test, the test results are shown in Table 1.

[0057] Table 1

[0058] Surge current(A) 170 180 190 200 210 Test Results pass pass pass pass Invalidation

[0059] After optimizing the solder joint position using the chip packaging structure of the present application, the IFSM surge capability test was performed, and the test results are shown in Table 2.

[0060] Table 2

[0061] Surge current(A) 180 190 200 210 220 Test Results pass pass pass pass Invalidation

[0062] It can be seen that before optimizing the solder joint, the maximum surge current that the jumper can withstand is 200A. By optimizing the solder joint position, the maximum surge current that the jumper can withstand is 210A, and its IFSM can be improved by about 5%.

[0063] An embodiment of the present application further provides a package body, which includes a connection carrier and one or more chip packaging structures described in the present application, wherein the connection carrier is used to connect electronic components, and the bonding wires of the chip packaging structure are electrically connected to the connection carrier.

[0064] Wherein, the connection carrier can be a terminal, a base or a lead frame. The base is a PCB board, and the PCB board can be a single-sided board, a double-sided board, a multi-layer board or an HDI board (high-density interconnect board). The bonding wire of the chip packaging structure is connected to the conductive layer of the PCB board. The lead frame includes a pad and a pin, and the bonding wire of the chip packaging structure is electrically connected to the lead frame through the pin, or the bonding wire can be directly connected to the pad.

[0065] In some embodiments, the bonding wires of the chip packaging structure are connected to a lead frame or a terminal or a base or other board and then connected as a whole to other substrate baseplates. The other board and substrate baseplates may be ceramic boards. Ceramic boards have excellent thermal stability and high thermal conductivity, and their types include DBC substrates, AMB substrates, PBC substrates, DPC substrates, and the like.

[0066] The electronic components may be resistors, capacitors, inductors, etc.

[0067] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects that may be produced may be any one or a combination of the above, or any other beneficial effects that may be obtained.

[0068] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of this specification. Although not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to this application. Such modifications, improvements and corrections are suggested in this specification, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of this application.

[0069] It should be noted that in the description of this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", and "fix" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a rotating connection or a sliding connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood in combination with specific circumstances.

[0070] In addition, when terms such as "first", "second", and "third" are used in the specification of this application to describe various features, these terms are only used to distinguish these features and cannot be understood as indicating or implying the relationship between the features, the relative importance, or implicitly indicating the number of features indicated.

[0071] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device nor to limit the scope of the exemplary embodiments.

[0072] At the same time, the present application uses specific words to describe the embodiments of this specification. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in the present application does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0073] Similarly, it should be noted that in order to simplify the description disclosed in this application and thus help understand one or more embodiments, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0074] Finally, it should be understood that the embodiments described in this application are only used to illustrate the principles of the embodiments of the present application. Other variations may also fall within the scope of the present application. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present application may be considered to be consistent with the teachings of the present application. Accordingly, the embodiments of the present application are not limited to the embodiments explicitly introduced and described in the present application.

Claims

1. A chip packaging structure, characterized in that: include: A chip, the chip comprising a welding area, the welding area being equally divided into N sub-welding areas along a first direction, N being a positive integer greater than or equal to 1, and each of the sub-welding areas being provided with at least one welding point; At least one bonding wire, each of which is connected in series to at least one welding spot of the sub-welding area along a second direction, wherein the second direction is perpendicular to the first direction.

2. The chip packaging structure according to claim 1, characterized in that: The at least one welding spot in at least one of the sub-welding areas is evenly arranged along the second direction.

3. The chip packaging structure according to claim 2, characterized in that: At least one of the sub-welding areas is equally divided into n sub-welding areas along the second direction, where n is a positive integer greater than or equal to 1, and each of the sub-welding areas is provided with a welding point.

4. The chip packaging structure according to claim 3, characterized in that: n is equal to 1, the sub-welding area overlaps with the sub-welding area, and the welding point is located at the center of the sub-welding area.

5. The chip packaging structure according to claim 3, characterized in that: n is greater than 1, and each welding point in the sub-welding area is located at the center of the sub-welding area.

6. The chip packaging structure according to claim 1, characterized in that: The bonding wire is electrically connected to the top metal layer of the chip through the at least one solder joint.

7. The chip packaging structure according to claim 1, characterized in that: The cross section of the solder joint is a regular shape, the length dimension of the cross section is 1 to 5 times the diameter of the bonding wire, and the width dimension of the cross section is 1 to 3 times the diameter of the bonding wire.

8. The chip packaging structure according to claim 1, characterized in that: The bonding wire material includes aluminum, copper, silver or gold.

9. A package, characterized in that: The package body comprises a connection carrier and one or more chip packaging structures according to any one of claims 1 to 8, the connection carrier is used to connect electronic components, and the bonding wires of the chip packaging structure are electrically connected to the connection carrier.

10. The package according to claim 9, characterized in that: The connection carrier is a terminal, a base or a lead frame.

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