Semiconductor device

Abstract

A semiconductor device includes a channel region on a substrate and a source / drain (S / D) feature adjacent to the channel region. The semiconductor device includes a gate structure over a channel region, a first interlayer dielectric (ILD) layer over the gate structure, an etch stop layer over the first ILD layer, and a second ILD layer over the etch stop layer. A tungsten S / D contact is disposed over the S / D feature and surrounded by a first ILD layer. Tungsten S / D vias fall on the S / D contacts and are surrounded by a second ILD layer. A tungsten gate via falls on the gate structure and is surrounded by the first ILD layer and the second ILD layer. The tungsten gate via includes one or more air gaps.

Description

Technical Field

[0001] The embodiment of the utility model relates to a semiconductor device, in particular to a semiconductor device with metal contacts and through holes of an all-tungsten solution. Background Art

[0002] The integrated circuit (IC) industry has grown exponentially. Advances in semiconductor manufacturing technology have resulted in multiple IC generations, each with smaller and more complex circuits than the previous IC generation. During IC evolution, functional density (i.e., the number of connected IC devices per chip area) generally increases, while geometry (i.e., the area and / or size of IC features and / or the spacing between these IC features) decreases. Generally speaking, scaling is limited only by the ability to lithographically define IC features at ever-decreasing geometries.

[0003] However, as feature sizes continue to decrease, metal contacts and / or vias need to fit into smaller spaces while minimizing contact resistance. Fitting metal materials into smaller spaces typically creates seams or voids, which compromise electrical connections. Undesirable seams may be formed when forming source / drain contacts and source / drain vias (which are then connected to upper interconnects and metal lines). The same problem may occur when forming gate vias on top of metal gates. In order to avoid voids and minimize contact resistance, existing methods for forming low-resistance metal contacts and / or vias are costly (e.g., requiring expensive wet cleaning chemicals, process sequence tightening, and interface engineering). Therefore, there is a need to optimize and balance performance and cost; achieving low resistance in metal filling schemes while still simplifying the process.

[0004] Thus, while existing methods of forming semiconductor metal contacts and vias have generally been adequate for their intended purposes, they have not been satisfactory in every aspect. Utility Model Content

[0005] The present disclosure provides a semiconductor device. The semiconductor device includes a channel region, a source / drain feature, a gate structure, a first interlayer dielectric layer, an etch stop layer, a second interlayer dielectric layer, a tungsten source / drain contact, a tungsten source / drain via, and a tungsten gate via. The channel region is on a substrate. The source / drain feature is adjacent to the channel region. The gate structure is above the channel region. The first interlayer dielectric layer is above the gate structure. The etch stop layer is above the first interlayer dielectric layer. The second interlayer dielectric layer is above the etch stop layer. The tungsten source / drain contact is above the source / drain feature and is surrounded by the first interlayer dielectric layer. The tungsten source / drain via falls on the tungsten source / drain contact and is surrounded by the second interlayer dielectric layer. The tungsten gate via falls on the gate structure and is surrounded by the first interlayer dielectric layer and the second interlayer dielectric layer. The tungsten gate via includes one or more air gaps.

[0006] In some embodiments, the tungsten source / drain vias are also located on a top surface of the first interlayer dielectric layer.

[0007] In some embodiments, the tungsten source / drain contact has a first width, and the first width is smaller than a second width of the tungsten source / drain via.

[0008] In some embodiments, the channel region includes a stack of a plurality of channel layers; and each of the channel layers is surrounded by the gate structure.

[0009] In some embodiments, a bottom surface and sidewall surfaces of the tungsten gate via are lined with a tungsten seed layer, and the tungsten seed layer has a metal conductivity greater than that of the tungsten gate via.

[0010] In some embodiments, the semiconductor device further comprises: a silicide feature above the source / drain feature.

[0011] In some embodiments, the semiconductor device further comprises: a tungsten seed layer above the silicide feature, wherein the tungsten source / drain contacts directly contact the tungsten seed layer.

[0012] In some embodiments, the tungsten source / drain contacts directly contact the first interlayer dielectric layer.

[0013] In some embodiments, the etching stop layer is a first etching stop layer, and the semiconductor device further includes: a gate spacer on a sidewall of the gate structure; and a second etching stop layer on a sidewall of the gate spacer.

[0014] In some embodiments, the first interlayer dielectric layer separates the tungsten source / drain contacts from the second etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments of the present disclosure may be understood in more detail by reading the following detailed description and examples in conjunction with the corresponding drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale. In fact, for the sake of clarity, the sizes of the various features may be increased or decreased at will. It should also be noted that the drawings only show typical embodiments of the present disclosure and should not be considered as limiting the scope, as the present disclosure may also be applicable to other embodiments.

[0016] Figure 1A and Figure 1B A flow chart of a method of manufacturing partial or full metal contacts and vias is shown according to various aspects of the present disclosure.

[0017] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 ,as well as Fig. 20 According to the embodiment of the present disclosure, Figure 1A and Figure 1B A method of manufacturing a semiconductor device at an intermediate station in the process is provided.

[0018] Fig.21 According to another embodiment of the present disclosure, Figure 1A and Figure 1B A cross-sectional view of a semiconductor device processed by the method.

[0019] The reference numerals are described as follows:

[0020] 100: Methods

[0021] 102~132: Operation

[0022] 200: Semiconductor devices and equipment

[0023] 202: Substrate

[0024] 206: Active Zone

[0025] 206a: Passage area

[0026] 206b: Source / drain region

[0027] 208: Metal Gate Stack

[0028] 209: Gate spacer

[0029] 210: Metal gate structure

[0030] 212: Etch stop layer

[0031] 250: Artifacts

[0032] 302: First interlayer dielectric layer

[0033] 306: Source / drain trench

[0034] 308: Silicide Characteristics

[0035] 310: First tungsten seed layer

[0036] 312: Sacrificial Layer

[0037] 316: Tungsten source / drain contacts, source / drain contacts

[0038] 317: Compliant conductive barrier layer, barrier layer

[0039] 319: Overloaded Metal

[0040] h1: height

[0041] h2: height

[0042] h3: Chemical mechanical polishing surface height, height

[0043] 402: Second interlayer dielectric layer

[0044] 412: Etch stop layer

[0045] 406: Source / drain via trench

[0046] 416: Tungsten source / drain vias, source / drain vias

[0047] 417: Compliant conductive barrier layer, barrier layer

[0048] 419: Overloaded Metal

[0049] h4: height

[0050] h5: height

[0051] h6: Chemical mechanical polishing surface height, height

[0052] d1: width

[0053] d2: width

[0054] 408: Gate via trench

[0055] 410: Second tungsten seed layer

[0056] 505: Void

[0057] 516: Tungsten gate via, gate via

[0058] 207: Channel layer

[0059] 211: Internal spacer DETAILED DESCRIPTION

[0060] The present disclosure relates generally to integrated circuit (IC) semiconductor devices, and more particularly to device-level metal contacts and vias in IC semiconductor devices.

[0061] The present disclosure provides many different embodiments or examples to implement the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and it may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact.

[0062] In addition, the following different embodiments of the present disclosure may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed. In addition, the formation of a feature on another feature, the formation of a feature connected to another feature, and / or the formation of a feature coupled to another feature in the subsequent present disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features can be formed to insert features so that the features may not be in direct contact.

[0063] In addition, spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate description of the relationship between one element or feature and another element or features in the diagram. In addition to the orientation shown in the drawings, these spatially related terms are intended to include different orientations of the device in use or operation. In addition, the device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may also be interpreted in the same manner.

[0064] In addition, when a number or a numerical range is described with "about", "approximately", etc., the term is intended to encompass numbers within a reasonable range including the stated number, such as values ​​within + / -10% or other values ​​understood by a person of ordinary skill in the art. For example, the term "about 5 nm" includes a size range of 4.5 nm to 5.5 nm.

[0065] The present disclosure relates to metal contacts and vias that are physically and electrically connected to upper interconnects and metal lines. The metal contacts include source / drain (S / D) contacts formed above S / D epitaxial features. The metal vias include S / D vias formed above the S / D contacts and gate vias formed above the metal gate. A full tungsten metal filling scheme for forming S / D contacts and S / D vias is proposed. This allows for a uniform interface and excellent growth uniformity. In addition, when the S / D vias and S / D contacts are formed without voids by selective tungsten bottom-up metal growth, the contact resistance of the S / D vias and S / D contacts is reduced. The gate vias also utilize an all-tungsten scheme by using a physical vapor deposition (PVD) tungsten liner and then forming the gate vias by growing isotropic tungsten metal above the liner. Although each isotropic metal growth may produce one or more voids in the gate via, device performance is not affected due to the all-tungsten gate via scheme and the wider gate via process window. In addition, isotropic metal growth is a cheaper process, thus simplifying manufacturing operations.

[0066] The all-tungsten contact scheme for S / D contacts, S / D vias, and gate vias facilitates overall process integration, improved defect / process control, tool capacity, and usage. To illustrate various aspects of the all-tungsten contact scheme in the present disclosure, a method for forming a semiconductor device is discussed below. The embodiments shown in the present disclosure are implemented using FinFETs, but the present disclosure is not limited to this. Those with ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. For example, the present disclosure can be implemented using a wrap-around gate FET, such as a nanosheet FET or a nanowire FET.

[0067] Figure 1A and Figure 1BA flow chart of a method 100 for fabricating partial or full metal contacts and vias is shown according to various aspects of the present disclosure. The method 100 is briefly described below. At operation 102, the method 100 receives or is provided with a workpiece, the workpiece including a gate structure above a channel region on a substrate. The channel region can be a channel region for a fin FET, a nanowire or nanosheet FET, or other types of multi-gate FETs. The channel region can be a portion of an active region protruding from the substrate. Adjacent to the channel region is an S / D region having S / D features. At operation 104, the method 100 deposits a first interlayer dielectric (ILD) layer above the gate structure and above the S / D features. At operation 106, the method 100 forms an S / D trench through the first ILD layer, the S / D trench exposing a top surface of the S / D feature. At operation 108, the method 100 forms a silicide feature above the S / D feature. At operation 110, the method 100 forms a first tungsten seed layer above the silicide feature by physical vapor deposition (PVD). At operation 112, the method 100 removes a top portion of the first tungsten seed layer by a first removal process. At operation 114, the method 100 removes a side portion of the first tungsten seed layer by a second removal process. At operation 116, the method 100 forms a tungsten S / D contact by growing tungsten over the remaining portion of the first tungsten seed layer by selective bottom-up metal growth. At operation 118, the method 100 performs a first planarization process such that a top surface of the tungsten S / D contact is coplanar with the first ILD layer. At operation 120, the method 100 deposits a second ILD layer over the tungsten S / D contact and over the first ILD layer. At operation 122, the method 100 forms an S / D via trench through the second ILD layer, the S / D via trench exposing a top surface of the tungsten S / D contact. At operation 124, the method 100 forms a tungsten S / D via over the tungsten S / D contact by selective bottom-up metal growth. At operation 126, the method 100 performs a second planarization process so that the top surface of the tungsten S / D via is flush with the second ILD layer. At operation 128, the method 100 forms a gate via trench through the first and second ILD layers, the gate via trench exposing the top surface of the gate structure. At operation 130, the method 100 forms a second tungsten seed layer in the gate via trench by PVD. At operation 132, the method 100 forms a tungsten gate via by growing tungsten on the second tungsten seed layer by chemical vapor deposition (CVD) isotropic metal growth.

[0068] Method 100 may perform further operations to complete the fabrication of the semiconductor device. The present disclosure contemplates additional processes. Additional operations may be provided before, during, and after method 100, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 100. Embodiments of method 100 may be applied to SRAM devices, logic devices, and other devices, particularly when the resistance of metal contacts and vias is a concern. Embodiments of method 100 may be easily integrated into existing manufacturing flows to simplify the process while improving device performance.

[0069] Combine the following Figures 2 to 20 Further describing the method 100, Figures 2 to 20 A cross-sectional view of a semiconductor device 200 is shown at an intermediate point in the manufacturing and processing according to an embodiment of the present disclosure. For clarity, Figures 2 to 20It has been simplified to better understand the concepts of the present disclosure. Additional features may be added to the device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the device 200. The device 200 may be part of an integrated circuit (IC) chip, a system on chip (SoC), or a portion thereof, which includes passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), fin field effect transistors (FinFETs), nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device 200 is included in a non-volatile memory, such as a non-volatile random access memory (NVRAM), a flash memory, an electrically erasable programmable read only memory (EEPROM), an electrically erasable programmable read-only memory (EPROM), other suitable memory types, or combinations thereof.

[0070] Now refer to Figure 2At operation 102, the method 100 receives a workpiece 250 of the device 200. The workpiece 250 may include a substrate 202 and an active region 206 above the substrate 202. The substrate 202 may be a silicon (Si) substrate, or a substrate having other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The active region 206 may be an extension of the substrate 202 protruding from the substrate 202. The active region 206 extends longitudinally along the x-direction and includes a channel region 206a below the metal gate structure 210 and an S / D region 206b between the channel region 206a.

[0071] The S / D region 206b includes S / D features epitaxially grown from the substrate 202 and / or the channel region 206a. The S / D features may include N-type S / D features corresponding to the N-type transistor region or P-type S / D features corresponding to the P-type transistor region. The S / D features may be formed by an epitaxial process using CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial growth, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the components of the substrate 202 and / or the channel region 206a. In some embodiments, for N-type transistors, the epitaxial S / D features include silicon and may be doped with carbon, phosphorus, arsenic, other N-type dopants, or combinations thereof (e.g., forming Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial S / D features). In some embodiments, for P-type transistors, the epitaxial source / drain features include silicon germanium or germanium and may be doped with boron, other P-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain features).

[0072] Each metal gate structure 210 extends longitudinally along the y-direction above one or more channel regions 206a of one or more active regions 206. Each metal gate structure 210 includes a metal gate stack 208 and a gate spacer 209 along the sidewalls of the metal gate stack 208. The gate spacer 209 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k material, and / or other suitable dielectric materials. Figure 2 A single layer of gate spacers 209 on the sidewalls of the metal gate stack 208 is shown, but the disclosure is not limited thereto. For example, the gate spacers 209 may be multi-layered, and each layer may have a different material for specific design considerations (eg, etch protection and isolation).

[0073] Each metal gate stack 208 includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer wraps around the bottom surface and the side surface of the gate electrode. In some embodiments, the gate dielectric layer includes an interface layer and a high-k dielectric layer disposed on the interface layer. The gate electrode can be formed by any suitable deposition process, such as atomic layer deposition (ALD), CVD, PVD, high-density plasma CVD (HDP-CVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (ACVD), etc. Pressure CVD; APCVD), spin coating, electroplating, other deposition processes or combinations thereof. The gate electrode may include one or more conductive materials, such as a work function metal layer, a metal fill layer and / or other suitable conductive material layer. The gate electrode may include one or more conductive materials, such as a work function metal layer, a metal fill layer and / or other suitable conductive material layer. The work function layer (if present) may be the same or different, and may be an N-type work function layer or a P-type work function layer. The gate dielectric layer includes a high-k dielectric material, such as a material with a dielectric constant greater than silicon oxide (k≈3.9). Each gate electrode includes a suitable conductive material, such as aluminum (Al), tungsten (W), cobalt (Co) and / or copper (Cu). Each gate electrode may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials or combinations thereof. In the FinFET structure, the metal gate stack 208 covers the top and side surfaces of the fin-shaped channel in the channel region 206a. In the GAA FET structure, the metal gate stack 208 completely surrounds the vertically stacked transistor channel in the channel region 206a (see Fig.21 In either case, metal gate stack 208 includes a portion disposed directly on and over channel region 206a.

[0074] In some embodiments, the workpiece 250 further includes an etch stop layer 212 along the sidewalls of the metal gate structure 210. For example, the etch stop layer 212 can be disposed adjacent to the gate spacer 209. The etch stop layer 212 can be a different material composition than the gate spacer 209. The etch stop layer 212 can include silicon nitride, silicon oxynitride, or other suitable materials.

[0075] Now refer to Figure 3 At operation 104, the method 100 deposits a first interlayer dielectric (ILD) layer 302 over the metal gate structure 210 and over the S / D features in the S / D region 206b. The first ILD layer 302 may directly contact the top surfaces of the gate spacers 209, the metal gate stack 208, the etch stop layer 212, and the S / D features in the S / D region 206b. The first ILD layer 302 fills the space between adjacent metal gate structures 210 and may directly contact the side surface of the etch stop layer 212. The first ILD layer 302 may be formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof. In some embodiments, the first ILD layer 302 is formed by a flowable CVD (FCVD) process, which includes depositing a flowable material (e.g., a liquid compound) above the device 200 and converting the flowable material into a solid material by a suitable technique, such as thermal annealing and / or ultraviolet radiation treatment. The first ILD layer 302 includes a dielectric material, the dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Example low-k dielectric materials include fluoride-doped silicate glass (FSG), carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), Xerogel, Aerogel, Amorphous fluorinated carbon, Parylene, Benzocyclobutene (BCB), (The Dow Chemical Company, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In the present embodiment, for the purpose of etchant selectivity, the first ILD layer 302 may have a different material composition than the etch stop layer 212 and the gate spacer 209. For example, in the case where the etch stop layer 212 includes silicon nitride or silicon oxynitride, the gate spacer 209 may include silicon oxide, and the first ILD layer 302 may include an oxide formed of TEOS.

[0076] Now refer to Figure 4 At operation 106, the method 100 forms an S / D trench 306 through the first ILD layer 302 and between the metal gate structures 210. The S / D trench 306 exposes the top surface of the S / D feature in the S / D region 206b. Figure 4 As shown, the S / D trench 306 is formed so that a thin layer of the first ILD layer 302 remains on the side surface of the etch stop layer 212. In other embodiments, the S / D trench 306 is formed so that the side surface of the etch stop layer 212 is partially or completely exposed. The S / D trench 306 can be formed by an etching process, such as a dry etching process, a wet etching process, other suitable etching processes or combinations thereof. In one embodiment, a lithography process is performed to form a patterned mask layer covering the metal gate structure 210, and when the S / D trench 306 is formed, the etching process uses the patterned mask layer as an etching mask.

[0077] Now refer to Figure 5, at operation 108, the method 100 forms a silicide feature 308 over the S / D feature in the S / D region 206b. In some embodiments, the silicide feature 308 may also be formed on a side portion of each S / D trench 306 (not shown). The silicide feature 308 may include a titanium silicide (TiSi) layer. In other embodiments, the silicide feature 308 may include cobalt silicide (CoSi), ruthenium silicide (RuSi), nickel silicide (NiSi), TiSiGe, CoSiGe, RuSiGe, NiSiGe, other suitable silicides, or combinations thereof. Different materials may be used depending on the application. In one example, titanium silicide is used for N-type transistors, and cobalt silicide is used for P-type transistors. The silicide feature 308 may be formed by any suitable method. For example, a metal layer (e.g., titanium) may be deposited over the device 200 by a deposition process, such as CVD, ALD, PVD, other suitable processes, or combinations thereof. Next, the device 200 is annealed to allow the metal layer and the semiconductor material of the S / D features to react and form the silicide features 308. Thereafter, the unreacted metal layer is removed, leaving the silicide features 308 as a layer above the top surface of the S / D features. In another embodiment, the metal silicide layer is directly and conformally deposited over the device 200 and into the S / D trenches 306. Thereafter, as part of the first and second removal processes in operations 112 and 114 described below, the side portions of the metal silicide layer are removed. In this case, the remaining portions of the metal silicide layer become the silicide features 308.

[0078] Reference Figure 6 At operation 110, the method 100 forms a first tungsten seed layer 310 over the silicide features 308 by physical vapor deposition (PVD). The first tungsten seed layer 310 is conformally formed over a top surface of the first ILD layer 302, a top surface of the silicide features 308, and a side surface of the first ILD layer 302. In other words, a bottom portion of the first tungsten seed layer 310 lands directly on each silicide feature 308, and a side portion of the first tungsten seed layer 310 lands directly on a side portion of each S / D trench 306. In embodiments where the metal silicide is directly and conformally deposited over the device 200, a side portion of the first tungsten seed layer 310 lands directly on a side portion of the silicide feature 308 (not shown).

[0079] The first tungsten seed layer 310 is formed using PVD rather than CVD or other deposition processes because a pure metal precursor layer is desired. In order to achieve low resistance seamless fill, tungsten is also selected for subsequent bottom-up metal growth of a single grain or less grain boundary interface. The first tungsten seed layer 310 can have a dual function. First, the first tungsten seed layer 310 acts as a PVD metal cap layer to protect the silicide feature 308. The silicide feature 308 can be exposed to the atmosphere or other oxygen-containing air when it is formed. Therefore, there is a risk that the silicide feature 308 is oxidized, which will increase its resistance. Therefore, the first tungsten seed layer (or PVD cap layer) 310 should be thick enough to act as a lid to prevent undesired silicide oxidation. Secondly, the first tungsten seed layer 310 acts as a suitable landing land for subsequent selective bottom-up metal growth. As such, no barrier layer or adhesion layer (e.g., made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN)) is formed over the silicide feature 308. This helps to reduce the resistivity because the first tungsten seed layer 310 has a lower resistivity than the barrier layer or adhesion layer.

[0080] Because the first tungsten seed layer 310 is formed to prepare for subsequent bottom-up metal growth, the side portions of the first tungsten seed layer 310 will be removed. This is to allow directional vertical growth from the bottom portion of the first tungsten seed layer 310, rather than horizontal growth from the side portions of the first tungsten seed layer 310. Because the growth is directional in the vertical direction (i.e., there is no growth in the horizontal direction), the metal fill formed has no voids. To achieve this, the top and side portions of the first tungsten seed layer 310 are removed in operations 112 and 114 to prepare for subsequent bottom-up metal growth.

[0081] Reference Figures 7 to 9 At operation 112, the method 100 removes a top portion of the first tungsten seed layer 310 by a first removal process. Figure 7 , the first removal process includes first depositing a sacrificial layer 312 in the S / D trench 306 and above the first tungsten seed layer 310. The sacrificial layer 312 will be removed later and can be a bottom anti-reflective coating (BARC) layer. The BARC layer is formed by spin coating, which is a cheaper process than CVD or PVD. Now refer to Figure 8, the first removal process includes partially etching the sacrificial layer 312 to expose the top portion of the first tungsten seed layer 310. The top portion of the first tungsten seed layer 310 includes portions on the top and side surfaces of the first ILD layer 302. Since the sacrificial layer 312 is only partially etched, the lower portion of the first tungsten seed layer 310 remains covered. Now referring to Fig. 9 , the first removal process includes etching away the exposed top portion of the first tungsten seed layer 310 by using the sacrificial layer 312 as an etch stop film.

[0082] Reference Fig.10 At operation 114, the method 100 removes the remaining side portions of the first tungsten seed layer 310 by a second removal process. The second removal process includes etching the sacrificial layer 312 to expose additional side portions of the first tungsten seed layer 310, and then etching additional side portions of the first tungsten seed layer 310. This process may be repeated until only a bottom portion of the first tungsten seed layer 310 remains on the silicide feature 308.

[0083] In an embodiment where the metal silicide is deposited directly and conformally above the device 200, the top and side portions of the metal silicide are removed in the same process that removes the top and side portions of the first tungsten seed layer 310 (i.e., during the first and second removal processes). In another embodiment, instead of the first and second removal processes that etch the sacrificial layer 312 and the first tungsten seed layer 310 individually, the sacrificial layer 312 and the first tungsten seed layer 310 may be etched together by a controlled etching process. In either case, only the bottom portion of the first tungsten seed layer 310 remains. In one embodiment, the bottom portion of the first tungsten seed layer 310 has a thickness in the range of 3 to 10 nm and has a top surface that is substantially lower than the top surface of the metal gate structure 210.

[0084] Reference Fig.11 , at operation 116, the method 100 forms a tungsten S / D contact 316 by growing tungsten over the remaining portion of the first tungsten seed layer 310. Growing tungsten on tungsten can achieve good interface contact and single grain boundaries, thereby reducing contact resistance. This is achieved by bottom-up deposition, also known as selective bottom-up metal growth. Bottom-up deposition can be performed by a suitable method, such as CVD or ALD. This deposition is isotropic and directional in the vertical direction. In the embodiment shown, the tungsten S / D contact 316 grows to a height h2 that is less than height h1. The height h1 is the height of the first ILD layer 302. Because bottom-up deposition can be more time-consuming and expensive than other methods, the tungsten S / D contacts 316 are only grown until they are above the subsequent chemical-mechanical polishing (CMP) surface height h3 (see Fig.12). In addition, because bottom-up deposition is directional, growing the S / D contact 316 above the top surface of the first ILD layer 302 may create an undesirable bump for subsequent CMP processes. As such, the S / D contact 316 does not grow above height h1. At this process station, the top surface of the S / D contact 316 is lower than the top surface of the first ILD layer 302.

[0085] Still refer to Fig.11 After forming the S / D contact 316 or as part of forming the S / D contact 316, operation 116 includes forming a compliant conductive barrier layer 317 over the S / D contact 316 and over the top and side surfaces of the first ILD layer 302. Operation 116 further includes forming an over-burden metal 319 over the compliant conductive barrier layer 317 and overfilling the S / D trench 306. The barrier layer 317 acts as an adhesion layer between the S / D contact 316 and the over-burden metal 319. The barrier layer 317 may have a material composition different from tungsten, and it is prepared for the subsequent formation of the over-burden metal 319. In one embodiment, the barrier layer 317 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). In another embodiment, the barrier layer 317 may include tungsten. The overload metal 319 is formed by isotropic chemical vapor deposition (CVD), which is a faster and cheaper metal growth process compared to selective bottom-up growth. In addition, because the growth is isotropic and formed over the compliant conductive barrier layer 317, it produces a more uniform top surface when it is formed over the first ILD layer 302. This is required to prepare for the subsequent CMP process. In one embodiment, the overload metal 319 may include tungsten. In other embodiments, the overload metal 319 may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tantalum (Ta), or molybdenum (Mo).

[0086] Now refer to Fig.12 At operation 118, the method 100 performs a first planarization process so that the top surface of the tungsten S / D contact 316 is flush with the top surface of the first ILD layer 302. The first planarization process may be a CMP process, and the first planarization process removes the compliant conductive barrier layer 317 and the overload metal 319. The first planarization process planarizes the first ILD layer 302 and the tungsten S / D contact 316 to a height h3 that is lower than the height h2.

[0087] Reference Fig.13At operation 120, the method 100 deposits a second ILD layer 402 over the tungsten S / D contacts 316 and over the first ILD layer 302. As part of or prior to operation 120, the method 100 first deposits a contact etch stop layer (CESL) 412 over the planarized surfaces of the first ILD layer 302 and the tungsten S / D contacts 316. Thereafter, the second ILD layer 402 is formed over the CESL 412. The CESL 412 may be similar in composition to the etch stop layer 212, and the second ILD layer 402 may be similar in composition to the first ILD layer 302.

[0088] Reference Fig.14 At operation 122, the method 100 forms an S / D via trench 406 through the second ILD layer 402 and the CESL 412. The S / D via trench 406 exposes the top surface of the tungsten S / D contact 316. In one embodiment, the S / D via trench 406 also exposes the top surface of the first ILD layer 302. For example, as shown in the figure, the S / D via trench 406 is formed to be wider than the S / D trench 306 in the x-direction, thereby exposing the first ILD layer 302. This is to ensure complete and correct contact between the S / D via 416 and the S / D contact 316 formed later, thereby reducing contact resistance. The S / D via trench 406 can be formed by an etching process, such as a dry etching process, a wet etching process, other suitable etching processes or combinations thereof. In one embodiment, the etching process is a multi-step etching process. For example, the etching process can include alternative etchants to remove the second ILD layer 402 and the CESL 412 separately and alternately. In one embodiment, a photolithography process is performed to form a patterned mask layer, and an etching process uses the patterned mask layer as an etching mask when forming the S / D via trenches 406 .

[0089] Reference Fig.15, at operation 124, the method 100 forms a tungsten S / D via 416 by growing tungsten over the exposed top surface of the tungsten S / D contact 316. Similar to how the tungsten S / D contact 316 is formed, the growth of the tungsten S / D via 416 is achieved by bottom-up deposition (also referred to as selective bottom-up metal growth). Notably, there is no need to form an additional tungsten seed layer by PVD, and the S / D via 416 can be grown directly from the S / D contact 316. This is because the tungsten S / D contact 316 itself is a suitable seed layer for subsequent tungsten growth. And similar to the interface between the first tungsten seed layer 310 and the tungsten S / D contact 316, here, growing the tungsten S / D via 416 on the tungsten S / D contact 316 allows for good interface contact and single grain boundaries, thereby reducing contact resistance. The bottom-up deposition can be performed by a suitable method, such as CVD or ALD. This deposition is isotropic and directional in the vertical direction. In the illustrated embodiment, the tungsten S / D vias 416 are grown to a height h5 that is lower than the height h4. The height h4 is the height of the second ILD layer 402. Since bottom-up deposition can be more time consuming and expensive than other methods, the tungsten S / D vias 416 are only grown until they are above the subsequent CMP surface height h6 (see FIG. Fig.16 ). In addition, because bottom-up deposition is directional, growing the S / D via 416 above the top surface of the second ILD layer 402 may produce an undesirable bump for subsequent CMP processes. As such, the S / D via 416 does not grow higher than the height h4, and the top surface of the S / D via 416 is lower than the top surface of the second ILD layer 402 at this process station.

[0090] Still refer to Fig.15After or as part of forming the S / D via 416, operation 124 includes forming a compliant conductive barrier layer 417 over the S / D via 416 and over the top and side surfaces of the second ILD layer 402. Operation 124 further includes forming an overload metal 419 over the compliant conductive barrier layer 417 and overfilling the S / D via trench 406. The barrier layer 417 acts as an adhesion layer between the S / D via 416 and the overload metal 419. The barrier layer 417 may have a material composition different from tungsten, and it is prepared for the subsequent formation of the overload metal 419. In one embodiment, the barrier layer 417 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). In another embodiment, the barrier layer 417 may include tungsten. The overload metal 419 is formed by isotropic chemical vapor deposition (CVD), which is a faster and cheaper metal growth process compared to selective bottom-up growth. In addition, since the growth is isotropic and formed over the compliant conductive barrier layer 417, a more uniform top surface is produced when it is formed over the second ILD layer 402. This is required to prepare for the subsequent CMP process. In one embodiment, the overload metal 419 may include tungsten. In other embodiments, the overload metal 419 may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tantalum (Ta), or molybdenum (Mo).

[0091] Now refer to Fig.16 At operation 126, the method 100 performs a second planarization process such that the top surface of the tungsten S / D via 416 is flush with the top surface of the second ILD layer 402. The second planarization process may be a CMP process, and the second planarization process removes the compliant conductive barrier layer 417 and the overload metal 419. The second planarization process planarizes the second ILD layer 402 and the tungsten S / D via 416 to a height h6 that is lower than the height h5. It is noteworthy that at this process station, the tungsten S / D via 416 is formed to be wider than the tungsten S / D contact 316 in the x-direction (i.e., the width d2 is greater than the width d1). As a result, the tungsten S / D via 416 directly contacts the top surface of the first ILD layer 302.

[0092] Reference Fig.17 At operation 128 , the method 100 forms a gate via trench 408 through the second ILD layer 402 , the CESL 412 , and the first ILD layer 302 . Fig.17One gate via trench 408 is shown, but the present disclosure contemplates that multiple gate via trenches 408 may be formed. The gate via trench 408 exposes the top surface of the metal gate structure 210 (specifically the metal gate stack 208). The gate via trench 408 may be formed by an etching process, such as a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In one embodiment, the etching process is a multi-step etching process. For example, the etching process may include an alternative etchant to remove the second ILD layer 402, the CESL 412, and the first ILD layer 302, respectively and alternately. In one embodiment, a lithography process is performed to form a patterned mask layer, and the etching process uses the patterned mask layer as an etching mask when forming the gate via trenches 408406.

[0093] Reference Fig.18 At operation 130, the method 100 forms a second tungsten seed layer 410 in the gate via trench 408 and over the metal gate structure 210 by PVD. The second tungsten seed layer 410 is conformally formed over a top surface of the second ILD layer 402, a top surface of the metal gate stack 208, side surfaces of the first ILD layer 302 and the second ILD layer 402, and a side surface of the CESL 412. In other words, a bottom portion of the second tungsten seed layer 410 directly lands on each metal gate stack 208, and a side portion of the second tungsten seed layer 410 directly lands on a side portion of each gate via trench 408.

[0094] The second tungsten seed layer 410 is formed using PVD rather than CVD or other deposition processes because a pure metal precursor layer is desired. It is noteworthy that the second tungsten seed layer 410 can act as a conductive liner for the subsequent formation of gate vias 516. Instead of using a conventional conductive barrier layer (e.g., made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN)), a tungsten liner is used to help reduce resistivity. The tungsten liner also helps prepare for the subsequent tungsten metal growth of a single grain or less grain boundary interface.

[0095] Reference Fig.19, at operation 132, the method 100 forms tungsten gate vias 516 by growing tungsten above the second tungsten seed layer 410. The gate vias 516 are formed by chemical vapor deposition (CVD), and they are formed by isotropic metal growth rather than bottom-up deposition. As such, in operation 132, the top and side portions of the second tungsten seed layer 410 are retained. This is different from the process used to form the tungsten S / D contacts 316, where the top and side portions of the first tungsten seed layer 310 are removed. Since the tungsten gate vias 516 are formed by CVD isotropic metal growth, tungsten also grows in a horizontal direction from the side surface of the second tungsten seed layer 410. As such, one or more voids 505 (also referred to as seams or air gaps) may be formed in the tungsten gate vias 516. Even so, device performance is not affected due to the all-tungsten solution and the looser process window for forming the gate vias. In addition, by using CVD isotropic growth for gate via 516, manufacturing operations are simplified. That is, no additional removal process is required for the second tungsten seed layer 410, and no additional deposition of overload metal is required. As shown in the figure, CVD isotropic growth grows tungsten above the top surface of the second tungsten seed layer 410. No additional overload metal deposition is required before performing the planarization process.

[0096] Now refer to Fig. 20 As part of forming the tungsten gate via 516, a third planarization process is performed so that the top surface of the tungsten gate via 516 is flush with the top surface of the tungsten S / D via 416 and the second ILD layer 402. The third planarization process may be a CMP process, and the third planarization process removes a top portion of the second tungsten seed layer 410 above the second ILD layer 402.

[0097] The following describes in more detail Fig. 202. The device 200 in FIG. 2. The tungsten S / D contact 316 passes through the top surface of the first ILD layer 302 and is flush with the top surface of the first ILD layer 302. The tungsten S / D via 416 passes through the second ILD layer 402 and the CESL 412. The tungsten S / D via 416 may be wider than the tungsten S / D contact 316 and lands on the tungsten S / D contact 316 and the first ILD layer 302. The tungsten gate via 516 passes through the second ILD layer 402, the CESL 412, and the first ILD layer 302. The tungsten gate via 516 has a top surface that is flat with the top surface of the tungsten S / D via 416. The tungsten gate via 516 lands on the metal gate stack 208. The tungsten S / D contact 316 and the S / D via 416 are formed by bottom-up deposition and have no voids. The tungsten gate via 516 is formed by CVD isotropic growth with one or more voids 505. The tungsten S / D contact 316 is lined with the first tungsten seed layer 310 only at the bottom horizontal interface between the S / D contact 316 and the silicide feature 308. The tungsten S / D via 416 is not lined with any seed layer. The tungsten gate via 516 is lined with the second tungsten seed layer 410, which surrounds the sidewalls and bottom surface of the tungsten gate via 516. The first tungsten seed layer 310 and the second tungsten seed layer 410 are formed by PVD metal deposition.

[0098] Although both the seed layer and the metal contacts / vias are made of tungsten, the seed layer has a higher metal conductivity than the metal contacts / vias. This is because the seed layer is formed by PVD, while the metal contacts / vias are formed by bottom-up deposition or CVD isotropic growth, where halogen gas may be mixed with the deposited metal. Therefore, PVD-formed tungsten may also have lower resistivity and higher reflectivity than CVD-formed tungsten.

[0099] An all-tungsten contact scheme for S / D contacts, S / D vias, and gate vias is shown. Method 100 describes forming various seed layers (e.g., a first tungsten seed layer 310 and a second tungsten seed layer 410). These seed layers are referred to as layers separate from the metal contacts and / or vias formed thereon. However, although formed by separate processes, these seed layers may also be referred to as part of the corresponding metal contacts or vias. For example, the first tungsten seed layer 310 is part of the tungsten S / D contact 316, and the second tungsten seed layer 410 is part of the tungsten gate via 516.

[0100] Fig.21 According to another embodiment of the present disclosure, Figure 1A and Figure 1B 2 is a cross-sectional view of a semiconductor device 200 processed by the method. Fig.21 and Fig. 20Similar, and for the sake of brevity, similar features will not be described again. The difference is that the all-tungsten contact scheme is applied to the GAA device. As shown in the figure, the channel region 206a includes a stack of channel layers 207, and each channel layer 207 is surrounded by a metal gate structure 210 (specifically a metal gate stack 208). Internal spacers 211 can also be set in the channel region 206a between the channel layers 207 and between the metal gate stack 208 and the S / D region 206b.

[0101] Although not intended to be limiting, the present disclosure provides advantages associated with metal contacts and vias (e.g., S / D contacts, S / D vias, and gate vias). One example advantage is that the metal contacts and vias are both made of tungsten to achieve a uniform interface. Another example advantage is that the S / D contacts and S / D vias are formed without voids. Another example advantage is that a tungsten seed layer is used when forming the gate via, rather than depositing a traditional barrier layer.

[0102] One aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes receiving a workpiece having a plurality of gate structures above a plurality of channel regions on a substrate and source / drain (S / D) features adjacent to the channel regions. The method includes forming a plurality of tungsten S / D contacts in a first ILD layer above the S / D features by a first selective bottom-up metal growth process. The method includes forming a plurality of tungsten S / D vias in a second ILD layer above the tungsten S / D contacts by a second selective bottom-up metal growth process. And after forming the tungsten S / D vias, the method includes forming a plurality of tungsten gate vias in the first ILD layer and the second ILD layer above the gate structures. The formation of the tungsten gate vias includes forming a tungsten seed layer by physical vapor deposition (PVD), and directly depositing tungsten on a plurality of horizontal surfaces and a plurality of sidewall surfaces of the tungsten seed layer by chemical vapor deposition (CVD).

[0103] In one embodiment, the tungsten seed layer is a second tungsten seed layer, and the formation of the tungsten S / D contacts includes forming a first tungsten seed layer by PVD, removing multiple portions of the first tungsten seed layer, and depositing tungsten on multiple horizontal surfaces of the first tungsten seed layer by a first selective bottom-up metal growth process.

[0104] In further embodiments, tungsten S / D vias are formed directly on multiple horizontal surfaces of the tungsten S / D contacts.

[0105] In one embodiment, the tungsten S / D contacts and tungsten S / D vias are formed without voids, and the tungsten gate vias are formed with one or more voids.

[0106] In one embodiment, a tungsten S / D via and a tungsten gate via are formed through an etch stop layer interposed between the first ILD layer and the second ILD layer.

[0107] In one embodiment, before forming the tungsten S / D vias, the method further includes forming a compliant conductive barrier layer over the tungsten S / D contacts, depositing an overload metal over the compliant conductive barrier layer, and performing a planarization process to remove the compliant conductive barrier layer and the overload metal.

[0108] In further embodiments, the compliant conductive barrier layer is different in material composition from the tungsten S / D contacts.

[0109] In a further embodiment, the overload metal is tungsten, and the overload metal is formed by isotropic chemical vapor deposition.

[0110] In a further embodiment, before forming the tungsten gate via, the method further includes forming a compliant conductive barrier layer over the tungsten S / D via, depositing an overload metal over the compliant conductive barrier layer, and performing a planarization process to remove the compliant conductive barrier layer and the overload metal.

[0111] Another aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes receiving a workpiece having a plurality of gate structures above a plurality of channel regions on a substrate and source / drain (S / D) features adjacent to the channel regions. The method includes depositing a first interlayer dielectric (ILD) layer above the gate structures and above the S / D features. The method includes forming a plurality of S / D trenches through the first ILD layer, the S / D trenches exposing a plurality of top surfaces of the S / D features. The method includes forming a plurality of silicide features on the S / D features. The method includes forming a first tungsten seed layer by physical vapor deposition (PVD) above the first ILD layer and in the S / D trenches. A plurality of bottom portions of the first tungsten seed layer fall directly on the silicide features. The method includes removing a plurality of top portions and a plurality of side portions of the first tungsten seed layer so that only a bottom portion of the first tungsten seed layer remains. The method includes forming a plurality of tungsten S / D contacts above a bottom portion of the first tungsten seed layer by selective bottom-up metal growth. The method includes depositing a second ILD layer above the S / D contacts and above the first ILD layer. The method includes forming a plurality of S / D via trenches through the second ILD layer, the S / D via trenches exposing a plurality of top surfaces of the tungsten S / D contacts. The method includes forming a plurality of tungsten S / D vias above the tungsten S / D contacts by selective bottom-up metal growth. After forming the tungsten S / D vias, the method includes forming a plurality of gate via trenches through the first ILD layer and the second ILD layer, the gate via trenches exposing a plurality of top surfaces of the gate structure. The method includes forming a second tungsten seed layer by PVD above the second ILD layer and in the gate via trenches. And the method includes forming a plurality of tungsten gate vias above the second tungsten seed layer by chemical vapor deposition (CVD).

[0112] In one embodiment, removing the top portion and the side portion of the first tungsten seed layer includes a first removal process and a second removal process, and the first removal process removes the top portion of the first tungsten seed layer and the second removal process removes the side portion of the first tungsten seed layer.

[0113] In a further embodiment, the first removal process includes depositing a sacrificial layer in the S / D trenches and over the first tungsten seed layer, partially etching the sacrificial layer to expose a top portion of the first tungsten seed layer, and etching the exposed top portion of the first tungsten seed layer.

[0114] In a further embodiment, the second removal process includes etching the remaining portions of the sacrificial layer to expose side portions of the first tungsten seed layer, and etching the exposed side portions of the first tungsten seed layer.

[0115] In one embodiment, forming a tungsten S / D contact includes growing a tungsten metal layer on a first tungsten seed layer to a first height, and the tungsten metal layer has a top surface lower than a top surface of a first interlayer dielectric layer; forming a compliant conductive barrier layer above the tungsten metal layer and above multiple top surfaces and multiple side surfaces of a first ILD layer; forming an overload metal above the compliant conductive barrier layer; and performing a planarization process to remove the compliant conductive barrier layer and the overload metal, the planarization process planarizing the first ILD layer and the tungsten metal layer to a second height lower than the first height.

[0116] In one embodiment, the S / D via trench is formed to be wider than the S / D trench, such that the S / D via trench also exposes a top surface of the first ILD layer.

[0117] In one embodiment, each of the channel regions includes a stack of multiple channel layers surrounded by a respective gate structure over the channel region.

[0118] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a channel region on a substrate and an S / D feature adjacent to the channel region. The semiconductor device includes a gate structure above the channel region, a first interlayer dielectric (ILD) layer above the gate structure, an etch stop layer above the first ILD layer, and a second ILD layer above the etch stop layer. A tungsten S / D contact is disposed above the S / D feature and surrounded by the first ILD layer. A tungsten S / D via falls on the S / D contact and is surrounded by the second ILD layer. A tungsten gate via falls on the gate structure and is surrounded by the first ILD layer and the second ILD layer. The tungsten gate via includes one or more air gaps.

[0119] In one embodiment, the tungsten S / D contact has a first width that is less than a second width of the tungsten S / D via, and the tungsten S / D via also lands on the top surface of the first ILD layer.

[0120] In one embodiment, the channel region includes a stack of multiple channel layers, and each of the channel layers is surrounded by a gate structure.

[0121] In one embodiment, the bottom surface and sidewall surfaces of the tungsten gate via are lined with a tungsten seed layer having a greater metal conductivity than the tungsten gate via.

[0122] The foregoing text summarizes the features of many embodiments so that those with ordinary knowledge in the art can better understand the present disclosure from various aspects. Those with ordinary knowledge in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications may be made to the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a channel region on a substrate; a source / drain feature adjacent to the channel region; a gate structure, above the channel region; a first interlayer dielectric layer, above the gate structure; an etch stop layer above the first interlayer dielectric layer; a second interlayer dielectric layer above the etch stop layer; a tungsten source / drain contact over the source / drain features and surrounded by the first interlayer dielectric layer; a tungsten source / drain via hole located on the tungsten source / drain contact and surrounded by the second interlayer dielectric layer; and a tungsten gate via, located on the gate structure and surrounded by the first interlayer dielectric layer and the second interlayer dielectric layer, The tungsten gate through hole includes one or more air gaps.

2. The semiconductor device according to claim 1, wherein The tungsten source / drain vias also fall on a top surface of the first interlayer dielectric layer.

3. The semiconductor device according to claim 1, wherein: The tungsten source / drain contact has a first width, and the first width is smaller than a second width of the tungsten source / drain through hole.

4. The semiconductor device according to claim 1, wherein The channel region comprises a stack of a plurality of channel layers; and Each of the channel layers is surrounded by the gate structure.

5. The semiconductor device according to claim 1, wherein: A bottom surface and a plurality of sidewall surfaces of the tungsten gate via are lined with a tungsten seed layer, and the tungsten seed layer has a metal conductivity greater than that of the tungsten gate via.

6. The semiconductor device according to claim 1, wherein: Also includes: A silicide feature is formed over the source / drain feature.

7. The semiconductor device according to claim 6, wherein: Also includes: A tungsten seed layer is above the silicide features, wherein the tungsten source / drain contacts directly contact the tungsten seed layer.

8. The semiconductor device according to claim 1, wherein The tungsten source / drain contacts directly contact the first interlayer dielectric layer.

9. The semiconductor device according to claim 1, wherein: The etching stop layer is a first etching stop layer, and the semiconductor device further comprises: a gate spacer on a side wall of the gate structure; and A second etching stop layer is on a side wall of the gate spacer.

10. The semiconductor device according to claim 9, wherein: The first interlayer dielectric layer separates the tungsten source / drain contacts from the second etch stop layer.

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