Semiconductor device

Abstract

A semiconductor device disclosed herein includes an interconnect structure over a substrate, a first magnetic layer over the interconnect structure, one or more conductive features over the first magnetic layer, a dielectric layer over the first magnetic layer and the one or more conductive features, and a second magnetic layer over the dielectric layer. In some embodiments, the one or more conductive features include a textured top surface.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster semiconductor devices that are simultaneously capable of supporting an increasing number of increasingly complex and sophisticated functions. Thus, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and reducing associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] Many applications implemented on modern semiconductor chips require accurate voltages. An integrated voltage regulator (IVR) can be used to automatically maintain a constant voltage. In an IVR device, a sensing structure and one or more passivation layers can be formed above a semiconductor substrate including device layers (e.g., transistors, etc.) and above a multi-layer interconnect (MLI) structure that provides interconnections between various microelectronic components of the substrate and upper contact features. Various contact features and magnetic films can be formed in an IVR device. In various instances, one or more passivation layers, MLI structures, conductive features, and / or magnetic films can experience stress in certain areas, which can result in delamination, thereby degrading device reliability.

[0004] Therefore, the prior art has not proven to be completely satisfactory in all respects. Utility Model Content

[0005] Some embodiments of the present disclosure provide a semiconductor device, a semiconductor device comprising: an interconnect structure above a substrate; a first magnetic layer above the interconnect structure; one or more conductive features above the first magnetic layer; a dielectric layer above the first magnetic layer and the one or more conductive features; and a second magnetic layer above the dielectric layer. The one or more conductive features include a textured top surface.

[0006] Some embodiments of the present disclosure provide a semiconductor device comprising: a top metal wiring above a substrate; a conductive pad above the top metal wiring; two conductive features above the conductive pad; a dielectric layer above the two conductive features; and a magnetic layer above the dielectric layer, wherein the conductive pad and the two conductive features each include a textured top surface.

[0007] Some embodiments of the present disclosure provide a semiconductor device, the semiconductor device comprising two conductive features above a substrate and embedded in a first dielectric layer; the two conductive features and a second dielectric layer above the first dielectric layer; and a magnetic layer above the second dielectric layer. The two conductive features include a textured surface, the textured surface having a surface roughness of 50 nm to 90 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of this disclosure are as follows: Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a perspective view of a portion of a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 2 A portion of a semiconductor device according to some embodiments of the present disclosure is provided along Figure 1 A cross-sectional view taken along line AA in FIG.

[0011] Figure 3 , Figure 4 and Figure 5 is a cross-sectional view of a portion of a package including a semiconductor device according to some embodiments of the present disclosure.

[0012]

Explanation of symbols

[0013] 100:Semiconductor device

[0014] 102:Substrate

[0015] 104: Interconnection structure

[0016] 105: Induction structure

[0017] 106: Conductor

[0018] 107: Multilayer Interconnection Structure / MLI Structure

[0019] 108: Passivation structure

[0020] 108L: Lower layer

[0021] 108U: Upper layer

[0022] 110: Top metal wiring

[0023] 112: Conductive pad

[0024] 114: Magnetic components

[0025] 115a: Top surface

[0026] 115b: Top surface

[0027] 116a: Side wall

[0028] 116b: Side wall

[0029] 118: Isolation Components

[0030] 118a: Part 1

[0031] 118b: Part 2

[0032] 122: Dielectric layer

[0033] 125:Joint / Boundary

[0034] 126: Magnetic layer

[0035] 126a: Part 1

[0036] 126b: Part 2

[0037] 127a: Top surface

[0038] 127b: Top surface

[0039] 128: Isolation layer

[0040] 132: Dielectric filler

[0041] 137: Top surface

[0042] 139: Side wall

[0043] 145: Airfoil / Edge

[0044] 200: Encapsulation

[0045] 202:Substrate

[0046] 204: Interconnection structure

[0047] 210: Protective layer

[0048] 215: first conductive feature

[0049] 220: Second conductive feature

[0050] 225: Bump

[0051] 300: Encapsulation

[0052] 302:Substrate

[0053] 305: Conductive characteristics

[0054] 310:Molding Underfill / MUF

[0055] 315:Metal ball structure

[0056] 400: Encapsulation

[0057] 402:Substrate

[0058] 404: Shell substrate

[0059] 405: Conductive characteristics

[0060] 410:Molding Underfill / MUF

[0061] 415:Metal ball structure

[0062] 420: Conductive characteristics

[0063] 500: Device

[0064] 505: Device

[0065] D1: Angle

[0066] D2: Angle

[0067] H1: Height

[0068] H2: Height

[0069] R1: Surface roughness value

[0070] R2: Surface roughness value

[0071] R3: Surface roughness value

[0072] R4: Surface roughness value

[0073] W1: Width

[0074] W2: Width

[0075] AA:Line

[0076] X: Axis

[0077] Y: Axis

[0078] Z: Axis DETAILED DESCRIPTION

[0079] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simple and clear purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0080] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0081] Furthermore, when a number or a range of numbers is described by "about," "approximately," and the like, the term is intended to encompass numbers within a reasonable range including the described number, such as numbers within + / -10% of the described number or other values ​​as understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0082] The sensing structure is used in various electronic applications, such as radio frequency filters, alternating current (AC) blockers, voltage regulators, transformers, and / or the like. The sensing structure may include a magnetic component, such as a magnetic film. A voltage regulator integrated on a package or die may be referred to as an integrated voltage regulator (IVR). An IVR device (such as a coupled inductor voltage regulator (CLVR)) may include a sensing structure and one or more passivation layers formed above a semiconductor substrate including device layers (e.g., transistors, etc.) and above a multi-layer interconnect (MLI) structure. The MLI structure may include metal wiring and metal via layers and provide interconnects between various microelectronic components within the semiconductor substrate and upper contact features. Upper contact features, such as contact pads, may be formed in one or more passivation layers (e.g., for connecting external circuits). In an IVR device, the magnetic film and other elements (e.g., contact pads, conductive features, dielectric features) experience stress during manufacture and / or operation of the IVR device. The magnetic film and / or other elements may not sustain the stress and result in device defects (e.g., cracks and / or delamination), thereby degrading device reliability. Furthermore, during operation of the IVR device, excess energy may be wasted. Thus, existing structures have not been completely satisfactory in all respects.

[0083] The present disclosure is generally directed to an IVR device, such as a CLVR device. More specifically, the present disclosure proposes a semiconductor device (e.g., an IVR device, a CLVR device) having conductive features including a dense copper (Cu) material. The disclosed semiconductor device may include an interconnect structure above a substrate. The interconnect structure may include a contact pad on a top metal wire. In various examples, the disclosed semiconductor device includes a first magnetic layer above the interconnect structure, two conductors above the first magnetic layer, a dielectric layer above the two conductors, and a second magnetic layer above the dielectric layer. The two conductors and / or the contact pad may include a dense copper material that includes more than 97% copper (111). The dense copper material has a lower modulus and higher conductivity than at least some prior implementations, and may have reduced height conductors and / or conductive pads, thereby reducing stress (e.g., chip package interaction stress or CPI stress), delamination defects, and / or wasted energy of the semiconductor device. The dense copper material may also include rough surfaces of both conductors and / or contact pads, which also helps maintain stress and mitigate stress and defects (e.g., this decomposition effect). Additional details of embodiments of the present disclosure are provided below, and additional benefits and / or other advantages will become more apparent to those skilled in the art having the benefit of this disclosure.

[0084] View now Figure 1 , shown is a perspective view of a portion of a semiconductor device 100 according to some embodiments. In some embodiments, the semiconductor device 100 includes a substrate 102, an interconnect structure 104 above the substrate 102, and a sensing structure 105 above the interconnect structure 104. In some embodiments, the sensing structure 105 includes one or more conductors 106. The sensing structure 105 and the one or more conductors 106 may extend longitudinally along the Y direction.

[0085] The substrate 102 may be a semiconductor substrate such as a silicon substrate. The substrate 102 may include various layers including conductive or insulating layers formed on the substrate 102. The substrate 102 may include various doping configurations depending on design requirements as known in the art. The substrate 102 may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 102 may include a compound semiconductor and / or an alloy semiconductor. Additionally, in some embodiments, the substrate 102 may include an epitaxial layer (epi-layer), the substrate 102 may be tensioned for performance enhancement, the substrate 102 may include a silicon-on-insulator (SOI) structure, and / or the substrate 102 may have other suitable enhancement features.

[0086] In some embodiments, substrate 102 includes one or more active and / or passive semiconductor devices, such as transistors, diodes, optoelectronic devices, resistors, capacitors, sensors, or other devices. In various examples, transistors may include source / drain features, gate structures, gate spacers, contact features, isolation structures such as shallow trench isolation (STI) structures, or other suitable elements. For example, active and / or semiconductor devices formed in substrate 102 may be formed as part of a front-end-of-line (FEOL) process.

[0087] In some embodiments, the substrate 102 includes one or more dielectric layers. The one or more dielectric layers may include silicon oxide or a material containing silicon oxide. In some cases, the one or more dielectric layers may include undoped silicate glass (USG). In various examples, the one or more dielectric layers may be deposited by plasma enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), sub-atmospheric CVD (SACVD), ALD, PVD, or a combination thereof.

[0088] In some embodiments, the substrate 102 includes an interlayer dielectric (ILD) layer. The ILD layer may include silicon oxide, a material containing silicon oxide, or a low-k dielectric layer such as TEOS oxide, undoped silicate glass (USG), or doped silicon oxide such as BPSG, FSG, PSG, BSG, and / or other suitable low-k dielectric materials. In various examples, the ILD layer may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0089] In some embodiments, the substrate 102 includes an etch stop layer (ESL). In some cases, the ESL includes a nitrogen-containing material and / or a carbon-containing material. For example, the ESL may include silicon carbide nitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), or a combination thereof. In various examples, the ESL may be deposited by CVD, ALD, PVD, or a combination thereof.

[0090] View now Figure 2 , shown is a diagram according to some embodiments along Figure 1 1 is a cross-sectional view of a portion of the semiconductor device 100 taken along line AA in FIG. In some embodiments, the interconnect structure 104 includes a multi-layer interconnect (MLI) structure 107 and a passivation structure 108 over the MLI structure 107. By way of example, the MLI structure 107, the passivation structure 108, and other layers, features, elements, or devices formed over the MLI structure 107 may be formed as part of a back end of line (BEOL) process.

[0091] The MLI structure 107 may include a plurality of patterned dielectric layers and conductive layers, each of which provides interconnections (wiring) between various microelectronic components formed within the substrate 102 and upper conductive features in the passivation structure 108. As mentioned, the MLI structure 107 may include a plurality of conductive features and a plurality of dielectric layers to provide isolation between the conductive features. In some embodiments, the dielectric layers of the MLI structure 107 may include silicon oxide or a silicon oxide-containing material in which silicon is present in various suitable forms. In some examples, the dielectric layer may include a low-k dielectric layer (e.g., having a dielectric constant less than that of SiO2, which is about 3.9), such as an oxide formed from tetraethylorthosilicate (TEOS), undoped silicate glass (USG), or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable low-k dielectric materials.

[0092] In some embodiments, the conductive features of the MLI structure 107 may include contacts, vias, or metal wiring (e.g., top metal wiring 110) to provide horizontal and vertical interconnects. In some cases, the metal wiring includes copper (Cu), aluminum (Al), aluminum-copper (AlCu) alloy, ruthenium (Ru), cobalt (Co), or other suitable metal layers. In some examples, the contacts and / or vias may include Cu, Al, AlCu alloy, Ru, Co, tungsten (W), or other suitable metal layers. In some embodiments, the metal wiring, contacts, and / or vias include a barrier layer and a bulk metal layer above the barrier layer.

[0093] The top metal wiring (e.g., top metal wiring 110) is sometimes referred to as a top metal (TM) contact because it represents the top metal layer of the MLI structure 107 discussed previously. By way of example, forming the top metal wiring (e.g., top metal wiring 110) includes multiple processes. The top metal wiring 110 can be formed by patterning the dielectric layer of the MLI structure 107 to form a trench, depositing a barrier layer in the trench, and depositing a metal fill layer over the barrier layer. In various examples, the dielectric layer can be patterned using a suitable combination of optical lithography processes (e.g., such as photoresist deposition, exposure, and development) to form an etch mask, and the etching process can be performed using the etch mask to form the trench. In some cases, a hard mask layer (e.g., such as a nitride-containing layer) can be used as part of the patterning process of the dielectric layer. It should be understood that other top metal wirings can also be formed in other trenches provided by the patterned dielectric layer. In some embodiments, a barrier layer is formed in each trench provided by the patterned layer, followed by depositing a metal fill layer over the barrier layer. In some embodiments, the barrier layer comprises titanium nitride, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the metal fill layer comprises a metal or metal alloy such as copper, cobalt, nickel, aluminum, tungsten, titanium, or a combination thereof. In some embodiments, the metal fill layer is formed by deposition or electroplating followed by a chemical mechanical planarization (CMP) process.

[0094] In some embodiments, the passivation structure 108 is formed above the MLI structure 107 and above the top metal wiring 110, such as Figure 2 . In some embodiments, the passivation structure 108 includes a plurality of passivation layers. The plurality of passivation layers may include a protective layer including a nitrogen-containing material and / or a carbon-containing material. For example, the protective layer may include SiCN, SiOC, SiC, SiOCN, SiN, or a combination thereof. In various examples, the protective layer may be deposited by CVD, ALD, PVD, or a combination thereof. In some embodiments, the protective layer may protect the top metal wiring from oxidation.

[0095] The plurality of passivation layers may further include a plasma-enhanced oxide (PEOX) layer formed over the protective layer. In some embodiments, the PEOX layer may include silicon oxide or a material containing silicon oxide. In some cases, the PEOX layer may include undoped silicate glass (USG). The PEOX layer may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, or a combination thereof.

[0096] In some embodiments, the plurality of passivation layers include an ESL. The ESL may be made of or include tantalum oxide, zirconium oxide, tantalum nitride, titanium, one or more other suitable materials, or a combination thereof.

[0097] In some embodiments, the passivation structure 108 further includes a polymer layer. The polymer layer may be formed above the plurality of passivation layers. In some embodiments, the polymer layer is the topmost layer of the passivation structure 108. In some embodiments, the polymer layer includes epoxy, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or a combination thereof. In some embodiments, the polymer layer includes PI and is referred to as a PI layer. The polymer layer may be deposited on the MLI structure 107 using a suitable deposition technique, such as spin coating or a vapor-deposition process (VDP).

[0098] In some embodiments, the passivation structure 108 includes a conductive pad 112 above the top metal wire 110. In some embodiments, the conductive pad 112 includes more than 97% copper (111). In some embodiments, the top surface of the conductive pad 112 includes more than 97% copper (111). In some embodiments, the conductive pad 112 includes less than 3% of a metal or metal alloy other than copper (111), such as copper (110), cobalt, nickel, aluminum, tungsten, titanium. In some embodiments, the top surface of the conductive pad 112 includes less than 3% of a metal or metal alloy other than copper (111). Copper (111) is a type of crystalline copper with a specific crystal orientation. Compared to other copper materials, such as copper (100) and copper (110), copper (111) is more dense and has a relatively low energy surface and lower thermal expansion along three lattice directions. For the purpose of description in this disclosure, materials having more than 97% copper (111) are also referred to as "dense copper (Cu) materials". In some embodiments, the conductive pad 112 includes a dense copper material. In some embodiments, the dense copper material includes a nano-twinned Cu material, such as a nano-twinned Cu (111) material. The nano-twinned Cu material has a crystal lattice on each boundary edge that is a symmetrical atomic configuration across respective boundaries. Some benefits of dense copper materials include greater conductivity and smaller modulus compared to other copper materials. Therefore, by including dense copper material, the conductive pad 112 may have reduced resistance and increased ability to maintain stress, such as chip package interaction (CPI) stress. The ability to maintain stress herein refers to the ability to carry or withstand any existing stress. The conductive pad 112 may have any suitable shape. The conductive pad 112 may have a height H1 of about 1 μm to about 7 μm along the Z direction. If H1 is too small, the conductive pad 112 may be too thin to protect the underlying structure, and the resistance of the conductive pad 112 may be too large, thereby causing unnecessary energy waste during operation of the semiconductor device 100. If H1 is too large, the ability of the conductive liner 112 to sustain stress may be too small, and H1 may unnecessarily increase the material of the conductive liner 112 and the cost associated with the conductive liner 112. In some embodiments, the ratio of the width W1 of the conductive liner 112 along the X direction to H1 is about 0.5 to about 15. If the ratio is too small, the ability of the conductive liner 112 to sustain stress may be too small. If the ratio is too large, the ratio may necessarily increase the footprint of the conductive liner 112 and the cost associated with the conductive liner 112, and / or the conductive liner 112 may be too thin to protect the underlying structure.

[0099] The conductive pad 112 may be formed using any suitable method. In some examples, after the lower layer 108L of the passivation structure 108 is formed over the MLI structure 107 and the top metal wiring 110, an opening through the lower layer 108L is formed to expose the top surface of the top metal wiring 110. In some embodiments, the opening may be formed using an etching process (e.g., such as a dry etching process, a wet etching process, or a combination thereof). In various embodiments, the sidewalls of the opening may expose the sidewalls of the lower layer 108L through which the opening penetrates. In some embodiments, the conductive pad 112 is formed in and over the opening. In some embodiments, to form the conductive pad 112, a dense copper layer including a dense copper material is first conformally deposited over the lower layer and into the opening using a suitable deposition technique, such as ALD, PVD, or CVD. In the depicted embodiment, a CMP process may be performed to planarize the top surface 115a of the conductive pad 112 and the top surface of the lower layer 108L. In these embodiments, the top surface 115a and the sidewalls 116a have smooth surfaces. In other embodiments, the deposited dense copper layer is patterned to form the conductive pad 112. In some embodiments, the dense copper layer is patterned in a one-stage or multi-stage etching process. In some embodiments, the conductive pad 112 includes an upper portion above the lower layer 108L and a lower portion inside the opening. In some embodiments, the top surface (e.g., top surface 115b) of the conductive pad 112 is not planarized and has a textured surface having a surface roughness value R1 of about 10nm to about 90nm. Surface roughness can also be referred to as peak-to-valley height, which is the distance between peaks and valleys of a surface (e.g., top surface 115b of the conductive pad 112) perpendicular to the surface (e.g., along the Z direction). In some embodiments, the sidewall of the conductive liner 112 (e.g., the sidewall 116b of the upper portion of the conductive liner 112) has a textured surface, thereby having a surface roughness value R2 of about 10 nm to about 90 nm. In some embodiments, the sidewall of the conductive liner 112 includes more than 97% copper (111) and less than 3% of a metal or metal alloy other than copper (111). After forming the conductive liner 112, the upper layer 108U of the passivation structure 108 is formed over the conductive liner 112 and the lower layer 108L of the passivation structure 108.

[0100] In some embodiments, the conductive pad 112 and other similar contact features of the passivation structure 108 are part of a redistribution layer (RDL) that includes features for redistributing the bonding pads to different orientations, such as redistributing from a peripheral orientation to be uniformly distributed on the wafer surface. In various examples, the RDL couples a multi-layer interconnect (MLI) structure 107 to the bonding pads to connect to external circuits. In addition, upper contact features (e.g., contact features in the passivation structure 108, such as the conductive pad 112) provide electrical contact to lower contact features (e.g., contact features in the MLI structure 107, such as the top metal wire 110).

[0101] In some embodiments, semiconductor device 100 includes a sensing structure 105 over a passivation structure 108. In some embodiments, sensing structure 105 includes various elements such as magnetic component 114, one or more conductors 106, isolation component 118, dielectric filler 132, isolation layer 128, dielectric layer 122, and magnetic layer 126.

[0102] In some embodiments, the sensing structure 105 includes a magnetic component 114 above the passivation structure 108. The magnetic component 114 extends horizontally along the top surface of the passivation structure 108. The magnetic component 114 may include one or more magnetic layers. In some embodiments, a lower layer of the one or more magnetic layers is wider than an upper layer of the one or more magnetic layers along the X direction. In other words, the width of the one or more magnetic layers along the X direction gradually decreases from the bottom to the top. In some embodiments, the magnetic component 114 includes one or more magnetic materials, such as a cobalt alloy (e.g., cobalt-zirconium-tantalum (CoZrTa or CZT), CoZr and / or the like), a nickel alloy (e.g., nickel-iron (NiFe) and / or the like), another magnetic material, or a combination thereof. In some embodiments, the magnetic component 114 includes cobalt, zirconium, tantalum, iron, nickel, or a combination thereof. In some embodiments, the magnetic component 114 includes CoZrTa (or CZT).

[0103] The magnetic component 114 may be formed by any suitable method, such as a deposition and patterning process (e.g., sequential deposition and patterning process). One or more magnetic layers of the magnetic component 114 may be deposited using a PVD process, a CVD process, an ALD process, one or more other applicable processes, or a combination thereof. A patterned mask layer (not depicted) may be formed over the one or more magnetic layers to assist in the subsequent patterning process of the one or more magnetic layers. In some embodiments, the patterned mask layer is a patterned photoresist layer. An optical lithography process may be used to form a patterned mask layer having a desired pattern. For example, a top view of the patterned mask layer may have a square shape, a rectangular shape, or another suitable shape. In some embodiments, an etching process is used to partially remove one or more magnetic layers when the patterned mask layer serves as an etching mask. In some embodiments, the etching process is a wet etching process. The etchant used for the wet etching process may include nitric acid, hydrochloric acid, hydrofluoric acid, one or more other suitable etchants, or a combination thereof. For example, a mixture of nitric acid, hydrochloric acid, and hydrofluoric acid is used in a wet etching process. The ESL in the passivation structure 108 may protect the underlying structure of the passivation structure 108 from being damaged during a wet etching process used to pattern the one or more magnetic layers.

[0104] In some embodiments, the sensing structure 105 includes an isolation component 118. The isolation component 118 includes a first portion 118a above the top surface of the magnetic component 114 and a second portion 118b above the top surface of the passivation structure 108. The isolation component 118 has a step profile at the interconnection (or boundary between) of the first portion 118a and the second portion 118b. The isolation component 118 can insulate the one or more conductors 106 from the magnetic component 114. In some embodiments, the isolation component 118 includes one or more insulating and / or dielectric materials, such as silicon nitride (SiN), silicon dioxide (SiO), PI, BCB, and / or the like. In some embodiments, the isolation component 118 includes PI.

[0105] In some embodiments, the sensing structure 105 includes one or more conductors 106 above the first portion 118a of the isolation component 118. In some embodiments, the sensing structure 105 includes two conductors 106. The two conductors 106 may correspond to an input (e.g., Vin) of the sensing structure 105 and an output (e.g., Vout) from the sensing structure 105. In some embodiments, the one or more conductors 106 include conductive traces, conductive wires, and / or other conductive components. In some embodiments, the one or more conductors 106 include more than 97% copper (111). In some embodiments, the one or more conductors 106 include less than 3% of a metal or metal alloy other than copper (111), such as copper (110), cobalt, nickel, aluminum, tungsten, titanium. In some embodiments, a top surface 137 of the one or more conductors 106 includes more than 97% copper (111) and less than 3% of a metal or metal alloy other than copper (111). In some embodiments, the sidewall 139 of the one or more conductors 106 includes more than 97% copper (111) and less than 3% of a metal or metal alloy other than copper (111). In some embodiments, the one or more conductors 106 include a dense copper material as described above. By using a dense copper material with greater conductivity and lower modulus, the one or more conductors 106 can have reduced resistance and increased ability to sustain stresses, such as CPI stresses, and can also reduce some of the stresses. In some examples, stresses occur in the circular portion of the magnetic component 114, such as Figure 2 In some examples, stress occurs in the magnetic layer 126 .

[0106] One or more conductors 106 may have a height H2 of about 5 μm to about 18 μm along the Z direction. The height H2 may be adjusted to meet design parameters (e.g., resistance and modulus of one or more conductors 106). Having a height H2 within this range may reduce stress (e.g., stress in the circular portion of the magnetic component 114 and / or stress in the magnetic layer 126). If H2 is too small, the resistance of one or more conductors 106 may be too large, which may increase energy waste during operation of the semiconductor device 100. If H2 is too large, the stress reduction benefit may not exist, and H2 may unnecessarily increase the material of one or more conductors 106 and the cost associated with the conductors 106. In some embodiments, the ratio of the width W2 of one or more conductors 106 along the X direction to H2 is about 0.5 to about 2. If the ratio is too small, the ability of one or more conductors 106 to maintain stress may be too small. If the ratio is too large, the ratio may unnecessarily increase the footprint of one or more conductors 106 and the cost associated with the conductors 106.

[0107] The top surface 137 of the one or more conductors 106 may have a textured surface, thereby having a surface roughness value R3 of about 50 nm to about 90 nm, such as Figure 2. In some embodiments, the sidewall 139 of one or more conductors 106 has a textured surface, thereby having a surface roughness value R4 of about 10 nm to about 90 nm. In some other embodiments, the sidewall 139 of one or more conductors 106 has a smooth surface (e.g., having a surface roughness value of less than about 5 nm). The surface roughness value R3 of the top surface 137 of one or more conductors 106 may be greater than the surface roughness value R4 of the sidewall 139, greater than the surface roughness value R1 of the top surface 115 b of the conductive liner 112, and greater than the surface roughness value R2 of the sidewall surface 116 b of the conductive liner 112. Having a surface roughness value of the top surface 137 and / or the sidewall 139 may reduce delamination defects and other defects (e.g., cracks in the dielectric filler 132) and / or reduce stress in the semiconductor device 100 (e.g., in the magnetic layer 126). If the surface roughness value R3 of the top surface 137 is too small, the benefits of reducing delamination defects and other defects and / or reducing stress may not exist. If the surface roughness value R3 of the top surface 137 is too large, the surface roughness value R3 may increase to a defect (eg, a crack) of the dielectric filler 132 .

[0108] In some embodiments, the sensing structure 105 includes a dielectric filler 132 above the one or more conductors 106. The dielectric filler 132 fills the space between the adjacent one or more conductors 106. In some embodiments, the dielectric filler 132 is disposed on the top surface and sidewalls of the one or more conductors 106, so that the one or more conductors 106 are embedded in the dielectric filler 132. Figure 2 , the top surface of the dielectric filler 132 has a hill shape, so that the top surface of the middle portion of the dielectric filler 132 (e.g., the portion above the one or more conductors 106) is above the top surface of the outer portion of the dielectric filler 132. In some embodiments, the dielectric filler 132 has two winglets (or edges) 145 in the outer portion. The two winglets 145 are above the first portion 118a of the isolation component 118. The dielectric filler 132 can insulate the one or more conductors 106 from the magnetic layer 126. In some embodiments, the dielectric filler 132 includes one or more insulating and / or dielectric materials, such as silicon nitride (SiN), silicon dioxide (SiO), polymers (e.g., epoxy, PI, BCB, PBO), and / or the like. In some embodiments, the dielectric filler 132 includes PI. In some embodiments, the dielectric filler 132 may include the same material as the isolation component 118.

[0109] In some embodiments, the sensing structure 105 includes an isolation layer 128 above the dielectric filler 132. The isolation layer 128 is merged with the first portion 118a of the isolation component 118 outside the airfoil 145 of the dielectric filler 132 and has a smaller thickness than the first portion 118a. The isolation layer 128 can be made of a material similar to that of the dielectric filler 132 and the isolation component 118.

[0110] In some embodiments, the sensing structure 105 includes a dielectric layer 122 over a dielectric filler 132 and one or more conductors 106. In some embodiments, the dielectric layer 122 is over the top surface of the isolation layer 128 and the isolation component 118. The dielectric layer 122 includes a stepped profile outside the airfoil 145 of the dielectric filler 132. The angle D1 between the bottom surface of the dielectric layer 122 and the top surface of the magnetic component 114 is about 20 degrees to about 40 degrees. If D1 is too small, D1 may unnecessarily increase the footprint of the outer portion of the dielectric filler 132 and the cost associated with the dielectric filler 132. If D1 is too large, the stress (e.g., the stress of the magnetic component 114 under the airfoil 145) may be too large. The dielectric layer 122 may include any suitable dielectric material. In some embodiments, the dielectric layer 122 includes a nitride component, such as silicon nitride (SiN, SiN4). In some embodiments, the dielectric layer 122 includes SiN4.

[0111] In some embodiments, the sensing structure 105 includes a magnetic layer 126 over the top surface of the dielectric layer 122. The magnetic layer 126 has a non-uniform thickness in different portions. In the depicted embodiment, the magnetic layer 126 includes a first portion 126a over the dielectric filler 132 and a second portion 126b over the second portion 118b, as well as a portion of the first portion 118a of the isolation component 118. In some embodiments, the magnetic layer 126 includes a stepped profile at a joint (or boundary) 125 of the first portion 126a and the second portion 126b. In some embodiments, an angle D2 is formed between a top surface 127a of the first portion 126a and a top surface 127b of the second portion 126b at the joint 125. In some embodiments, D2 is about 120 degrees to about 180 degrees. In the case where D2 is 180 degrees, the top surface 127a of the first portion 126a and the top surface 127b of the second portion 126b are substantially flush (coplanar) with each other at the joint 125. If D2 is too small, delamination defects may occur (e.g., at joints 125 of magnetic layer 126). If D2 is too large, D2 may unnecessarily increase the material of magnetic layer 126 and the cost associated with magnetic layer 126. In the depicted embodiment, magnetic layer 126 is separated from magnetic assembly 114. In some embodiments, although not depicted in FIG. Figure 2, but the magnetic layer 126 is in contact with the magnetic component 114. In such embodiments, the magnetic layer 126 and the magnetic component 114 enclose one or more conductors 106 and the dielectric filler 132.

[0112] In some embodiments, magnetic layer 126 includes one or more magnetic materials, such as a cobalt alloy (e.g., cobalt-zirconium-tantalum (CoZrTa or CZT), CoZr, and / or the like), a nickel alloy (e.g., nickel-iron (NiFe) and / or the like), another magnetic material, or a combination thereof. In some embodiments, magnetic layer 126 includes cobalt, zirconium, tantalum, iron, nickel, or a combination thereof. In some embodiments, magnetic layer 126 includes CoZrTa.

[0113] The semiconductor device 100 disclosed herein may be used in any suitable package, such as a wafer level chip scale package (WLCSP), a flip-chip chip scale package (FCCSP), and a multi-chip module (MCM).

[0114] Figure 3A cross-sectional view of a portion of a package 200 including a semiconductor device 100 according to some embodiments disclosed herein is depicted. The package 200 may be a WLCSP. In some embodiments, the package 200 includes a substrate 202 similar to the substrate 102 described above, an interconnect structure 204 similar to the interconnect structure 104 described above, and the semiconductor device 100. The package 200 may include more than one semiconductor device 100. In some embodiments, the package 200 includes a first conductive feature 215 above the interconnect structure 204 and a second conductive feature 220 above the first conductive feature 215, and a bump 225 above the second conductive feature 220. The first conductive feature 215, the second conductive feature 220, and the bump 225 electrically couple the package 200 with an external circuit. In some embodiments, the bump 225 is a solder bump, a copper bump, or a metal bump including Ni or Au. The first conductive feature 215 and the second conductive feature 220 may include various conductive features, such as under bump metallization (UBM) layers, vias, metal layers, and may include any suitable metal, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), copper (Cu), copper alloys, nickel (Ni), tin (Sn), gold (Au), or combinations thereof. In some embodiments, the package 200 includes a protective layer 210 over the semiconductor device 100, an interconnect structure 204, the first conductive feature 215, and the second conductive feature 220. The protective layer 210 may include a polymer, such as epoxy, PI, BCB, PBO, and the like, although other relatively soft organic dielectric materials may also be used. In some embodiments, the protective layer 210 is formed of a non-organic material selected from the group consisting of un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

[0115] Figure 4 A cross-sectional view of a portion of a package 300 including a semiconductor device 100 according to some embodiments disclosed herein is depicted. Package 300 may be an FCCSP. In some embodiments, package 300 includes a substrate 302 similar to substrate 102 described above. In some embodiments, package 300 includes one or more metal ball structures 315 below substrate 302 for routing to other circuits. Semiconductor device 100 of package 300 is flipped to an inverted position and disposed above substrate 302, such as Figure 4. The semiconductor device 100 may be electrically coupled to the substrate 302 by one or more conductive features 305 below the semiconductor device 100. In some embodiments, the package 300 includes a molded underfill (MUF) 310, which is above the substrate 302 and fills the space between the semiconductor device 100, the one or more conductive features 305, and the substrate 302. In other words, the semiconductor device 100 and the one or more conductive features 305 may be embedded in the MUF 310. In some embodiments, the MUF 310 has a filler. The MUF 310 may be used for protection and insulation purposes. The MUF 310 supports the package 300 and prevents cracks from occurring at the joints between the semiconductor device 100, the one or more conductive features 305, and the substrate 302. In addition, the MUF 310 may also prevent the structures on the substrate 302 from bending (deformation) after thermal cycling due to the mismatch of the coefficients of thermal expansion (CTE) of the materials on the substrate 302. In some embodiments, MUF 310 is made of epoxy resin (amine type, phenol type, anhydride type, etc.), silicon filler, curing agent, additives and / or hardener materials.

[0116] Figure 5A cross-sectional view of a portion of a package 400 including a semiconductor device 100 according to some embodiments disclosed herein is depicted. The package 400 may be an MCM. In some embodiments, the package 400 includes a substrate 402, a semiconductor device 100 as disclosed herein, and another device 500. The substrate 402 is similar to the substrate 102 described above. The device 500 may be any suitable device, such as a logic device, a memory device, a power management device, a radio frequency (RF) device, or other suitable device. The semiconductor device 100 and the device 500 are disposed above the substrate 402 and connected to the substrate 402 by one or more conductive features 405. In some embodiments, the package 400 includes a MUF 410, which is above the substrate 402 and fills the space between the semiconductor device 100, the device 500, the one or more conductive features 405, and the substrate 402. The MUF 410 is similar to the MUF 310 described above. In some embodiments, package 400 includes one or more devices 505 that are below substrate 402 and connected to substrate 402 by conductive features 420. In some embodiments, one or more devices 505 include an integrated passive device (IPD). Package 400 may also include a housing substrate 404 below substrate 402 and connected to substrate 402 by metal ball structures 415, which are similar to metal ball structures 315 described above. Housing substrate 404 may include a printed circuit board (PCB) or the like.

[0117] The various embodiments described herein thus confer several advantages over the prior art. It should be understood that not all advantages have necessarily been discussed herein, no particular advantage is claimed for all embodiments, and other embodiments may confer different advantages. As an example, by having dense copper material in the conductive pads and / or conductors, the semiconductor devices disclosed herein have an improved ability to maintain and / or relieve stress and enhance electrical performance, such as by increasing conductivity and reducing wasted energy. In some examples, the semiconductor device reduces and / or eliminates delamination defects by having optimally specified dimensions (e.g., heights of the conductive pads and conductors, angles D1 and D2), and surface roughness values ​​of the conductive pads and / or conductors. Thus, stresses and any potential cracks in the semiconductor device resulting from delamination defects can be reduced and / or avoided. Additional benefits and / or other advantages will become more apparent to those skilled in the art who benefit from the present disclosure.

[0118] In one example aspect, the present disclosure is directed to a semiconductor device comprising: an interconnect structure over a substrate; a first magnetic layer over the interconnect structure; one or more conductive features over the first magnetic layer; a dielectric layer over the first magnetic layer and the one or more conductive features; and a second magnetic layer over the dielectric layer. The one or more conductive features include a textured top surface.

[0119] In some embodiments, the one or more conductive features include more than 97% copper (111). In some embodiments, a taper angle between the dielectric layer and the first magnetic layer is about 20 to about 40 degrees. In some embodiments, the textured top surface has a surface roughness value of about 50nm to about 90nm. In some embodiments, the dielectric layer is a first dielectric layer, the semiconductor device further includes a second dielectric layer between the one or more conductive features and the first dielectric layer, the first magnetic layer extends beyond an edge of the second dielectric layer, and multiple top surfaces of the second magnetic layer form a step angle of about 120 degrees to about 180 degrees above the edge of the second dielectric layer. In some embodiments, the one or more conductive features have a height of about 5μm to about 18μm. In some embodiments, the interconnect structure includes a top metal wire, the semiconductor device further includes a conductive pad above the top metal wire, the conductive pad includes more than 97% copper (111), and the conductive pad has a height of about 1μm to about 7μm. In some embodiments, the first magnetic layer and the second magnetic layer include a cobalt alloy, a nickel alloy, or a combination thereof. In some embodiments, the dielectric layer includes SiN4, SiN, or a combination thereof.

[0120] In another example aspect, the present disclosure is directed to a semiconductor device, the semiconductor device comprising: a top metal connection above a substrate; a conductive pad above the top metal connection; two conductive features above the conductive pad; a dielectric layer above the two conductive features; and a magnetic layer above the dielectric layer. The top surfaces of the conductive pad and the two conductive features each include a dense copper (Cu) material.

[0121] In some embodiments, a top surface of the two conductive features comprises a textured copper (111) surface having a surface roughness value R3 of about 50 nm to about 90 nm. In some embodiments, a plurality of sidewalls of the two conductive features have a surface roughness value R4 less than R3. In some embodiments, the dense copper material comprises more than 97% copper (111). In some embodiments, the magnetic layer is a first magnetic layer, and the semiconductor device further comprises a second magnetic layer above the conductive pad and below the two conductive features. In some embodiments, the dielectric layer is a first dielectric layer, and the semiconductor device further comprises a second dielectric layer extending horizontally and below the two conductive features; and a third dielectric layer disposed below the first dielectric layer and above the second dielectric layer and the two conductive features. The third dielectric layer has an edge directly above the second dielectric layer, the magnetic layer comprises two top surfaces forming a step angle above the edge, and the step angle is about 120 degrees to about 180 degrees. In some embodiments, the magnetic layer is a first magnetic layer, and the semiconductor device further comprises a second magnetic layer disposed below the second dielectric layer and extending horizontally. In some embodiments, the magnetic layer comprises cobalt zirconium tantalum (CZT), and the dielectric layer comprises SiN4.

[0122] In another example aspect, the present disclosure is directed to a semiconductor device, the semiconductor device comprising two conductive features above a substrate and embedded in a first dielectric layer; the two conductive features and a second dielectric layer above the first dielectric layer; and a magnetic layer above the second dielectric layer. The two conductive features include a copper (Cu) (111) surface having a surface roughness of about 50 nm to about 90 nm.

[0123] In some embodiments, the two conductive features include more than 97% copper (111). In some embodiments, the magnetic layer is a first magnetic layer, the semiconductor device further includes a second magnetic layer disposed below the two conductive features, and an angle between the second dielectric layer and the second magnetic layer is about 20 degrees to about 40 degrees.

[0124] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: an interconnect structure above a substrate; a first magnetic layer above the interconnect structure; one or more conductive features over the first magnetic layer; a dielectric layer over the first magnetic layer and the one or more conductive features; and a second magnetic layer above the dielectric layer, Wherein the one or more conductive features include a textured top surface.

2. The semiconductor device according to claim 1, wherein A taper angle between the dielectric layer and the first magnetic layer is 20 degrees to 40 degrees.

3. The semiconductor device according to claim 1 or 2, wherein: The textured top surface has a surface roughness value of 50 nanometers to 90 nanometers.

4. The semiconductor device according to claim 1 or 2, wherein: wherein the dielectric layer is a first dielectric layer, wherein the semiconductor device further comprises a second dielectric layer between the one or more conductive features and the first dielectric layer, wherein the first magnetic layer extends beyond an edge of the second dielectric layer, and A plurality of top surfaces of the second magnetic layer form a step angle of 120 degrees to 180 degrees above the edge of the second dielectric layer.

5. The semiconductor device according to claim 1 or 2, wherein: The one or more conductive features have a height of 5 microns to 18 microns.

6. A semiconductor device, characterized in that: Include: a top metal connection above a substrate; a conductive pad above the top metal connection; two conductive features above the conductive pad; a dielectric layer over the two conductive features; and a magnetic layer above the dielectric layer, The conductive pad and the two conductive features each include a textured top surface.

7. The semiconductor device according to claim 6, wherein: The magnetic layer is a first magnetic layer, and the semiconductor device further includes a second magnetic layer above the conductive pad and below the two conductive features.

8. The semiconductor device according to claim 6 or 7, wherein: The dielectric layer is a first dielectric layer, and the semiconductor device further comprises: a second dielectric layer extending horizontally and below the two conductive features; and a third dielectric layer disposed below the first dielectric layer and above the second dielectric layer and the two conductive features, wherein the third dielectric layer has an edge directly above the second dielectric layer, wherein the magnetic layer includes two top surfaces forming a step angle above the edge, and The step angle is 120 degrees to 180 degrees.

9. A semiconductor device, characterized in that: Include: two conductive features over a substrate and embedded in a first dielectric layer; The two conductive features and a second dielectric layer over the first dielectric layer; and a magnetic layer above the second dielectric layer, The two conductive features include a textured surface having a surface roughness of 50 nanometers to 90 nanometers.

10. The semiconductor device according to claim 9, wherein: wherein the magnetic layer is a first magnetic layer, The semiconductor device further comprises a second magnetic layer disposed below the two conductive features, An angle between the second dielectric layer and the second magnetic layer is 20 degrees to 40 degrees.

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