3D package stacked chip
By adding a heat dissipation plate on the side walls of the 3D package stacked chip, the problem of insufficient heat dissipation efficiency in the horizontal direction in high-power products is solved, and a more efficient heat dissipation effect is achieved.
Patent Information
- Application Number
- CN202420647011.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-03-29
AI Technical Summary
3D package stacked chips face challenges in heat dissipation design in high-power products, especially inadequate heat dissipation efficiency in the horizontal direction, resulting in poor overall heat dissipation effect.
Add a heat dissipation plate on the side wall of the 3D package stacked chip, transfer heat from the stacked chip part to the heat dissipation plate through the first interface material layer, and dissipate heat in the vertical direction through the radiator, thereby improving the heat dissipation efficiency and heat dissipation of the chip Effect.
By adding a heat dissipation board, the chip's heat dissipation ability in the horizontal direction is improved, and the overall heat dissipation efficiency and heat dissipation effect of the 3D package stacked chip is significantly improved.
Smart Images
Figure CN222462901U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, in particular to the field of chip technology, and specifically to a 3D packaged stacked chip. Background Art
[0002] As the performance of chip products continues to improve, the integration of chips is getting higher and higher, the power density is also increasing, and the overall heat generation is getting higher and higher. It is necessary to passively or actively dissipate heat on the chip to ensure that its temperature is below the specified operating temperature.
[0003] Specifically, the thermal resistance of chip products using 3D packaging stacking technology has always been a focus of the industry. For products with higher power, the heat generated is very large. For products such as high-bandwidth memory, after the processor and high-bandwidth memory are directly stacked using 3D packaging technology, the challenges faced by the heat dissipation design of high-bandwidth memory products will be even greater.
[0004] The technical means described in this section are not necessarily technical means that have been previously conceived or adopted. Unless otherwise specified, it should not be assumed that any technical means described in this section are considered to be prior art simply because they are included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to have been recognized in any prior art. Utility Model Content
[0005] The present disclosure provides a 3D packaged stacked chip.
[0006] According to one aspect of the present disclosure, a 3D packaged stacked chip is provided, comprising: a stacked chip portion, the stacked chip portion having a plurality of stacked sub-chips; a first interface material layer, the inner side of the first interface material layer being adhered to the outer side of the side wall of the stacked chip portion; and a heat sink, the inner side of at least a portion of the heat sink being adhered to the outer side of the first interface material layer.
[0007] In some embodiments, the 3D packaged stacked chip further includes: a heat sink, wherein the heat sink is located on an upper surface of the stacked chip portion.
[0008] In some embodiments, the 3D packaged stacked chip further includes: a base material layer, wherein the base material layer is adhered to the lower surface of the stacked chip portion and constitutes a bottom structure of the 3D packaged stacked chip.
[0009] In some embodiments, the 3D packaged stacked chip further includes: a second interface material layer, the second interface material layer is located between the upper surface of the stacked chip portion and the heat sink, and the second interface material layer is respectively bonded to the upper surface of the stacked chip portion and the heat sink.
[0010] In some embodiments, the heat dissipation plate further includes a second portion in addition to the at least one portion, and an inner side of the second portion is attached to an upper surface of the stacked chip portion.
[0011] In some embodiments, the 3D packaged stacked chip further includes: a third interface material layer, the third interface material layer is located between the second portion of the heat sink and the heat sink, and the third interface material layer is respectively bonded to the second portion of the heat sink and the heat sink.
[0012] In some embodiments, the 3D packaged stacked chip further includes: a packaging material layer, wherein the packaging material layer is adhered to the outer side of the at least a portion of the heat dissipation plate.
[0013] In some embodiments, the inner sides of the first interface material layer are respectively attached to the outside of four side walls of the stacked chip portion.
[0014] In some embodiments, an inner side of the at least a portion of the heat dissipation plate is in contact with a first interface material layer in contact with at least one side wall of the stacked chip portion.
[0015] According to one or more embodiments of the present disclosure, a heat sink is added to the side wall of the 3D packaged stacked chip to increase the heat dissipation of the chip in the horizontal direction, thereby improving the heat dissipation efficiency and effect of the 3D packaged stacked chip.
[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.
[0018] Figure 1A and Figure 1B A side view and a top view of a 3D packaged stacked chip according to some embodiments of the present disclosure are respectively shown;
[0019] Figure 2 A schematic diagram showing the heat dissipation principle of 3D packaged stacked chips according to some embodiments of the present disclosure;
[0020] Figure 3A and Figure 3B A side view and a top view of a 3D packaged stacked chip according to some embodiments of the present disclosure are respectively shown;
[0021] Figure 4 A schematic diagram showing the heat dissipation principle of 3D packaged stacked chips according to some embodiments of the present disclosure;
[0022] Figure 5A and Figure 5B A side view and a top view respectively show a 3D packaged stacked chip according to some embodiments of the present disclosure; and
[0023] Figure 6 A schematic diagram showing 3D packaged stacked chips according to some embodiments of the present disclosure.
[0024] Reference numerals:
[0025] 100-3D package stacked chips
[0026] 101-Stacked Chip Department
[0027] 102-first interface material layer
[0028] 103-Heat Radiator
[0029] 104-Radiator
[0030] 105-base material layer
[0031] 106- second interface material layer
[0032] 107-Encapsulation material layer
[0033] 201-third interface material layer
[0034] 202-Fourth interface material layer DETAILED DESCRIPTION
[0035] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.
[0036] In some related technologies, the heat dissipation solutions for chips focus on optimizing heat dissipation in the vertical direction of the chip, including using interface materials with higher thermal conductivity and reducing the number of heat exchange interfaces inside and outside the chip package, or changing the architecture of the external heat sink of the package, including increasing the volume and weight of the heat sink and increasing the size of the heat sink interface. In some solutions, the internal structure of the external heat sink can also be changed, including adding cooling liquid inside the heat sink and circulating it, and using phase change materials to enhance the heat dissipation capacity of the heat sink.
[0037] The inventors found that the above heat dissipation solution has gradually failed to meet the heat dissipation requirements of high-power server CPUs and GPUs. As the integration of chips increases, the number of stacked chips in 3D packaged stacks is also increasing, and the final 3D packaged stacked chip products have a certain height. Therefore, on the basis of the existing technology for heat dissipation optimization in the vertical direction, it is possible to increase the heat dissipation of the chip in the horizontal direction by adding a heat sink on the side wall of the chip, thereby improving the heat dissipation efficiency and heat dissipation effect of the chip.
[0038] The embodiment of the present disclosure provides a 3D packaged stacked chip, which can improve the heat dissipation efficiency and effect of the 3D packaged stacked chip by adding a heat sink to the side wall of the 3D packaged stacked chip to increase the heat dissipation of the chip in the horizontal direction.
[0039] Figure 1A and Figure 1B The side view and top view of the 3D packaged stacked chips according to some embodiments of the present disclosure are respectively shown.
[0040] like Figure 1A As shown, the 3D packaged stacked chip 100 includes: a stacked chip unit 101, the stacked chip unit having a plurality of stacked sub-chips; a first interface material layer 102, the inner side of the first interface material layer 102 is adhered to the outer side wall of the stacked chip unit 101; and a heat sink 103, the inner side of at least a portion of the heat sink 103 is adhered to the outer side of the first interface material layer 102.
[0041] Thus, the heat generated by each layer of sub-chips in the stacked chip part 101 in the 3D packaged stacked chip 100 can be transferred to the heat sink 103 through the first interface material layer 102 in the horizontal direction, so that the heat is gathered and transferred on the heat sink 103, thereby achieving the purpose of heat dissipation. The 3D packaged stacked chip 100 increases the heat dissipation of the chip in the horizontal direction by adding a heat sink on the side wall, which can improve the heat dissipation efficiency and heat dissipation effect of the 3D packaged stacked chip.
[0042] According to some embodiments, the 3D packaged stacked chip 100 further includes: a heat sink 104 , wherein the heat sink 104 is located on an upper surface of the stacked chip portion 101 .
[0043] According to some embodiments, the 3D packaged stacked chip 100 also includes: a second interface material layer 106, the second interface material layer 106 is located between the upper surface of the stacked chip portion 101 and the heat sink 104, and the second interface material layer 106 is respectively bonded to the upper surface of the stacked chip portion 101 and the heat sink 104.
[0044] like Figure 1AAs shown, the second interface material layer 106 is respectively adhered to the upper surface of the stacked chip portion 101 and the heat sink 104, so that the heat sink 104 is more stably, tightly and firmly fixed above the stacked chip portion 101, and thus the heat sink 104 located above the upper surface of the stacked chip portion 101 can be used for heat dissipation of the 3D packaged stacked chip 100 in the vertical direction.
[0045] In some examples, the projection of the heat sink 104 in the vertical direction can cover the projection of the second interface material layer 106 in the vertical direction, and the projection of the second interface material layer 106 in the vertical direction can cover the sum of the projections of the chip stacking part 101, the first interface material layer 102, and the heat sink 103 in the vertical direction. Such a structure enables the heat sink 104 and the second interface material layer 106 to cover the chip structure located below them to achieve a better heat dissipation effect. Specifically, multiple sub-chips in the stacked chip part 101 can pass through the second interface material layer in the vertical direction and use the heat sink 104 for heat dissipation; the heat transferred in the horizontal direction and accumulated on the heat sink 103 can also pass through the second interface material layer 106 and use the heat sink 104 for heat dissipation, thereby achieving simultaneous heat dissipation of the chip in the horizontal and vertical directions, and improving the heat dissipation efficiency and heat dissipation effect of the chip.
[0046] According to some embodiments, the 3D packaged stacked chip 100 further includes: a base material layer 105 , wherein the base material layer 105 is adhered to the lower surface of the stacked chip portion 101 and constitutes a bottom structure of the 3D packaged stacked chip 100 .
[0047] In some examples, substrate material layer 105 may represent a package substrate chip.
[0048] According to some embodiments, the 3D packaged stacked chip 100 further includes: a packaging material layer 107 , wherein the packaging material layer 107 is attached to the outer side of the at least a portion of the heat dissipation plate 103 .
[0049] In one example, the packaging material layer 107 as the outermost layer of the 3D packaged stacked chip 100 can enhance the robustness of the chip structure and improve the waterproof sealing of the chip.
[0050] Figure 2 A schematic diagram showing the heat dissipation principle of 3D packaged stacked chips according to some embodiments of the present disclosure.
[0051] like Figure 2As shown, when the heat generated by each layer of sub-chips of the stacked chip part 101 in the 3D packaged stacked chip 100 is blocked from being transferred in the vertical direction, it can be transferred to at least a portion of the heat sink 103 through the first interface material layer 101 in the horizontal direction, and then the heat is gathered and transferred on at least a portion of the heat sink 103. Specifically, the heat received by at least a portion of the heat sink 103 can be transferred out through the packaging material layer 107, and the heat can also be transferred to the heat sink 104 from the vertical heat sink 103 through the second interface material layer 106 in the vertical direction.
[0052] Exemplarily, the first interface material layer 102 and the second interface material layer 106 are made of the same interface material, which is used to fit two adjacent structures to achieve a sealed fit, thereby having good airtightness. It is understandable that the thermal conductivity of the packaging material used in the packaging material layer 107 is usually slightly lower than the materials of the first interface material layer 102, the second interface material layer 106 and the heat sink 104. Therefore, the heat received by at least a portion of the heat sink 103 is transferred from the vertical heat sink 103 to the heat sink 104 through the second interface material layer 106 in the vertical direction, which is the main heat transfer path.
[0053] In some examples, the heat sink 103 may be made of a material with high thermal conductivity such as metal, graphene, etc. Meanwhile, increasing the thickness d of the heat sink 103 may effectively increase the heat dissipation of the stacked chip portion 101 .
[0054] In some examples, the interface material used for the first interface material layer 102 and the second interface material layer 106 is a mixture of bonding materials commonly used in the semiconductor industry (for example, epoxy resin-based composite materials or bonding silver paste, etc.) and general interface materials, which can achieve the adhesion of the heat sink 103 to the side wall of the stacked chip part 101 and also have certain thermal conductivity.
[0055] The packaging material layer 107 can effectively package the heat sink 103 and the stacked chip portion 101 to enhance the reliability of the overall structure of the 3D packaged stacked chip 100 .
[0056] In order to further enhance the heat dissipation of the stacked chip unit 101 by the heat dissipation plate 103 , the following implementation may also be adopted. Figure 3A and Figure 3B The side view and top view of the 3D packaged stacked chips according to some embodiments of the present disclosure are respectively shown.
[0057] like Figure 3A As shown, the heat dissipation plate 103 further includes a second portion in addition to the at least one portion, and the inner side of the second portion is attached to the upper surface of the stacked chip portion 101 .
[0058] According to some embodiments, the 3D packaged stacked chip 100 also includes: a third interface material layer 201, wherein the third interface material layer 201 is located between the second portion of the heat sink 103 and the heat sink 104, and the third interface material layer 201 is respectively bonded to the second portion of the heat sink 103 and the heat sink 104; and a fourth interface material layer 202, wherein the fourth interface material layer 202 is located between the second portion of the heat sink 103 and the stacked chip portion 101, and the fourth interface material layer 202 is respectively bonded to the second portion of the heat sink 103 and the stacked chip portion 101.
[0059] Compared to Figure 1A , Figure 3A The heat sink 103 in the embodiment is changed from a single side structure to a structure combining the side and the top. The heat sink 103 is respectively attached to the four side walls of the stacked chip part 101, and on the side walls, the heat sink 103 and the stacked chip part 101 are bonded by a first interface material layer 102. In addition, the heat sink 103 also includes a second part in addition to the at least one part, and the inner side of the second part is bonded to the upper surface of the stacked chip part 101, and the two are bonded by a fourth interface material layer 202.
[0060] Therefore, the second portion of the heat sink 103, ie, the top structural portion, can ensure the mechanical strength of the packaging structure of the 3D packaged stacked chip, and can simultaneously enhance the heat dissipation capability of the chip on the four side walls and the upper surface of the chip.
[0061] Figure 4 A schematic diagram showing the heat dissipation principle of 3D packaged stacked chips according to some embodiments of the present disclosure.
[0062] like Figure 4 As shown, the second part of the heat sink 103, i.e., the top structure part, greatly increases the area of the heat sink 103, and can more effectively receive the heat transferred via the first interface material layer 102 and the fourth interface material layer, and play the role of a heat spreader. At the same time, the larger area of the heat sink means that the heat transfer to the heat sink 104 via the third interface material layer 201 in the vertical direction will be greatly improved. In addition, in this embodiment, no longer using the packaging material layer can enhance the diffusion of heat to the air, so that the heat sink 103 can obtain a larger area and thickness, which can greatly increase the ability to transfer the heat generated by the stacked chip unit 101 in the horizontal direction.
[0063] Figure 5A and Figure 5B 3D packaged stacked chips of some embodiments of the present disclosure are shown in side view and top view respectively. Figure 5A and 5BAs shown in Figure 3A and 3B On the basis of the 3D packaged stacked chip structure shown, a packaging material layer 107 can be further added on the side wall of the chip, so as to effectively package the heat sink 103 and the stacked chip part 101 to enhance the reliability of the overall structure of the 3D packaged stacked chip 100 .
[0064] By using a heat sink 103 outside the side wall of the stacked chip unit 101 and a horizontal heat sink 103 connecting the heat sinks in the vertical direction, and using a packaging material layer 107, the structure can improve heat dissipation and structural strength while ensuring a certain degree of sealing.
[0065] According to some embodiments, the inner sides of the first interface material layer 102 are respectively attached to the outer sides of four side walls of the stacked chip portion 101 .
[0066] According to some embodiments, the inner side of the at least a portion of the heat dissipation plate 103 is in contact with the first interface material layer 102 that is in contact with at least one side wall of the stacked chip portion 101 .
[0067] Figure 6 The side view and top view of the 3D packaged stacked chips with heat dissipation plates added to one side wall, three side walls and four side walls of the stacked chip portion 101 are shown.
[0068] In some embodiments, heat dissipation plates may be added to the upper surface of the stacked chip portion 101 and one side wall, three side walls, and four side walls, respectively, to obtain different 3D packaged stacked chip structures.
[0069] It is understandable that if the top structure of the heat sink 103 does not adopt a full-surface covering structure, the heat dissipation and structural enhancement functions can also be achieved. These solutions can be used to improve the heat dissipation of memory using 3D packaging technology, and can also be used to improve the overall heat dissipation efficiency of products that integrate and package processors and storage chips using 2.5D or 3D packaging technology. The greater the height of the stacked chips and the larger the side of the chip, the more obvious the heat dissipation enhancement effect of the solution provided by the present application.
[0070] The implementation method proposed in this application can effectively improve the heat dissipation performance of products in the above application scenarios or designed with similar stacked chip technology, thereby supporting higher power product design and achieving higher product performance.
[0071] It should be understood that in this specification, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships or dimensions that are based on the orientations or positional relationships or dimensions shown in the accompanying drawings, and these terms are used only for the convenience of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the scope of protection of the present disclosure.
[0072] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0073] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0074] In the present disclosure, unless otherwise expressly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0075] This specification provides many different embodiments or examples that can be used to implement the present disclosure. It should be understood that these different embodiments or examples are purely exemplary and are not intended to limit the scope of protection of the present disclosure in any way. Those skilled in the art can conceive of various changes or replacements based on the disclosure of the present specification, which should all be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection defined by the attached claims.
Claims
1. A 3D packaged stacked chip, characterized in that: The 3D packaged stacked chip comprises: A stacked chip portion, the stacked chip portion having a plurality of stacked sub-chips; A first interface material layer, the inner side of the first interface material layer being attached to the outer side wall of the stacked chip portion; and A heat dissipation plate, wherein at least a portion of the inner side of the heat dissipation plate is attached to the outer side of the first interface material layer.
2. The 3D packaged stacked chip according to claim 1, characterized in that: The 3D packaged stacked chip further includes: A heat sink is located on the upper surface of the stacked chip portion.
3. The 3D packaged stacked chip according to claim 2, characterized in that: The 3D packaged stacked chip further includes: A base material layer is adhered to the lower surface of the stacked chip portion and constitutes a bottom structure of the 3D packaged stacked chip.
4. The 3D packaged stacked chip according to claim 2 or 3, characterized in that: The 3D packaged stacked chip further includes: The second interface material layer is located between the upper surface of the stacked chip portion and the heat sink, and the second interface material layer is respectively attached to the upper surface of the stacked chip portion and the heat sink.
5. The 3D packaged stacked chip according to claim 2 or 3, characterized in that: The heat dissipation plate further includes a second portion other than the at least one portion, and an inner side of the second portion is attached to an upper surface of the stacked chip portion.
6. The 3D packaged stacked chip according to claim 5, characterized in that: The 3D packaged stacked chip further includes: a third interface material layer, the third interface material layer being located between the second portion of the heat dissipation plate and the heat sink, and the third interface material layer being respectively attached to the second portion of the heat dissipation plate and the heat sink; and A fourth interface material layer is located between the second portion of the heat sink and the stacked chip portion, and the fourth interface material layer is respectively attached to the second portion of the heat sink and the stacked chip portion.
7. The 3D packaged stacked chip according to any one of claims 1 to 3, characterized in that: The 3D packaged stacked chip further includes: A packaging material layer is attached to the outer side of at least a portion of the heat sink.
8. The 3D packaged stacked chip according to any one of claims 1 to 3, characterized in that: The inner sides of the first interface material layer are respectively attached to the outside of the four side walls of the stacked chip portion.
9. The 3D packaged stacked chip according to claim 8, characterized in that: The inner side of the at least a portion of the heat dissipation plate is in contact with a first interface material layer in contact with at least one side wall of the stacked chip portion.